CN114968540B

CN114968540B - A frequency adjustment method for internuclear migration

Info

Publication number: CN114968540B
Application number: CN202110200336.2A
Authority: CN
Inventors: 沈日胜; 许虎
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-02-23
Filing date: 2021-02-23
Publication date: 2025-02-07
Anticipated expiration: 2041-02-23
Also published as: WO2022179473A1; CN114968540A

Abstract

The embodiment of the application provides a frequency adjustment method for inter-core migration, wherein electronic equipment determines that expected computing capacity corresponding to a current load of a first processor core is larger than a first preset value, migrates a first task in a first task queue of the first processor core to a second task queue of a second processor core, records the first computing capacity corresponding to the current frequency of the first processor core and a first migration type of the first task, determines the first frequency of the second processor core corresponding to the first computing capacity when the first task is determined to be a new task of the first migration type when the electronic equipment schedules the first task in the second task queue, and adjusts the frequency of the second processor core to be the first frequency when the current frequency of the second processor core is smaller than a second preset value, wherein the second preset value is determined based on the first frequency. Therefore, the quick frequency raising of the target processor core after the inter-core migration can be realized, and the response speed of the electronic equipment to the inter-core migration task is effectively improved.

Description

Frequency adjustment method for inter-core migration

Technical Field

The application relates to the technical field of terminals, in particular to a frequency adjustment method for inter-core migration.

Background

With the development of technology, the functions supported by electronic devices such as smart phones and tablet computers are more and more abundant, and users can use various APP at the smart terminals. Aiming at the electronic equipment of the multi-core processor, in order to ensure the performance of the electronic equipment and further meet the user experience, the electronic equipment is required to carry out resource scheduling and task scheduling aiming at the load condition of each processor core. In the conventional technology, an electronic device generally uses a load statistics algorithm to periodically count load contributions of tasks to a system based on a load (capability) condition of a currently executed task in a previous period, and performs resource scheduling based on the load contributions. For example, the processor core is frequency adjusted, the frequency of the processor core is increased when the load of the current execution task of the processor core is increased, and the frequency of the processor core is decreased when the load of the current execution task of the processor is decreased. In summary, the load statistics of the conventional technology have a certain hysteresis, and correspondingly, the frequency adjustment also has a certain hysteresis.

For example, for an electronic device of a multi-core CPU, when the load of the CPU core 1 is excessive, the task of the CPU core 1 may be migrated to the CPU core 2 with a lighter load. Aiming at a task needing quick response, the current frequency modulation mode cannot meet the performance requirement of the task after inter-core migration.

Disclosure of Invention

The application provides a frequency adjustment method for inter-core migration, which can realize the rapid frequency raising of a target processor core after the inter-core migration of a task, and effectively improve the response speed of electronic equipment to the inter-core migration task.

According to the method, when the electronic device schedules the first task in the second task queue, when the first task is determined to be a new task of the first migration type in the second task queue, the first frequency of the second processor core corresponding to the first computing capacity is determined, when the current frequency of the second processor core is smaller than a second preset value, the frequency of the second processor core is adjusted to be the first frequency, and the second preset value is determined based on the first frequency.

In the embodiment of the application, when the electronic device determines that the computing capacity of the current processor core cannot meet the expected computing capacity corresponding to the current load, the electronic device migrates the first task in the task queue of the processor core to other target processor cores with stronger computing capacities, and records the current computing capacity of the source processor core and migration types of the tasks. In this way, when the electronic device schedules the first task, if it is determined that the first task is a new task of inter-core migration of the first migration type, the expected frequency of the target processor core is calculated based on the current computing capability, and the frequency of the target processor core is adjusted to the expected frequency if the current frequency of the target processor core is smaller than the expected frequency. Therefore, the quick frequency raising of the target processor core after the inter-core migration is realized, the response speed of the electronic equipment to the first task is effectively improved, and the blocking condition of the electronic equipment after the task migration is avoided.

In one possible implementation manner, when the first task is determined to be a new task of the first migration type in the second task queue, determining the first frequency of the second processor core corresponding to the first computing capability includes determining the first frequency of the second processor core corresponding to the first computing capability when the first task is determined to be a new task of the first migration type in the second task queue and the first task is determined to be a task of the first type.

In the embodiment of the present application, the first type of task may refer to a critical task. The various tasks performed by the electronic device include critical tasks and non-critical tasks. The electronic equipment can carry out resource management and control in different modes on the critical tasks and the non-critical tasks, and the inter-core migration frequency adjustment method provided by the embodiment of the application can respond to the critical tasks in time only for the critical tasks and maximize the resource utilization rate.

In one possible implementation manner, the migration of the first task in the first task queue of the first processor core to the second task queue of the second processor core and recording the first computing capacity corresponding to the current frequency of the first processor core and the first migration type of the first task includes migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core and determining the first computing capacity corresponding to the current frequency of the first processor core when the first task performs context switching, and recording the computing capacity corresponding to the current frequency of the source processor core of the first task as the first computing capacity in the context of the first task and the migration type of the first task as the first migration type. In this way, during the context switch process of the first task, the first computing capability and the first migration type are recorded in the context of the first task, so that the recording of the two parameters and the subsequent calling are facilitated.

In one possible implementation manner, the migration of the first task in the first task queue of the first processor core to the second task queue of the second processor core and recording the first computing capacity corresponding to the current frequency of the first processor core and the first migration type of the first task includes migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, determining whether the first computing capacity corresponding to the current frequency of the first processor core and the first task are tasks of a first type when the first task is subjected to context switching, and recording whether the computing capacity corresponding to the current frequency of the source processor core of the first task is the first computing capacity, the migration type of the first task is the first migration type and the first task information in the context of the first task, wherein the first task information is used for representing whether the first task is the task of the first type. In this way, in the context switching process of the first task, the first computing capability, the first migration type and the first task information are recorded in the context of the first task, so that the recording of the two parameters and the subsequent calling are facilitated.

The method is not limited to recording the first computing capability, the first migration type and the first task information in the context of the first task, but the embodiment of the application may also record the information in other storage modules, which is not limited herein.

In one possible implementation manner, when the first task is determined to be a new task of the first migration type in the second task queue, determining the first frequency of the second processor core corresponding to the first computing capability includes acquiring the migration type of the first task and first task information from a context of the first task when the first task is determined to be the new task in the second task queue, and acquiring the current computing capability of the source processor core of the first task when the first task is migrated from the context of the first task when the first task is determined to be the first migration type and the first task information represents the task of the first type when the first task is determined to be the first migration type, wherein the current computing capability of the source processor core of the first task is the first computing capability, and the electronic device determines the first frequency of the second processor core corresponding to the first computing capability. Thus, when the current frequency of the second processor core is smaller than the expected frequency (namely the first frequency) of the first task, the frequency of the second processor core can be quickly adjusted to the expected frequency, so that the first task can quickly raise the frequency of the second processor core after inter-core migration, and the first task can be responded in time.

In one possible implementation manner, the electronic device records the running time of each task in the second task queue in the second processor core, and determines that the first task is a new task in the second task queue, including determining that the first task is a new task in the second task queue when the running time of the first task recorded by the electronic device in the second processor core is zero.

In one possible implementation, the first preset value is equal to the maximum computing power of the first processor core, or the first preset value is equal to k1 times the maximum computing power of the first processor core, where k1 is greater than zero and less than 1. For example, k1 takes a value of 0.9.

In one possible implementation, the second preset value is equal to the first frequency, or the second preset value is equal to k2 times the first frequency, where k2 is greater than zero and less than 1. For example, k2 has a value of 0.95.

In one possible implementation manner, the first type of task includes a task of a specified type and a task strongly related to the task of the specified type, or the first type of task includes a task of a specified type of an application corresponding to the top application group and the foreground group and a task strongly related to the task of the specified type, and the task of the specified type includes at least one of a drawing task, a data downloading task and a data uploading task.

In one possible implementation, the first type of task includes a task of a specific application, or the first type of task includes a task of a specific application corresponding to a top application group and a foreground group, and the specific application includes at least one of a game application, a navigation application, and a video application.

In a second aspect, the present application provides a terminal comprising one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, the one or more memories being operable to store computer program code comprising computer instructions that, when executed by the one or more processors, cause the communications apparatus to perform the method of any of the possible implementations of the first aspect described above.

In a third aspect, embodiments of the present application provide a computer storage medium comprising computer instructions which, when run on an electronic device, cause a communications apparatus to perform the method of any one of the possible implementations of the first aspect.

In a fourth aspect, embodiments of the present application provide a computer program product for, when run on a computer, causing the computer to perform the method of any one of the possible implementations of the first aspect.

Drawings

In order to more clearly describe the technical solution in the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be described below.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a system architecture of a CPU according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a control group tree according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a periodic step-up frequency according to an embodiment of the present application;

FIG. 5 is a frequency-raising schematic diagram of a target CPU core after inter-core migration according to an embodiment of the present application;

fig. 6 is a flow chart of a method for adjusting frequency of inter-core migration according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a WALT algorithm time window according to an embodiment of the present application;

FIG. 8 is a frequency-raising schematic diagram of a target CPU core after inter-core migration according to an embodiment of the present application;

fig. 9 is a schematic diagram of a software architecture according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.

The terminology used in the following embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. In the description of the embodiment of the present application, unless otherwise indicated, "/" means or, for example, a/B may represent a or B, and "and/or" in the text is merely an association relationship describing an association object, which means that three relationships may exist, for example, a and/or B, and that three cases of a alone, a and B together, and B alone exist, and further, in the description of the embodiment of the present application, "a plurality" means two or more.

The terms "first," "second," and the like, are used below for descriptive purposes only and are not to be construed as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature, and in the description of embodiments of the application, unless otherwise indicated, the meaning of "a plurality" is two or more.

First, an electronic device provided in an embodiment of the present application is described. Fig. 1 exemplarily shows a schematic structural diagram of an electronic device 100.

The electronic device 100 may be a cell phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, ultra-mobile personal computer (UMPC), netbook, and cellular telephone, personal Digital Assistant (PDA), augmented reality (augmented reality, AR) device, virtual Reality (VR) device, artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) device, wearable device, vehicle-mounted device, smart home device, and/or smart city device, and the specific type of the electronic device is not particularly limited by the embodiments of the present application.

The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (application processor, AP), a modem processor, a central processor (central processing unit, CPU), a graphics processor (graphics processing unit, GPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a memory, a video codec, a digital signal processor (DIGITAL SIGNAL processor, DSP), a baseband processor, and/or a neural-network processing unit, NPU, etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

In the embodiment of the application, the processor takes the rising edge of the clock pulse as the reference for executing the instruction, so that the higher the clock frequency of the processor, the more instructions are executed in unit time of the processor, and the faster the working speed.

The CPU is a final execution unit for information processing and program running. The CPU mainly comprises an arithmetic unit (ARITHMETIC LOGIC UNIT, ALU), a Cache (Cache) and a Bus (Bus) for realizing Data (Data), control and state of the connection between the arithmetic unit and the Cache. In the computer architecture, a CPU is a core hardware unit that performs control allocation and general-purpose operations on all hardware resources (such as a memory and an input/output unit). The operation of all software layers in the computer system will ultimately be mapped by the instruction set into the operation of the CPU. The operating frequency of the CPU is an important parameter for CPU performance, and is very important for improving the operation speed of the CPU.

The processor (e.g., CPU) according to the embodiments of the present application may be a multi-core processor, where a multi-core processor refers to two or more complete compute engines integrated into one processor, where the processor can support multiple processors on a system bus, and all bus control signals and command signals are provided by a bus controller. In the embodiment of the present application, the above-mentioned computing engine may be simply referred to as a kernel or a processor core.

In the embodiment of the present application, when the maximum computing capability of the processor core 1 cannot meet the expected computing capability corresponding to the current load of the processor core 1, the electronic device 100 may migrate the task 1 in the processor core 1 to the processor core 2 with a lower load, and record the current computing capability of the processor core 1 and the migration type of the task 1 when the task context is switched. Based on the current computing capability of the processor core 1 and the migration type of the task 1, the electronic device 100 can realize rapid frequency boosting after task migration, and effectively improve the response speed of the electronic device to the task migrated between cores, especially the response speed of the key task for inter-core migration.

The controller may be a neural hub and command center of the electronic device 100. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-INTEGRATED CIRCUIT, I2C) interface, an integrated circuit built-in audio (inter-INTEGRATED CIRCUIT SOUND, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface 130 may be used to connect a charger to charge the electronic device 100, and may also be used to transfer data between the electronic device 100 and a peripheral device. And can also be used for connecting with a headset, and playing audio through the headset. The interface may also be used to connect other electronic devices, such as AR devices, etc.

It should be understood that the interfacing relationship between the modules illustrated in the embodiments of the present application is only illustrative, and is not meant to limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also employ different interfacing manners in the above embodiments, or a combination of multiple interfacing manners.

The charge management module 140 is configured to receive a charge input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 140 may receive a charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charge management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. The charging management module 140 may also supply power to the electronic device through the power management module 141 while charging the battery 142.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, impedance) and other parameters. In other embodiments, the power management module 141 may also be provided in the processor 110. In other embodiments, the power management module 141 and the charge management module 140 may be disposed in the same device.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution for wireless communication including 2G/3G/4G/5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (low noise amplifier, LNA), etc. The mobile communication module 150 may receive electromagnetic waves from the antenna 1, perform processes such as filtering, amplifying, and the like on the received electromagnetic waves, and transmit the processed electromagnetic waves to the modem processor for demodulation. The mobile communication module 150 can amplify the signal modulated by the modem processor, and convert the signal into electromagnetic waves through the antenna 1 to radiate. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be provided in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used for demodulating the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low frequency baseband signal to the baseband processor for processing. The low frequency baseband signal is processed by the baseband processor and then transferred to the application processor. The application processor outputs sound signals through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays images or video through the display screen 194. In some embodiments, the modem processor may be a stand-alone device. In other embodiments, the modem processor may be provided in the same device as the mobile communication module 150 or other functional module, independent of the processor 110.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (WIRELESS FIDELITY, wi-Fi) network), bluetooth (BT), global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS), frequency modulation (frequency modulation, FM), near field communication (NEAR FIELD communication, NFC), infrared (IR), etc., applied to the electronic device 100. The wireless communication module 160 may be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2.

In some embodiments, antenna 1 and mobile communication module 150 of electronic device 100 are coupled, and antenna 2 and wireless communication module 160 are coupled, such that electronic device 100 may communicate with a network and other devices through wireless communication techniques. The wireless communication techniques can include the Global System for Mobile communications (global system for mobile communications, GSM), general packet radio service (GENERAL PACKET radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation SATELLITE SYSTEM, GLONASS), a beidou satellite navigation system (beidou navigation SATELLITE SYSTEM, BDS), a quasi zenith satellite system (quasi-zenith SATELLITE SYSTEM, QZSS) and/or a satellite based augmentation system (SATELLITE BASED AUGMENTATION SYSTEMS, SBAS).

The electronic device 100 implements display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) CRYSTAL DISPLAY, an organic light-emitting diode (OLED), an active-matrix organic LIGHT EMITTING diode (AMOLED), a flexible light-emitting diode (FLED), miniled, microLed, micro-oLed, a quantum dot LIGHT EMITTING diode (QLED), or the like. In some embodiments, the electronic device 100 may include 1 or N display screens 194, N being a positive integer greater than 1.

The electronic device 100 may implement photographing functions through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, and the like.

The ISP is used to process data fed back by the camera 193. For example, when photographing, the shutter is opened, light is transmitted to the camera photosensitive element through the lens, the optical signal is converted into an electric signal, and the camera photosensitive element transmits the electric signal to the ISP for processing and is converted into an image visible to naked eyes. ISP can also optimize the noise, brightness and skin color of the image. The ISP can also optimize parameters such as exposure, color temperature and the like of a shooting scene. In some embodiments, the ISP may be provided in the camera 193.

The camera 193 is used to capture still images or video. The object generates an optical image through the lens and projects the optical image onto the photosensitive element. The photosensitive element may be a charge coupled device (charge coupled device, CCD) or a Complementary Metal Oxide Semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, which is then transferred to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV, or the like format. In some embodiments, electronic device 100 may include 1 or N cameras 193, N being a positive integer greater than 1.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 100 selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.

Video codecs are used to compress or decompress digital video. The electronic device 100 may support one or more video codecs. Thus, the electronic device 100 may play or record video in a variety of encoding formats, such as moving picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, and the like.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent recognition of the electronic device 100, for example, image recognition, face recognition, voice recognition, text understanding, etc., can be realized through the NPU.

The internal memory 121 may include one or more random access memories (random access memory, RAM) and one or more non-volatile memories (NVM).

The random access memory may include a static random-access memory (SRAM), a dynamic random-access memory (dynamic random access memory, DRAM), a synchronous dynamic random-access memory (synchronous dynamic random access memory, SDRAM), a double data rate synchronous dynamic random-access memory (double data rate synchronous dynamic random access memory, DDR SDRAM, such as fifth generation DDR SDRAM is commonly referred to as DDR5 SDRAM), etc.;

The nonvolatile memory may include a disk storage device, a flash memory (flash memory).

The FLASH memory may include NOR FLASH, NAND FLASH, 3D NAND FLASH, etc. divided according to an operation principle, may include single-level memory cells (SLC-LEVEL CELL), multi-level memory cells (multi-LEVEL CELL, MLC), triple-level memory cells (LEVEL CELL, TLC), quad-LEVEL CELL, QLC), etc. divided according to a memory cell potential order, may include general FLASH memory (english: universal FLASH storage, UFS), embedded multimedia memory card (eMMC) MEDIA CARD, eMMC), etc. divided according to a memory specification.

The random access memory may be read directly from and written to by the processor 110, may be used to store executable programs (e.g., machine instructions) for an operating system or other on-the-fly programs, may also be used to store data for users and applications, and the like.

The nonvolatile memory may store executable programs, store data of users and applications, and the like, and may be loaded into the random access memory in advance for the processor 110 to directly read and write.

The external memory interface 120 may be used to connect external non-volatile memory to enable expansion of the memory capabilities of the electronic device 100. The external nonvolatile memory communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music and video are stored in an external nonvolatile memory.

The electronic device 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

In order to facilitate understanding of the technical solutions provided by the embodiments of the present application, the following briefly describes concepts that may be involved.

Task (task) migration-task scheduling only needs to solve the problem of switching between different tasks for an operating system with a single processor core. For operating systems having multiple processor cores, task scheduling includes handling the allocation of multiple tasks across the multiple processor cores and the migration of tasks between the different processor cores in addition to enabling switching between different tasks of the same processor core. The task migration refers to that the electronic device 100 migrates the task 1 from the task queue of the processor core 1 to the task queue of the processor core 2 based on one or more pieces of information such as the load of the task 1 in the processor core 1, the grouping of the task 1, the running state of the task 1, and the load information of the processor core 1. The task migration may be for implementing load balancing between different processor cores, or for quickly meeting the resource requirement of a specific task, which is not particularly limited in the embodiment of the present application.

The large core and the small core are limited by heat dissipation and power consumption, and hardware devices such as a processor and the like cannot continuously maintain to work at a high-performance working frequency. For better balancing the performance and power consumption relationships, a size core architecture, such as big. Littale architecture, is proposed. In general, a large core (big cores) in a large-small core architecture refers to a processor core with higher power consumption and better performance, a small core (little cores) in a large-small core architecture refers to a processor core with lower power consumption and lower performance, the main frequencies of the large core and the small core are different, and for the same task amount, the execution time of the small core is far higher than that of the large core. In some large and small core architectures, in addition to large and small cores, a middle core may be included, with the middle core having higher performance than the small core and lower performance than the large core, and the middle core having higher power consumption than the small core and lower power consumption than the large core.

In some embodiments of the present application, the electronic device 100 may assign a new task to a corelet first as the new task is assigned, and then the electronic device 100 schedules the task by tracking the load change of the task. When the load of the task in the middle core is too heavy, the task can be migrated from the middle core to the large core to run, and when the load of the task in the small core is too heavy, the task can be migrated from the middle core to the large core to run, so that the resource requirement of the task can be timely met, and better performance experience can be obtained. On the contrary, when the load of the task in the big core is reduced, the task can be migrated from the big core to the middle core or the small core to run, when the load of the task in the middle core is reduced, the task can be migrated from the middle core to the small core to run, and thus, the running speed is ensured, and the power consumption can be saved.

In one implementation, when a task is overloaded in a corelet, the task may be migrated from the corelet to the corelet, and when the corelet cannot meet the resource requirements of the task, the task may be migrated from the corelet to the corelet. In another implementation, for a task that needs to respond quickly, when the load of the small core is too heavy, the task can be directly migrated from the small core to the large core, so as to quickly meet the resource requirement of the task and avoid the electronic device from being blocked. The embodiment of the present application is not particularly limited thereto.

The multi-core processor according to the embodiment of the present application may be a multi-core CPU, or may be other multi-core processors, which is not specifically limited herein. Taking a multi-core CPU as an example, the inter-core migration frequency adjustment method provided by the embodiment of the application is introduced.

First, a system architecture of the multi-core CPU scheduling system will be described.

Fig. 2 exemplarily shows a system architecture of the CPU scheduling system to which the present application relates. As shown in fig. 2, the system includes a CPU run queue (CPU Runqueue), a Context Switch (Context Switch), a Main scheduler (Main scheduler), a periodic scheduler (Tick scheduler), load balancing (Load scheduler), a deadline scheduler (deadline scheduler, DL), a poll scheduler (realtime scheduler, RT), a full-fair scheduler (completely fair scheduler, CFS), an Idle scheduler (Idle scheduler), and a preemptive scheduler (stop scheduler). The CPU scheduling system shown in FIG. 2 may also include a custom scheduler. In the embodiment of the application, the CPU core may also be simply referred to as a CPU. Wherein:

Each CPU (or each CPU core in a multi-core CPU) maintains a respective run queue (runqueue), each of which may include one or more processes in a sleep (sleep) state or a runnable (runable) state. An runnable state refers to running on a CPU or waiting for a CPU to schedule running in a run queue. A process may include a plurality of threads, where the process is a basic unit of operating system resource allocation, and the threads are basic units of task scheduling and execution, and a scheduling entity corresponding to a task may be a process or a thread.

In the embodiment of the application, the task queue of the CPU can comprise a running queue, a waiting queue and a ready queue. When the process has running conditions but cannot run due to not occupying the CPU, the process is in a ready state and is positioned in a ready queue, and when the process cannot run due to the process itself and has running conditions after certain event must be waited, the process is in a waiting state and is positioned in a waiting queue. The process may switch between an executable state, a ready state, and a wait state.

The scheduler is used for distributing CPU time slices for each task, minimizing response time for real-time tasks, and simultaneously maximizing the overall utilization rate of the CPU. The schedulers include a Main scheduler (Main scheduler) and a periodic scheduler (tick scheduler). The main scheduler is used for activating the scheduling class to execute task scheduling when the process enters a sleep state or abandons the current CPU for other reasons, and the periodic scheduler is used for activating the scheduling class responsible for the current process to execute task scheduling at a fixed frequency so as to ensure the concurrency of the system.

The context of the CPU includes information about the CPU registers and the procedural technologists. The CPU register is a memory with minimum capacity but extremely high speed built in the CPU, and the program counter is used to store the position of the instruction being executed by the CPU or the position of the next instruction to be executed. Context switching refers to storing the context of the previous task in the system kernel, then loading the context of the new task into the registers and the program counter, and finally jumping to the position pointed by the program counter to run the new task.

Currently, the CPU scheduling system includes 5 scheduling classes shown in fig. 2, namely stop_ sched _class, dl_ sched _class, rt_ sched _class, fair_ sched _class and idle_ sched _class, each scheduling class may correspond to different scheduling policies, and the scheduling policies of different classes of processes are different. The task scheduling situation of the CPU may include four situations (1) when one process is switched from an operation state to a waiting state, (2) when one process is switched from an operation state to a ready state, (3) when one process is switched from a waiting state to a ready state, and (4) when one process is terminated.

In the embodiment of the present application, the electronic device 100 may combine the computing capability of the CPU to schedule the tasks in the task queue. The computational power of the CPU is a quantification of CPU performance (normalize), and the current computational power of the CPU is determined based on the frequency at which the CPU is currently running. In one implementation, the maximum computing power corresponding to the highest frequency of the CPU with the strongest performance in one multi-core CPU is set to 1024, and then the computing power corresponding to each frequency point of the CPU and other CPUs is quantized based on the computing power corresponding to the highest frequency. For example, when the frequency of the CPU is half of the highest frequency, the computing power of the CPU is equal to 512. It can be appreciated that, to facilitate task scheduling between CPUs, the operating system of the electronic device 100 may perform numerical quantization on the computing power of different CPUs at different frequency points, and through the current computing power value of the CPU, may also reversely infer the frequency at which the CPU is currently running.

In the embodiment of the present application, the electronic device 100 may group all processes through a control group (cgroup), and then allocate and control resources to the whole group. Specifically, each cgroup may include one or more processes, or may not include any processes. By way of example, FIG. 3 shows a schematic diagram of a hierarchy level (hierarchy) which may be understood as a cgroup tree with hierarchical relationships, one cgroup for each node of the tree, and with reference to FIG. 3, an exemplary process tree includes a top-level application (top-app) group, a foreground (foreground) group, a system-background (background) group, and a background (background) group. In the Android system, applications (also referred to as tasks or processes) may be divided into different cgroup based on their foreground and background states, so that the scheduler class corresponding to cgroup to which the application belongs is executed.

The electronic device 100 may indicate cgroup bound CPUs through cpuset, and may also select the bound CPU cores through schedtune, i.e., may indicate that cgroup is bound to a large core CPU, a medium core CPU, and/or a small core CPU through schedtune, so that the electronic device 100 schedules by checking different cgroup CPUs with different processing capabilities.

In the embodiment of the present application, the electronic device 100 may adjust the frequency of the CPU core according to the load condition of the CPU core. For example, when the electronic apparatus 100 determines that the load of one CPU core is large, the frequency of the CPU core may be increased, and when the electronic apparatus 100 determines that the load of one CPU core is small, the frequency of the CPU core may be reduced.

The user has burstiness and intermittence in the operation of the electronic device 100, while the corresponding tasks have burstiness and short-term high demands on the resources. However, current load statistics algorithms (such as PELT and WALT) use a periodic accumulation calculation method, that is, periodically counting the load of the current CPU core (i.e., cpu_utel, for convenience of description, hereinafter simply referred to as the current load of the CPU core) based on the load condition of each task that has been executed for a period of time, which results in a certain hysteresis of the load statistics, and an actual load mutation needs a certain period to be fed back on the data, so that the frequency of the CPU core is increased and also shows a periodic step-up. Since the load statistics period for counting the current load of the CPU core is often longer (for example, the load statistics period corresponding to WALT algorithm is 20ms by default), the frequency raising speed is slower. Especially, tasks with short time and high demands, such as User Interface (UI) related tasks (e.g., drawing tasks), the current load statistics algorithm cannot meet the fast response requirement of the tasks. Illustratively, a task is added to an idle CPU core, load statistics is performed by using WALT algorithm, and the frequency of the CPU core is increased in a periodic step-like manner as shown in fig. 4 along with the periodic statistics of the load.

For example, as shown in fig. 5, when the CPU core 1 runs the task 1, if it is determined that the computing power of the CPU core 1 (e.g., the small core CPU) cannot bear the load of all the tasks in the task queue of the CPU core 1, the scheduler may migrate the task 1 to the CPU core 2 (e.g., the large core CPU) with higher computing power. Because the load statistics algorithm adopts a periodic accumulation calculation mode, the actual load change can be fed back on the data after a certain period, if the current load of the CPU core 2 is smaller (correspondingly, the frequency is lower) before the task 1 is added into the task queue of the CPU core 2, after the task 1 is added into the task queue of the CPU core 2, the CPU core 2 starts to operate a plurality of load statistics periods of the task 1, the counted load applied by the task 1 to the CPU can be close to the actual load condition of the task 1, and accordingly, the frequency adjusted by the CPU core 2 can meet the frequency required by the task 1. Referring to fig. 5, after the task 1 is migrated into the CPU core 2, the frequency raising speed of the CPU core 2 is slower, and the requirement of the task 1 cannot be met rapidly. In this way, the response speed of the electronic device 100 to the task 1 is slow, and the electronic device 100 may get stuck when the CPU core 2 runs the task 1.

The embodiment of the application provides a frequency adjustment method for inter-core migration, when electronic device 100 determines that the maximum computing capacity of the current CPU core cannot meet the expected computing capacity corresponding to the current load of the CPU core, it migrates task 1 in a task queue of the CPU core to other target CPU cores with stronger computing capacities and lower loads, and records the current computing capacity of a source CPU core of task 1 and migration type (i.e., first migration type) of task 1. When the electronic device 100 schedules the task 1, if it is determined that the task 1 is a new task of inter-core migration of the first migration type, the electronic device 100 calculates a desired frequency of a corresponding target CPU core based on the current computing capability 1, and then adjusts the frequency of the target CPU core to the desired frequency. In this way, the rapid frequency raising of the target CPU core after the inter-core migration is realized, the response speed of the electronic equipment 100 to the task 1 is effectively improved, and the jam condition of the electronic equipment 100 after the task migration is avoided. The following describes the inter-core migration frequency adjustment method provided by the embodiment of the application in detail.

Fig. 6 is a schematic flow chart of a method for adjusting frequency of inter-core migration according to an embodiment of the present application, where the method includes, but is not limited to, steps S101 to S107. Wherein:

s101, the electronic device 100 counts the expected computing power 1 corresponding to the current load 1 of the CPU core 1.

In the embodiment of the present application, the current load of the CPU core 1 is periodically counted by a load counting algorithm (for example, a PLET algorithm and WALT algorithm), and the expected computing capacity of the CPU core 1 corresponding to the current load of the CPU core 1 is determined.

It should be noted that, the PLET algorithm and WALT algorithm track loads for the scheduling entity (i.e. process or thread) corresponding to each task, and the current load of each CPU core is the statistical value of the loads corresponding to all tasks in the task queue of the CPU core. The loads applied to the system by the tasks with different priorities are different, and the priorities of each task are considered by the PELT algorithm and the WALT algorithm, and the statistical value of the corresponding loads of all the tasks can be a weighted statistical value of the corresponding loads of each task, and the load weight of the corresponding loads of each task is determined based on the priorities of the tasks.

In some embodiments, the electronic device 100 uses WALT algorithm for load statistics. The WALT algorithm divides time into a plurality of time windows (windows) according to a certain time length, and can predict window loads of a task in a current time window according to load conditions of N previous time windows of the task. For example, referring to fig. 7, one time WINDOW SIZE (window_size) is 20ms, and each time WINDOW includes 5 time WINDOWs. Step S101 may specifically include steps S1 to S4. Wherein:

s1, periodically counting window loads of tasks 1 in a task queue of the CPU core 1 in each time window by the electronic device 100.

In some embodiments, based on the physical time during which task 1 is in an operational state on CPU core 1 within a time window, electronic device 100 may acknowledge the window load of task 1 during the time window (the window load may also be referred to as walt _time). In one implementation, the window load of task 1 over the time window may be expressed as delta (cur_freq1/max_freq) (cur_ipc1/max_ipc).

Wherein delta represents the physical time of the task 1 in the operable state on the CPU core 1 in the time window, cur_freq1 represents the current frequency of the CPU core 1, max_freq represents the maximum CPU frequency in the multi-core CPU system, cur_ipc1 represents the computing efficiency of the CPU core 1, and max_ipc represents the maximum computing efficiency in the multi-core CPU system.

The calculation efficiency of each CPU core is a fixed value determined in advance based on the hardware performance. In general, the electronic apparatus 100 stores a file containing the calculation efficiency of each CPU core, and the electronic apparatus 100 can acquire the calculation efficiency of the CPU core 1 and the above maximum calculation efficiency by referring to the above file.

S2, at the starting moment of the time window 1, based on window loads of the first N time windows of the time window 1 of the task 1, the electronic device 100 determines a task demand (TASK DEMAND) value of the time window 1 of the task 1 by using a specified value policy.

In the embodiment of the application, the value taking strategy can comprise the steps of taking an average value, taking a latest value, taking the maximum value and taking the minimum value among the average value and the latest value. The electronic device 100 may configure the value policy of WALT algorithm through a configuration interface in a user state. The electronic device 100 may determine which negative-valued policy to use specifically based on different system performance, power consumption requirements, etc., and is not specifically limited herein. It should be noted that, the task requirement (TASK DEMAND) of the task 1 in the time window 1 determined by the electronic device 100 using the specified value policy is the window load of the task 1 in the time window 1 predicted by the electronic device 100.

For example, as shown in fig. 7, N has a value of 5, and the statistical window loads of task 1 in the first 5 time windows of time window 1 are 7, 14, 3, 6, and 9, respectively. The five values of the above-mentioned average value, the latest value, the maximum value of the average value and the latest value, the maximum value and the minimum value are taken, and the task requirement values of the corresponding task 1 in the time window 1 are respectively 14, 7.8, 9 and 3.

S3, predicting the current load 1 of the CPU core 1 based on the task demands of all tasks in the task queue of the CPU core 1 in the time window 1.

In some embodiments, the current load of CPU core 1 is a weighted statistic of the task demand values of all tasks in the task queue of the CPU core 1 over time window 1.

S4, determining the expected computing capacity 1 corresponding to the current load 1 of the CPU core 1.

In some embodiments, the desired computing power 1 may be expressed as cpu_util1×max_capability/window_size. Where cpu_util1 represents the current load 1 and max_capability represents the maximum computational power value in the multi-core CPU system. For example, the default maximum computing power value is 1024.

In some embodiments, when the electronic device 100 performs load statistics using the WALT algorithm, the electronic device 100 adds the task requirement value of each task to the curr_ runnable _sum member of the task queue of the CPU core 1, where curr_ runnable _sum holds weighted statistics of task requirement values of all tasks in the task queue within the time window 1, that is, the current load 1.

In the embodiment of the present application, when the electronic device 100 performs load statistics by using WALT algorithm, walt _time of each task in the CPU core 1 in one time window is added to prev_ runnable _sum members, and in the time window 1, the prev_ runnable _sum will save the total window load of all tasks in the task queue of the CPU core 1 in the last time window of the time window 1.

It should be noted that, the present application is not limited to WALT algorithm and PELT algorithm, and other load statistics algorithms may be used to count the current load of the CPU core 1 according to the embodiments of the present application, which is not limited herein.

S102, when the expected computing capacity 1 of the CPU core 1 is larger than a first preset value, performing task migration on the task 1 in the task queue of the CPU core 1, and determining that the target CPU core of the task 1 is the CPU core 2 by the electronic device 100 based on the expected computing capacity 2 of the task 1.

In some embodiments, the first preset value is determined based on a maximum computing power of the CPU core 1. In one implementation, the first preset value is equal to the maximum computing power of the CPU core 1. In one implementation, the first preset value is equal to k1 times the maximum computing power of the CPU core 1, k1 being greater than zero and less than 1. For example, k1 takes a value of 0.9. In the embodiment of the present application, the first preset value may also be other values associated with the maximum computing capability, which is not limited herein.

In some embodiments, the small core CPU, the medium core CPU, and the large core CPU each correspond to a preset fixed value. When the CPU core 1 is a small core (or middle core, large core) CPU, the first preset value is a preset fixed value corresponding to the small core (or middle core, large core) CPU.

In some embodiments, the first preset value is equal to the maximum computing power of the CPU core 1. When the CPU core 1 schedules the task 2, if it is determined that the expected computing power 1 of the CPU core 1 is less than or equal to the maximum computing power of the CPU core 1, the electronic device 100 adjusts the frequency of the CPU core 1 based on the expected computing power 1 and runs the task 2, and if the maximum computing power of the CPU core 1 is less than the expected computing power 1 of the CPU core 1, task migration is performed on the task 1 in the task queue of the CPU core 1, and the task 1 is inserted into the ready queue of the target CPU core. In one implementation, task 1 may be the most heavily loaded task in the task queue of CPU core 1 (e.g., the task with the greatest task demand value at the current time window), and in one implementation, task 1 may be the most heavily loaded critical task in the task queue of CPU core 1.

In some embodiments, the electronic device 100 determines the target CPU core of task 1 based on the desired computing power 2 of task 1, and may specifically include steps S5 to S7. Wherein:

S5, the electronic device 100 determines the expected computing capacity 2 of the task 1 based on the task demand value of the task 1 in the current time window.

In one implementation, the desired computing power 2 of task 1 may be represented as demand 1 x 1024/window_size, where demand 1 represents the task demand value of task 1 over the current time WINDOW.

S6, the electronic device 100 determines the control group 1 based on the expected computing capacity 2 of the task 1.

It should be noted that, in the embodiment of the present application, the maximum computing power of the control group is the maximum computing power of one or more CPUs bound by the control group.

In some embodiments, the electronic device 100 determines at least one control group having a maximum computing power greater than 125% of the desired computing power 2, control group 1 being one of the at least one control group. In one implementation, the control group 1 is a control group with the smallest computing power among the at least one control group.

S7, determining the CPU core 2 bound by the control group 1 as the target CPU core of the task 1 based on the task demand value of the task 1 in the current time window.

In some embodiments, the electronic device 100 determines at least one of the CPU cores bound to the control group 1 that satisfies a condition that a maximum computing power of the CPU cores is greater than (demand 1+pre_runnable_sum 1) 1024/WINDOW_SIZE. Wherein pre_ runnable _sum1 represents the sum of window loads of all tasks in the task queue of the CPU core in the last time window, and CPU core 2 is one of the at least one CPU core. In one implementation, the CPU core 2 is a CPU core with the smallest computing power among the at least one CPU core. In one implementation, the CPU core 2 is a CPU core with the greatest computing power of the at least one CPU core.

The method of determining the target CPU core provided in the alternative embodiment of step S102 is not limited, and the embodiment of the present application may also determine the target CPU core of task 1 in other manners, which is not specifically limited herein.

It should be noted that, when the CPU core 1 currently running in the task 1 is a small core CPU, the electronic device 100 may determine the target CPU core of the task 1 in the middle core CPU, and when the middle core CPU cannot meet the resource requirement of the task 1, the electronic device 100 determines the target CPU core of the task 1 in the large core CPU, or when the CPU core 1 currently running in the task 1 is a small core CPU, the electronic device 100 may directly determine the target CPU core of the task 1 in the large core CPU, so as to quickly meet the resource requirement of the task 1, and avoid power consumption and time loss caused by frequent context switching.

S103, migrating the task 1 to a task queue of the CPU core 2, and in the process of switching the CPU context of the task 1, the electronic device 100 records the current computing capacity 1 of the CPU core 1 and the migration type of the task 1 to the context of the task 1.

In the embodiment of the present application, in the process of switching the CPU context, the electronic device 100 obtains the current computing power 1 corresponding to the current frequency of the CPU core 1.

In one implementation, the corresponding current computing power 1 is computed based on the current frequency of the CPU core 1, and the current computing power 1 may be expressed as (cur_freq1/cpu_max_freq1) ×cpu_capacity_org1. Where cpu_max_freq1 represents the maximum frequency of CPU core 1, and cpu_capability_org1 represents the relative computing power of CPU core 1 with respect to the maximum core in the multi-core CPU.

Cpu_capability_org1 may be expressed as cpu_scale1 x cpu_max_freq1/max_freq. Where cpu_scale1 represents the maximum computing power of CPU core 1.

In one implementation, for a multi-core CPU system, the electronic device 100 stores a file including the maximum computing power of each CPU core, and the electronic device 100 may generally query the file to obtain the maximum computing power of the CPU core 1.

In one implementation, the electronic device 100 stores a table of mapping relationships between the frequencies and the computing capacities of the CPU cores, and the electronic device 100 may query the computing capacities corresponding to the current frequencies of the CPU cores 1 according to the table.

In the embodiment of the present application, when the electronic device 100 performs task scheduling on a task in the task queue of the CPU core 1, it may determine that inter-core task migration is performed on a task in the task queue of the CPU core 1 according to one or more pieces of information such as a load of a currently executed task (for example, the task 1 corresponds to a control group), an operation state, and a current load of the CPU core 1.

In some embodiments, the inter-core task migration performed by the CPU core 1 may include, but is not limited to, two cases (1) when the computing power of the CPU core 1 cannot meet the statistical expected computing power of the current load of the CPU core 1 (i.e., the expected computing power is smaller than the first preset value), migrating the task with the heavier load to the task queue of the other CPU core with the larger computing power, and (2) when the task queue of the CPU core 2 is empty, actively pulling the task in the task queue of the CPU core 1. In one implementation, the migration types corresponding to the different cases are different, and when the electronic device 100 performs task migration of the task 1 in any one of the cases, the migration type corresponding to the case is recorded in the context of the task 1. In one implementation, when the electronic device 100 performs task migration of the task 1 based on the case 1, the migration type corresponding to the case is recorded in the context of the task 1, and the other cases are not recorded. In the embodiment of the present application, the migration type corresponding to the above case 1 may be referred to as a first migration type, and the migration type corresponding to the above case 2 may be referred to as a second migration type.

In one implementation, when the electronic device 100 schedules a task in a task queue of the CPU core, the electronic device 100 records first identification information in a context of the task. The first identification information is used for representing whether the task is an inter-core migration task and a specific migration type. For example, when the first identification information of the task 1 is 0, it indicates that the task 1 is an inter-core migration task, and when the first identification information of the task 1 is greater than 0, it indicates that the task 1 is not an inter-core migration task, specifically, when the first identification information of the task 1 is 1, it may indicate that the task 1 is a first migration type, and when the first identification information of the task 1 is 2, it may indicate that the task 1 is a second migration type.

In one implementation, when the electronic device 100 schedules a task in the task queue of the CPU core, the electronic device 100 records the second identification information and the third identification information in the context of the task. The second identification information is used for recording whether the task is an inter-core migration task, for example, when the second identification information of the task 1 is 1, the task 1 is represented as an inter-core migration task, and when the second identification information of the task 1 is 0, the task 1 is represented as a non-inter-core migration task. The third identification information is used for recording the migration type of the task, for example, when the third identification information of the task 1 is 0, the task 1 is represented as the first migration type, and when the third identification information of the task 1 is 1, the task 1 is represented as the second migration type.

In some embodiments, during the CPU context switch of task 1, electronic device 100 records the current computing power 1 of CPU core 1, the migration type of task 1, and the first task information to the context of task 1, where the first task information is used to characterize whether task 1 is a critical task.

In the embodiment of the present application, various tasks corresponding to all applications of the electronic device 100 may be divided into critical tasks and non-critical tasks. For critical tasks and non-critical tasks, different ways of resource management may be performed to maximize resource utilization.

In some embodiments, the electronic device 100 determines whether the task is a critical task according to a control group corresponding to the task. In one implementation, the electronic device 100 determines tasks of applications corresponding to the top-app group shown in fig. 3 as critical tasks, and tasks corresponding to other control groups as non-critical tasks. In one implementation, the electronic device 100 determines tasks of applications corresponding to the top-app set and foreground set shown in fig. 3 as critical tasks, and tasks corresponding to other control sets as non-critical tasks.

In some embodiments, the electronic device 100 determines whether a task is a critical task based on the task type of the task. In one implementation, the specified type of task and tasks that are strongly related to the specified type of task are determined to be critical tasks, and the other types of tasks are determined to be non-critical tasks. In one implementation, among the tasks of the applications corresponding to the top-app group and the foreground group shown in fig. 3, a task of a designated type and a task strongly related to the task of the designated type are determined as critical tasks, and tasks corresponding to other types of tasks and other control groups are determined as non-critical tasks.

In the embodiment of the application, the task of the specified type can comprise a task with strong user perception, such as a drawing task related to a UI and the like. For example, when the electronic device 100 detects a user operation related to animation, such as sliding or dragging, it determines that a drawing task corresponding to the operation is a critical task, and the electronic device 100 preferentially responds to such operation, so as to reduce the click feeling of the interface display. In one implementation, the above specified types of tasks may also include a data download task, a data upload task, and so on.

In some embodiments, the electronic device 100 determines whether a task is a critical task based on the application to which the task corresponds. In one implementation, tasks corresponding to a given application (e.g., applications such as gaming applications and navigation applications) are determined to be critical tasks, and tasks of other applications are determined to be non-critical tasks. In one implementation, in the top-app set and foreground set of corresponding applications shown in fig. 3, tasks of a given application (e.g., an application such as a game application, a navigation application, etc.) are determined to be critical tasks, and tasks of other applications and tasks of other control set corresponding applications are determined to be non-critical tasks.

In some embodiments, the electronic device 100 collects average historical load data for each task and determines whether the task is a critical task based on the average historical load data for each task, where the average historical load data for each task may include a task load of M load statistics cycles. In one implementation, a task is determined to be a critical task when the variance of the historical load data of the task is greater than a preset value, and is otherwise a non-critical task. In one implementation, among the tasks of the applications corresponding to the top-app group and the foreground group shown in fig. 3, the task with the variance of the historical load data greater than or equal to the preset value is determined as a critical task, and the task with the variance of the historical load data less than the preset value and the task corresponding to the other control groups are determined as non-critical tasks.

In some embodiments, the electronic device 100 stores the first file locally, or the electronic device 100 may obtain the first file online. The first file is used for storing identification information corresponding to each task of all applications of the electronic device 100, and attribute information of whether the task is a critical task. When the inter-core migration is performed on the task 1, whether the task 1 is a critical task can be queried from the first file according to the identification information of the task 1.

In some embodiments, the electronic device 100 stores the second file locally, or the electronic device 100 may first obtain the second file. The second file is used for storing identification information corresponding to each task of all applications of the electronic device 100, and a priority of the task. When the inter-core migration is performed on the task 1, the priority of the task 1 can be queried from the second file according to the identification information of the task 1, and whether the task 1 is a key process is determined according to the priority of the task 1. For example, when the priorities of tasks in the electronic device 100 include 1 to N, tasks having priorities less than the threshold value 1 are classified as critical tasks, and tasks having priorities equal to or greater than the threshold value 1 are classified as non-critical tasks.

It should be noted that, the method is not limited to the above determination manners of the critical task and the non-critical task, and in the embodiment of the present application, whether the task 1 is the critical task may also be determined by other manners, which is not limited herein. In some embodiments, the electronic device 100 may also employ a combination of the various determination approaches in the above embodiments.

S104, when the task 1 in the task queue of the CPU core 2 is called, determining whether the task 1 is a new task of the CPU core 2. If yes, S105 is executed.

In the embodiment of the present application, when a task in the task queue of the CPU core 2 is scheduled, the running time (for example, physical running time) of the task in the CPU core 2 may be accumulated. In one implementation, if the running time of a task in the CPU core 2 is zero, it may be determined that the task is a new task that has not been run in the task queue of the CPU core 2.

When the task 1 is migrated from the CPU core 1 to the CPU core 2, the physical running time of the task 1 on the CPU core 1 is cleared.

S105, when it is determined that task 1 is an inter-core migration task based on the context of task 1 and the migration type of task 1 is the first migration type, the current computing capability of the source CPU core in the context of task 1 is obtained.

Note that, when the task 1 is migrated from the CPU core 1 to the CPU core 2, the CPU core 1 is a source CPU core of the task 1, and the CPU core 2 is a target CPU core of the task 1. It will be appreciated that the current computing power of the source CPU core in the context of task 1 is the current computing power 1 of the aforementioned CPU core 1.

In some embodiments, when the migration type of task 1 is determined to be the first migration type based on the migration type of the context record of task 1, and task 1 is determined to be a critical task based on the first task information of the context record of task 1, the current computing power of the source CPU core in the context of task 1 is obtained.

In one implementation, the electronic device 100 does not record the first task information in the context of the task 1 in step S103, and the electronic device 100 may identify whether the task is a critical task before step S105 after confirming that the task 1 is a new task.

In the embodiment of the application, after the inter-core migration of the critical task, the electronic device 100 can perform frequency adjustment on the target CPU core based on the computing capability of the source CPU core of the task, so as to rapidly meet the resource requirement of the critical task and effectively improve the user experience. For the inter-core migration of non-critical tasks, the electronic device 100 may perform frequency adjustment on the target CPU core based on the conventional algorithm to save resources.

The present computing power 1 of the CPU core 1, the migration type of the task 1, and the first task information of the task 1 are not limited to be recorded in the context of the task 1, but may be recorded in other storage modules, which is not particularly limited in the embodiment of the present application. For example, to the storage module 1, accordingly, the electronic device 100 may acquire the current computing power 1 of the CPU core 1, the migration type of the task 1, and the first task information of the task 1 from the storage module 1 in step S105.

S106, determining a first frequency of the CPU core 2 corresponding to the current computing capacity of the source CPU core.

In one implementation, the first frequency of the corresponding CPU core 2 is calculated based on the current computing capability 1 of the CPU core 1, and the first frequency may be expressed as (cur_capability 1/cpu_capability_org2) ×cpu_max_freq2. Where cur_capability 1 represents the current computing power 1 of CPU core 1, cpu_max_freq 2 represents the maximum frequency of CPU core 2, and cpu_capability_org2 represents the relative computing power of CPU core 1 with respect to the maximum core in the multi-core CPU.

Cpu_capability_org2 may be expressed as cpu_scale 2 x cpu_max_freq1/max_freq. Where cpu_scale 2 represents the maximum computing power of CPU core 2.

In one implementation, the electronic device 100 stores a table of mapping relationships between the frequencies of the CPU cores and the computing capabilities, and the electronic device 100 may query the first frequency of the CPU core 2 corresponding to the current computing capability 1 according to the table.

S107, when the current frequency of the CPU core 2 is smaller than a second preset value, the frequency of the CPU core 2 is adjusted to the first frequency, and the second preset value is determined based on the first frequency.

The second preset value is equal to the first frequency, or the second preset value is equal to k2 times of the first frequency, and k2 is larger than zero and smaller than 1. For example, k2 has a value of 0.95. In the embodiment of the present application, the second preset value may also be other values associated with the first frequency, which is not specifically limited herein.

In the embodiment of the present application, when the first frequency is less than or equal to the current frequency of the CPU core 2, the CPU core 2 continues to perform frequency modulation based on the load counted by the load counting algorithm.

For example, as shown in fig. 8, when the CPU core 1 runs the task 1, the electronic device 100 determines that the maximum computing power of the CPU core 1 cannot meet the expected computing power corresponding to the current load of the CPU core 1, and the electronic device 100 migrates the task 1 to the CPU core 2 with a lower load and records the current computing power 1 of the CPU core 1 and the first migration type of the task 1 when the task context is switched. Referring to fig. 8, when task 1 is migrated to CPU core 2, the frequency of CPU core 2 is low. When the electronic device 100 schedules the task 1, it is determined that the task 1 is a new task of inter-core migration of the first migration type, the electronic device 100 calculates a desired frequency (i.e., a first frequency) corresponding to the CPU core 2 based on the above-mentioned current computing capability 1 recorded in the context of the task 1, and the electronic device 100 frequency-increases the frequency of the CPU core 2 to the above-mentioned desired frequency because the current frequency of the CPU core 2 is smaller than the above-mentioned desired frequency. The fast frequency raising of the inter-core migration task of the first migration type is realized, the response speed of the electronic equipment 100 is effectively improved, and the jam condition of the electronic equipment 100 after the task migration is avoided.

In the embodiment of the application, the first processor core may be the aforementioned CPU core 1, the first task queue may be a task queue of the CPU core 1, the first task may be the aforementioned task 1, the first computing power of the first processor core may be the aforementioned current computing power 1, the second processor core may be the aforementioned CPU core 2, the second task queue may be a task queue of the CPU core 2, and the first type of task may also be referred to as a critical task.

In embodiments of the present application, the software system of the electronic device 100 may employ a layered architecture, an event driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. In the embodiment of the application, taking an Android system with a layered architecture as an example, a software structure of the electronic device 100 is illustrated.

Referring to fig. 9, fig. 9 shows a software architecture block diagram of an electronic device 100 provided by an exemplary embodiment of the present application. Based on the software structure block diagram shown in fig. 9, for inter-core task migration of a first migration type, recording the current computing capacity of a source CPU core when the task is subjected to context switching, determining that the task is a new task of the first migration type in a target CPU task queue when a target CPU checks that the task is scheduled, determining a desired frequency of the target CPU corresponding to the current computing capacity based on the current computing capacity of the CPU core in the context of the task, and performing frequency adjustment by the target CPU based on the desired frequency.

As shown in fig. 9, the hierarchical architecture divides the software into several layers, each with distinct roles and branches. The layers communicate with each other through a software interface. In some embodiments, the Android system may be divided into an application layer, an application framework layer, and a kernel layer (kernel) from top to bottom. Wherein:

The application layer includes a series of application packages, such as cameras, gallery, and the like. Other applications, such as WeChat, tremble, etc., that may enable a front-facing camera of electronic device 100 may also be included.

The application framework layer provides an application programming interface (application programming interface, API) and programming framework for the application of the application layer. The application framework layer includes a number of predefined functions.

The application layer and the application framework layer run in a virtual machine. The virtual machine executes java files of the application program layer and the application program framework layer as binary files. The virtual machine is used for executing the functions of object life cycle management, stack management, thread management, security and exception management, garbage collection and the like.

As shown in FIG. 9, in an embodiment of the application, the application framework layer may include an Activity management service (ACTIVITY MANAGER SERVICE, AMS) and a mission critical identification module. The AMS is a system service of an android (android) system, and is used for controlling reasonable scheduling and running among different applications in the system. The main responsibilities of the AMS include uniformly scheduling activities of applications, managing processes of applications, managing memory, scheduling services (services), scheduling tasks (tasks), querying a current running state of a system, etc., and the tasks managed by the AMS include critical tasks and non-critical tasks. The mission critical identification module is used to identify and manage whether a task performed by the electronic device 100 is a mission critical. In some embodiments, the mission critical identification module has a first file stored therein. The first file is used for storing identification information corresponding to each task corresponding to all applications of the electronic device 100, and attribute information of whether the task is a critical task. In some embodiments, the mission critical identification module may obtain a second file, where the second file is used to store identification information corresponding to each task corresponding to all applications of the electronic device 100, and a priority of the task, and the mission critical identification module may identify whether the task is a mission critical based on the priority of the task.

The kernel layer is a layer between hardware and software. The kernel layer (kernel) may perform corresponding operations in response to the functions invoked by the application framework layer.

In the embodiment of the present application, as shown in fig. 9, the kernel layer may include a load statistics module, a scheduler, a scheduling class framework, and a context switching module. The load statistics module is configured to, when the electronic device 100 executes a task at the present time, count a current load of the electronic device 100 in each load statistics period. The scheduler is used for activating a designated scheduling class to execute task scheduling, namely, the allocation of a plurality of tasks on a plurality of CPU cores and the task migration among different CPU cores. The scheduling class framework may include the following scheduling classes: stop_ sched _class, dl_ sched _class rt_ sched _class rt_ sched \u class (S). The context switching module is used for executing the context switching of the task when the inter-core task is migrated, and the context switching module can also store the context of each task. In some embodiments, when a task performs inter-core migration, the current computing power of the source CPU core and the migration type of the task are recorded in the context of the task. In some embodiments, when a task performs inter-core migration, the context switch module invokes the critical task identification module to identify whether the task is a critical task, and records first task information of the task in a context of the task, where the first task information is used to characterize whether the task is a critical task.

In the embodiment of the application, the kernel layer can also comprise a touch chip driver, a display driver, a sensor driver, a camera driver, an audio driver and the like.

It should be noted that fig. 9 is merely an exemplary illustration of a software architecture block diagram according to an embodiment of the present application, and each layer of the software architecture block diagram shown in fig. 9 may further include other modules, which is not limited herein.

The embodiment of the application also provides a computer readable storage medium. All or part of the flow of the above method embodiments may be implemented by a computer program to instruct related hardware, where the program may be stored in the above computer storage medium, and when the program is executed, the program may include the flow of each method embodiment as described above. The computer readable storage medium includes a read-only memory (ROM) or a random access memory (random access memory, RAM), a magnetic disk or an optical disk, or other various media capable of storing program codes.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.

While the application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the foregoing embodiments may be modified or equivalents may be substituted for some of the features thereof, and that the modifications or substitutions do not depart from the spirit of the embodiments.

Claims

1. A method for frequency adjustment of inter-core migration, the method comprising:

when the electronic equipment determines that the expected computing capacity corresponding to the current load of a first processor core is larger than a first preset value, migrating a first task in a first task queue of the first processor core to a second task queue of a second processor core, and recording the first computing capacity corresponding to the current frequency of the first processor core and a first migration type of the first task;

When the electronic equipment schedules the first task in the second task queue, determining a first frequency of the second processor core corresponding to the first computing capability when determining that the first task is a new task of the first migration type in the second task queue;

When the current frequency of the second processor core is smaller than a second preset value, adjusting the frequency of the second processor core to be the first frequency, wherein the second preset value is determined based on the first frequency.

2. The method of claim 1, wherein when determining that the first task is a new task of the first migration type in the second task queue, determining a first frequency of the second processor core corresponding to the first computing capability comprises:

And when the first task is determined to be a new task of the first migration type in the second task queue and the first task is determined to be a task of a first type, determining a first frequency of a second processor core corresponding to the first computing capability.

3. The method according to claim 1 or 2, wherein the migrating a first task in the first task queue of the first processor core to a second task queue of a second processor core and recording a first computing power corresponding to a current frequency of the first processor core and a first migration type of the first task includes:

Migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and determining the first computing capacity corresponding to the current frequency of the first processor core when the first task performs context switching;

Recording that the computing capacity corresponding to the current frequency of the source processor core of the first task is the first computing capacity and the migration type of the first task is the first migration type in the context of the first task.

4. The method of claim 2, wherein the migrating a first task of the first task queue of the first processor core to a second task queue of a second processor core and recording a first computing power corresponding to a current frequency of the first processor core and a first migration type of the first task comprises:

Migrating the first task in the first task queue of the first processor core to the second task queue of the second processor core, and determining whether the first computing capacity corresponding to the current frequency of the first processor core and the first task are the first type of task when the first task performs context switching;

Recording that computing capacity corresponding to the current frequency of the source processor core of the first task is the first computing capacity, migration type of the first task is the first migration type and first task information in the context of the first task, wherein the first task information is used for representing whether the first task is the first type task.

5. The method of claim 4, wherein determining the first frequency of the second processor core corresponding to the first computing power when the first task is determined to be a new task of the first migration type in the second task queue comprises:

when the first task is determined to be a new task in the second task queue, acquiring the migration type of the first task and the first task information from the context of the first task;

when determining that the migration type of the first task is the first migration type and the first task information characterizes the first task as the first type of task, acquiring the current computing capacity of a source processor core of the first task when the first task is migrated from the context of the first task, wherein the current computing capacity of the source processor core of the first task is the first computing capacity;

the electronic device determines the first frequency of the second processor core corresponding to the first computing capability.

6. The method of claim 5, wherein the electronic device records a runtime of each task in the second task queue at the second processor core, wherein the determining that the first task is a new task in the second task queue comprises:

and when the running time of the first task recorded by the electronic equipment at the second processor core is zero, determining that the first task is a new task in the second task queue.

7. The method of claim 1, wherein the first preset value is equal to a maximum computing power of the first processor core or the first preset value is equal to k1 times the maximum computing power of the first processor core, the k1 being greater than zero and less than 1.

8. The method of claim 1, wherein the second preset value is equal to the first frequency, or wherein the second preset value is equal to k2 times the first frequency, the k2 being greater than zero and less than 1.

9. The method of claim 2, wherein the first type of task comprises a specified type of task and a task that is strongly related to the specified type of task;

Or the first type of task comprises the task of the appointed type of the application corresponding to the top application group and the foreground group and the task strongly related to the task of the appointed type;

The specified type of task includes at least one of a drawing task, a data download task, and a data upload task.

10. The method of claim 2, wherein the first type of task comprises an application-specific task;

Or the first type of task comprises a task of the appointed application corresponding to a top application group and a foreground group;

The designated application includes at least one of a gaming application, a navigation application, and a video application.

11. An electronic device comprising a memory, one or more processors, a plurality of application programs, and one or more programs, wherein the one or more programs are stored in the memory, wherein the one or more processors, when executing the one or more programs, cause the electronic device to implement the method of any of claims 1-10.

12. A computer storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any one of claims 1 to 10.

13. A computer program product, characterized in that the computer program product, when run on a computer, causes the computer to perform the method according to any of claims 1 to 10.