CN114967375A - Method for forming semiconductor pattern structure and method for processing semiconductor device - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor pattern structure and a processing method of a semiconductor device, and the method for forming a semiconductor pattern structure includes the following steps. An alignment operation is performed to align the reticle having the first preset pattern with the bottom alignment layer, and to obtain alignment parameters. The alignment parameter is corrected using the read offset parameter to shift the alignment position of the reticle. The photolithography apparatus is controlled to perform photolithography processing on the photoresist layer to pattern the photoresist layer based on the mask. Finally, the photoresist layer with the first preset pattern is used as a mask, and then the etching equipment is controlled to etch the dielectric layer, so as to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. The present disclosure can correct the position shift problem of the semiconductor pattern structure that occurs in the post-etching process by means of lithography mask overlay compensation in the photolithography process, and can significantly improve the yield of semiconductor devices.

Description

Method for forming semiconductor pattern structure and processing method of semiconductor device

technical field

The present disclosure relates to the technical field of semiconductor device processing, and more particularly, the present disclosure can provide a method for forming a semiconductor pattern structure and a method for processing a semiconductor device.

Background technique

Photolithography and etching processes are the basic and core processes used to manufacture semiconductor devices. The photolithography process utilizes the geometry on the mask, and can transfer the corresponding pattern to the photosensitive film layer (Photoresist, photoresist) covering the semiconductor wafer through photochemical reaction. However, the pattern on the photosensitive film layer is not the final part of the semiconductor device, but only a stamp of the final circuit pattern. The etching process is used for pattern transfer to form a semiconductor pattern structure on the device layer. According to a general theory, as long as a corresponding pattern is formed at a set position on the photoresist layer, a desired semiconductor pattern structure can be obtained at a desired position on the device layer.

However, in the process of actual semiconductor device processing, it is found that even if the pattern on the photoresist layer is aligned with the pattern on the alignment layer (the overetching error is theoretically zero), the semiconductor pattern formed by etching on the device layer is still There will be problems with deviation from the desired position.

SUMMARY OF THE INVENTION

In order to solve the problem that the semiconductor pattern formed by etching on the device layer may deviate from the desired position, the present disclosure can provide a method for forming a semiconductor pattern structure and a processing method of a semiconductor device, so as to correct the semiconductor pattern structure formed by etching on the device layer. location, etc. for at least one technical purpose.

In order to achieve the above technical purpose, the present disclosure provides a method for forming a semiconductor pattern structure; the method may include, but is not limited to, at least one of the following steps.

First, the lithography apparatus is controlled to perform an alignment operation, so as to align the reticle with the first preset pattern with the bottom alignment layer, and obtain alignment parameters. Then, the offset parameters generated in advance can be read, and the alignment parameters can be corrected by the offset parameters, and then the lithography apparatus can be controlled to perform a moving operation, so that the alignment position of the reticle is offset. Secondly, on the basis of the offset mask, the photolithography equipment is controlled to perform photolithography processing on the photoresist layer, so as to pattern the photoresist layer based on the mask. Finally, using the photoresist layer with the first preset pattern as a mask, and controlling the etching equipment to etch the dielectric layer, to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. Wherein, the photoresist layer can be disposed on the dielectric layer; the process of generating the offset parameters in advance is as follows. The photolithography alignment conditions are set, and after alignment, the photolithography equipment is controlled to perform photolithography processing, so as to form a second preset pattern on the first pretreatment film layer. Using the first pretreatment film layer with the second preset pattern as a mask, the etching equipment is controlled to etch the second pretreatment film layer, so as to etch the second preset pattern on the second pretreatment film layer structure. Then, the position of the second preset pattern structure on the second pretreatment film layer is compared with the preset position, and an offset parameter is generated according to the comparison result.

In order to achieve the above technical purpose, the present disclosure also provides a method for processing a semiconductor device, which may include, but is not limited to, the method for forming a semiconductor pattern structure in any embodiment of the present disclosure.

The beneficial effects of the present disclosure are:

The present disclosure can correct the position shift problem of the semiconductor pattern structure that occurs in the post-etching process by means of lithography mask overlay compensation in the photolithography process. For example, for the problem of shifting the semiconductor pattern formed near the edge of the wafer, the present disclosure can play a better effect and greatly improve the electrical performance of the device. Especially for peripheral circuits, the present disclosure can significantly improve the yield of semiconductor devices.

The present disclosure can form a semiconductor pattern structure at a desired position on the semiconductor device layer, and has the outstanding advantages of controllable position of the semiconductor pattern structure and high processing reliability of the semiconductor device.

The technical solution provided by the present disclosure significantly improves the etching process quality for semiconductor device processing, helps reduce the generation of defects, and greatly improves the yield of semiconductor device products.

Description of drawings

FIG. 1 shows a schematic diagram of setting a plurality of alignment marks on a scribe lane in one or more embodiments of the present disclosure.

2 is a schematic diagram illustrating alignment of post-lithography alignment pattern marks with alignment marks on a bottom alignment layer in one or more embodiments of the present disclosure.

FIG. 3 is a schematic diagram illustrating a misalignment state of non-vertical etching paths caused by different etching rates at different positions on the etched film layer in one or more embodiments of the present disclosure.

FIG. 4 is a schematic diagram illustrating a state of misalignment between the position of the pattern structure and the preset position due to different etching rates in one or more embodiments of the present disclosure.

FIG. 5 shows a schematic diagram of shifting the alignment position of the reticle according to the offset parameter after photolithography in one or more embodiments of the present disclosure.

FIG. 6 is a schematic diagram illustrating an alignment state of an etching path formed after etching is performed based on the mask formed by the offset mask in FIG. 5 in one or more embodiments of the present disclosure.

7 is a schematic diagram illustrating the formation of a semiconductor pattern structure aligned with the bottom alignment layer on the etched film layer based on the mask formed by the offset mask in FIG. 5 in one or more embodiments of the present disclosure .

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

The present disclosure can provide a method for forming a semiconductor pattern structure to form a semiconductor pattern structure aligned with a bottom alignment layer on a target film layer (etched film layer). A reference pattern is provided on the bottom alignment layer.

As shown in Figures 1 and 2, the lithography alignment conditions are set. After the alignment, the photolithography equipment is controlled to perform photolithography processing, so as to form a second preset pattern on the first pretreatment film layer. Specifically, setting the lithography alignment conditions in the present disclosure includes: performing alignment using one or more alignment marks (Align Marks) on the scribe lane (Scribe Lane) of the wafer shown in FIG. 1 , wherein the scribe lane is A spacer structure between adjacent different chips on a wafer. It can be understood that, when the present disclosure is implemented, a semiconductor substrate can be provided, and then a second pretreatment film layer and a first pretreatment film layer can be formed over the semiconductor substrate, and the first pretreatment film layer can be formed on the second pretreatment film. on the treatment film.

As shown in FIG. 3 , using the first pretreatment film layer with the second preset pattern as a mask, the etching equipment is controlled to etch the second pretreatment film layer, so as to etch on the second pretreatment film layer A second preset pattern structure is obtained. It can be understood from the diagram that when etching certain positions on the wafer (eg, a position near the edge of the wafer), the etching path is sometimes in a non-vertical state. The non-vertical path directly leads to a misalignment problem between the semiconductor pattern structure and the bottom alignment layer, which makes the etching process uncontrollable and reduces the yield of semiconductor device products.

As shown in FIG. 4 , under the premise of complete alignment in the photolithography process, the second preset pattern structure obtained by etching still shifts in a certain direction (shown as a left-downward direction). This is caused by the different etching rates of different positions on the wafer and the defects on the wafer surface (such as the slope generated by the Edge Ring), such as the wafer center (Wafer Center) and the wafer edge (Wafer Edge). The difference in the etching rate is relatively large, which causes the etched semiconductor pattern structure to be easily shifted in a certain direction. The present disclosure innovatively compensates the position of the semiconductor pattern structure based on the analysis result of the displacement cause, and performs preprocessing (ie, the above-mentioned processing process) before the actual processing of the semiconductor device. The degree of offset parameter (Overlay Parameter). Although the pre-lithography process in the pretreatment process is a photolithography process and the pre-etch process in the pre-treatment process is an etching process, the pre-lithography process and the pre-etch process involved in the present disclosure are not used for processing Instead of the semiconductor device, offset parameters used to compensate for the reticle position are obtained.

As shown in FIGS. 3 and 4 , the embodiment of the present disclosure specifically compares the position of the second preset pattern structure on the second pretreatment film layer with the preset position, and generates an offset parameter according to the comparison result. More specifically, in the present disclosure, comparing the position of the second preset pattern structure on the second pretreatment film layer with the preset position and generating the offset parameter according to the comparison result includes: reading the first position data of the preset position, and acquiring the second position data of the second preset pattern structure on the second pretreatment film layer by means of pattern check. The specific process of pattern inspection can be reasonably selected and used according to the actual situation, which will not be repeated in this disclosure. Difference calculation is performed on the corresponding first position data and the second position data to generate an offset parameter according to the difference calculation result. The offset parameters of the present disclosure may specifically include, but are not limited to, an x-direction offset (Offset X), a y-direction offset (Offset Y), an x-direction scaling amount (Scale X), and a y-direction scaling amount (Scale Y) , Orthogonality, and reticle rotation (RROT X/Y).

Next, the embodiment of the present disclosure performs the actual processing of the semiconductor device. The lithography apparatus is controlled to perform an alignment operation to align the reticle having the first preset pattern with the bottom alignment layer, and in the case of alignment, the alignment parameters are acquired. The offset parameter that has been generated in advance, that is, the offset parameter obtained by the deviation shown in FIGS. 3 and 4 is read. The acquired alignment parameters are corrected using the offset parameters. The alignment parameter is the overlay data when the reticle and the bottom alignment layer scribe track alignment mark are aligned; the present disclosure uses the offset parameter to correct the overlay data under the alignment condition.

It is understood that the present disclosure may provide a semiconductor substrate, and then a dielectric layer and a photoresist layer are sequentially formed over the semiconductor substrate. It should be understood that the first pretreatment film layer involved in the present disclosure is the same as or different from the photoresist layer. And the second pretreatment film layer is the same as or different from the dielectric layer, and the second preset pattern is the same as or different from the first preset pattern. The photoresist layer is formed on the dielectric layer, and the dielectric layer can be, for example, a silicon nitride layer or a silicon oxide layer.

As shown in FIG. 5 , the lithography apparatus is controlled to move based on the corrected alignment parameters, so that the alignment position of the reticle is shifted. It should be understood that “moving the lithography equipment” refers to moving the wafer or the reticle by the lithography equipment, that is, there are two implementations of “shifting the alignment position of the reticle” in the present disclosure: (1 ) The more commonly used method is that after the lithography equipment moves the wafer, the alignment position shifts; or (2) after the lithography equipment moves the mask, the alignment position shifts. It can be seen that the present disclosure moves the mask alignment position after aligning the mask with the bottom alignment layer, and the mask is not directly aligned with the bottom alignment layer after the movement. The photolithographic apparatus is controlled to photolithographically process the photoresist layer based on the reticle that has been deviated from the alignment position to pattern the photoresist layer based on the reticle at that position.

As shown in FIG. 6 , in the embodiment of the present disclosure, the photoresist layer having the first preset pattern is used as a mask, and the etching equipment is controlled to etch the dielectric layer, so as to form a bottom alignment layer on the dielectric layer. Aligned semiconductor pattern structures. It can be seen from FIG. 6 and FIG. 7 that even if the etching rates of different positions on the wafer are different, the present disclosure can still form a semiconductor pattern structure that is aligned with the bottom alignment layer. It can be seen that the present disclosure can align the non-vertical pattern with the bottom alignment layer, thereby effectively solving the problem of Real Pattern Overlay existing in the real pattern structure.

It can be understood that the present disclosure can also provide a method for processing a semiconductor device, the processing method including the method for forming a semiconductor pattern structure in any embodiment of the present disclosure. The semiconductor devices involved in the present disclosure may include, but are not limited to, semiconductor memory devices or logic devices, and the like. The semiconductor memory device can be, for example, a dynamic random access memory (DRAM, Dynamic Random Access Memory). The dynamic random access memory can include a plurality of memory cells arranged in a matrix structure, each memory cell having a transistor and a memory cell controlled by the transistor. composed of semiconductor capacitors. The semiconductor devices provided based on the technical solutions of the present disclosure can be applied to electronic devices, which may include but are not limited to smart phones, computers, tablet computers, wearable devices, artificial intelligence devices, and mobile power supplies. In addition, each film layer involved in the present disclosure can be formed directly or indirectly on a semiconductor substrate. Wherein the semiconductor substrate may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate or by performing Epitaxial thin film substrates obtained by selective epitaxial growth (SEG), etc.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (10)

1. A method for forming a semiconductor pattern structure, comprising: controlling the lithography equipment to perform an alignment operation to align the mask with the first preset pattern with the bottom alignment layer, and obtain alignment parameters; Read the offset parameters generated in advance; After correcting the alignment parameter by using the offset parameter, the lithography apparatus is controlled to perform a moving operation, so that the alignment position of the reticle is shifted; controlling the photolithography apparatus to perform photolithography processing on the photoresist layer to pattern the photoresist layer based on the mask; Using the photoresist layer with the first preset pattern as a mask, the etching equipment is controlled to etch the dielectric layer, so as to form a semiconductor pattern structure aligned with the bottom alignment layer on the dielectric layer. 2. The method for forming a semiconductor pattern structure according to claim 1, wherein the offset parameter is generated by: setting photolithography alignment conditions, and controlling the photolithography equipment to perform photolithography processing after alignment, so as to form a second preset pattern on the first pretreatment film layer; Using the first pretreatment film layer with the second preset pattern as a mask, the etching equipment is controlled to etch the second pretreatment film layer, so as to etch the second pretreatment film layer on the second pretreatment film layer. the second preset pattern structure; The position of the second preset pattern structure on the second pretreatment film layer is compared with the preset position, and the offset parameter is generated according to the comparison result. 3 . The method for forming a semiconductor pattern structure according to claim 2 , wherein the comparing the position of the second preset pattern structure on the second pretreatment film layer with the preset position and according to 3 . The offset parameter generated by the comparison result includes: Read the first position data of the preset position; Obtain the second position data of the second preset pattern structure on the second pretreatment film layer by means of pattern inspection; Difference calculation is performed on the corresponding first position data and the second position data to generate the offset parameter according to the difference calculation result. 4. The method for forming a semiconductor pattern structure according to claim 2 or 3, wherein the setting photolithography alignment conditions comprises: Alignment is performed using one or more alignment marks on the scribe lanes. 5. The method for forming a semiconductor pattern structure according to claim 2, wherein, The first pretreatment film layer is the same as or different from the photoresist layer. 6. The method for forming a semiconductor pattern structure according to claim 2, wherein, The second pretreatment film layer is the same as or different from the dielectric layer. 7. The method for forming a semiconductor pattern structure according to claim 2, wherein, The second preset pattern is the same as or different from the first preset pattern. 8 . The method for forming a semiconductor pattern structure according to claim 1 , wherein the offset parameters comprise an x-direction offset, a y-direction offset, an x-direction scaling amount, a y-direction scaling amount, Orthogonal values and reticle rotation values. 9 . The method of claim 1 , wherein the photoresist layer is formed on the dielectric layer. 10 . 10 . A method for processing a semiconductor device, comprising the method for forming a semiconductor pattern structure according to any one of claims 1 to 9 . 11 .

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