CN114966362A - A method for evaluating the bump reliability of plastic packaged flip-chip chips - Google Patents

Abstract

The invention discloses a method for evaluating the reliability of bumps of plastic-encapsulated flip-chip soldering chips, comprising: first, conducting electrical performance testing on the packaged flip-chip soldering chips, and extracting samples for ultrasonic scanning inspection after the test is completed; second, retaining certain samples As a control, the remaining samples were pretreated; 3. After the pretreatment, the samples were subjected to ultrasonic scanning inspection; 4. The samples were tested for electrical properties; Cycle, group B was subjected to UHAST, and group C was subjected to HAST test; 6. After the test was completed, the electrical properties of the samples were tested; 7. Part of the samples after temperature cycling were used to observe the specified bumps with 3DXRAY; 8. Abnormal bumps were found on 3DXRAY Slice and observe the section; 9. Combine the top view, side view and section observation of 3DXRAY to determine whether the bump is a cavity or a crack. If it is a cavity, it is qualified within the scope of the criterion. If it is a crack and has an extension trend, the bump cannot be guaranteed. Reliability for long-term applications.

Description

A method for evaluating the reliability of bumps of plastic packaged flip-chip chips

technical field

The invention relates to the field of flip-chip welding technology, in particular to a method for evaluating the reliability of bumps of plastic-encapsulated flip-chip welding chips.

Background technique

The flip-chip welding process is a direct interconnection process with the front side of the chip facing down. The bumps are aligned with the metal pads on the substrate 6, and stable and reliable mechanical and electrical connections are formed between the chip and the substrate by heating or pressing, and then the entire package is completed by filling underfill 2 and molding compound 5. The two-dimensional interconnect density can be maximized by the flip-chip bonding process. At the same time, because the metal pads can be placed on the entire surface of the chip, on the same area of the chip, compared with the conventional wire bonding process, the metal pads Density and quantity can be greatly improved, and because the signal transmission path is greatly shortened, flip-chip bonding has excellent electrical performance and reliability.

At present, there are two common flip-chip soldering processes, one is a metal-under-ball (UBM) structure, as shown in Figure 1-1, and the other is a 2P1M package without UBM, that is, the first dielectric layer (PI )4+metal redistribution layer (Metal)+second medium (PI/PBO)3, the structure is shown in Figure 1-2. Regardless of the form, there is a dielectric layer of polyimide (PI) or polybenzoxazole (PBO) 3 under the bump, underfill and molding fill 2 around the bump, and the substrate when connected to the substrate Green Oil (SR) Layer 1. Different organic materials have different thermal expansion coefficients, elastic modulus, and glass transition temperature (Tg). In some application environments with frequent or severe temperature changes, these organic materials will cause pulling or extrusion stress on the bumps. Once the packaging material When the filling or bump layout is unbalanced, the long-term effect of this force on the bump cannot be ignored, which will cause micro-cracks in the bump, and the crack expansion will cause abnormal electrical connection resistance between the chip and the substrate, affecting the chip. reliability, and even lead to device failure.

The traditional reliability assessment method of plastic chip package includes the following steps. The first step: pretreatment, and scanning acoustic inspection and electrical performance test before and after the pretreatment; second step: temperature cycle test, HAST test, uHAST test; third step: after the test is completed, conduct electrical test. The reliability evaluation results are only judged based on the final electrical test results.

Based on the consideration of reliability, the plastic-encapsulated flip-chip has bumps as the electrical connection between the chip and the substrate. If microcracks occur in the bumps, it may not be clearly reflected in the electrical parameter test, but it will bring hidden dangers to the reliability of long-term use. Crack propagation can significantly affect device electrical properties. That is, in the traditional assessment method for the packaging reliability of plastic packaged devices, there is a lack of reliability evaluation content for flip-chip solder bumps, and there is a problem that packaging risks cannot be identified at an early stage.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for evaluating the reliability of bumps of plastic-encapsulated flip-chip soldering chips, which can predict and release the risk of cracking of the flip-chip soldering bump structure in advance before the device leaves the factory.

In order to achieve the above-mentioned purpose, the present invention provides a method for evaluating the bump reliability of a plastic package flip-chip chip, comprising:

Step 1. Test the electrical performance of the packaged flip-chip chip, and after the test is completed, extract samples for identification for ultrasonic scanning inspection;

Step 2: Retain a certain sample as a control, and pretreat the rest of the samples;

Step 3. After the pretreatment is completed, carry out ultrasonic scanning inspection on the sample;

The fourth step is to test the electrical properties of the sample;

Step 5. Divide the samples into three groups: A, B, and C. Group A is subjected to temperature cycling, group B is subjected to UHAST, and group C is subjected to HAST test;

Step 6. After the test is completed, conduct an electrical performance test on the sample;

Step 7. Use 3DXRAY to observe the designated bumps of the samples after some temperature cycles;

Step 8. Observe the cross section of the abnormal bump slice found by 3DXRAY;

Step 9. Combine the top view, side view and cross-sectional observation of 3DXRAY to determine whether the bump is a cavity or a crack. If it is a cavity, it is qualified within the scope of the criterion. If it is a crack and has a tendency to extend, the bump cannot guarantee long-term application. reliability.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, wherein, in the second step, the pretreatment is specifically: a, appearance inspection; b, temperature cycle: -40°C to 60°C, 5 cycles; c , Baking: Bake at 125°C for 24h; d. Moisture absorption, under the condition of 30°C/60%RH, 192h; e. Reflow soldering: 3 times.

Reflow soldering conditions are shown in Table 1.

Table 1 Reflow Soldering Conditions

reflow stage condition warm up 150℃～200℃, 60～180s average heating rate ≤3℃/s Keep 217℃, 60～150s Package body maximum temperature 260℃ The time within the actual maximum temperature -5℃ 30s Cooling rate ≤6℃/s Time from 25°C to maximum temperature ≤8min

The above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, wherein, in the step 5, the temperature cycle test conditions include: the total conversion time from hot to cold or from cold to hot shall not exceed 1min, and the device is within 15min. reach the specified temperature.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, the temperature cycle test conditions are: the test temperature is -55°C to 125°C, and the cycle is performed 700-1000 times.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, the temperature cycle test conditions are as follows: the test temperature is -65°C to 150°C, and the cycle is performed 500 times.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, wherein, in the fifth step, the UHAST test conditions include: placing the chip in a temperature and humidity box, setting the temperature and humidity to 130°C/85% RH, and maintaining it for 96 hours , the chip does not apply any bias voltage at this time.

The above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, wherein, in the fifth step, the HAST test conditions include: placing the chip in a temperature and humidity box, setting the temperature and humidity to 130°C/85% RH, and keeping it for 96 hours , at this time, apply a 1.1Vdd bias to the chip power pin, the chip enable pin is placed at a low potential, the chip is in a non-working state, the ground pin is grounded, and the other adjacent IO pins are alternately placed at high potential and ground. If the IO pin is adjacent to the power pin, the IO pin is grounded. If the IO pin is adjacent to the ground pin, the IO pin is placed at a high potential. If the IO pin is connected to the power pin and the ground pin at the same time If the pins are adjacent to each other, grounding is performed to ensure that the chip has as many adjacent pins as possible with a voltage difference.

In the above-mentioned method for evaluating the reliability of bumps of a plastic-encapsulated flip-chip chip, wherein, in the seventh step, the selection of bumps includes: prioritizing stress release concentrated locations, such as bumps on four sides and four corners; prioritizing the flow of current in the analog circuit area. Large bumps, such as power bumps.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip chips, the 3DXRAY first observes the middle section of the bump, and if there are continuous holes, a top view needs to be taken, and the top view and the multi-section X-ray photos of the bump are judged. Whether the anomalous void region is continuous.

In the above-mentioned method for evaluating the reliability of bumps of plastic-encapsulated flip-chip soldering chips, wherein, in the step 8, the slice observation section is specifically as follows: grinding requires a distance from the target section, and when the target section is close to the target section, ion beam section grinding is used until the exposed section is exposed. target section.

Compared with the prior art, the technical beneficial effects of the present invention are:

The existing reliability assessment method does not aim at the reliability of the plastic package flip-chip bump structure itself, but only judges the reliability of the entire device through the electrical performance test, and there is a risk of insufficient reliability assessment. The invention proposes a condition selection for adding a temperature cycle test in the reliability process assessment of a plastic packaged device, observing a designated bump through 3DXRAY after adding the temperature cycle test, and a method for confirming the cracking of the bump.

By applying the sensitive stress of the bump to the plastic-encapsulated flip-chip soldering device, in addition to passing the electrical performance test, the invention increases the inspection of the vulnerable part of the bump, and can fully evaluate the reliability of the bump.

Description of drawings

A method for evaluating the reliability of bumps of a plastic packaged flip-chip chip of the present invention is given by the following embodiments and accompanying drawings.

Figure 1 is a schematic diagram of two structures of a common flip-chip welding process;

FIG. 2 is a schematic structural diagram of a plastic-encapsulated flip-chip device;

Figure 3 is a flowchart of a method for evaluating the reliability of bumps of plastic packaged flip-chip devices;

Figure 4 is a schematic diagram of the observation position of the bump.

Among them, Figure 1: 1-substrate green oil (SR) layer, 2-underfill and molding filling, 3-second medium (PI/PBO), 4-first medium layer (PI);

Figure 2: 2-underfill, 5-plastic compound, 6-substrate, 7-chip, 8-metal bump;

Figure 4: 9, 10, 11, 12, 13 are the cross-sections of the observed bumps.

Detailed ways

A method for evaluating the bump reliability of a plastic package flip-chip chip of the present invention will be described in further detail below with reference to the accompanying drawings.

Step (1), conduct the electrical performance test of the packaged flip-chip chip according to the product manual or detailed specification, and after the test is completed, 147 samples for identification are extracted for ultrasonic scanning inspection;

In step (2), 3 samples were retained as controls, and the remaining 144 samples were pretreated, and the pretreatment conditions were set with reference to JESD22-A113;

Step (3), carry out ultrasonic scanning inspection to the sample after the pretreatment is completed;

Step (4), conduct electrical performance test according to the product manual or detailed specification;

Step (5), divide 144 samples into three groups of A, B, and C, each group of 45+3, A group carries out temperature cycle, B group carries out UHAST, C group carries out HAST test, test conditions are as follows:

(5.1) Temperature cycle: The total conversion time from hot to cold or from cold to hot should not exceed 1min, and the device should reach the specified temperature within 15min. The test temperature is -55℃～125℃, cycle 700 times, and tighten 1000 times (optional); also can choose -65℃～150℃, cycle 500 times.

(5.2) UHAST: 130°C/85%RH, 96h.

(5.3) The power supply applies a 1.1Vdd bias voltage, the enable pin is pulled down, and the other adjacent IO pins are alternately pulled up and down, 130°C/85%RH, 96h.

Step (6), after the test is completed, conduct the electrical performance test according to the product manual or detailed specification;

Step (7), take 3 samples after temperature cycle and observe the designated bumps with 3DXRAY (Fig. 4). The selection of bumps is based on the following principles: 1. Prioritize stress release concentration locations, such as bumps on four sides and four corners 9, 10 ; 2. Prioritize the simulation of bumps with larger currents in the circuit area, such as power bumps; 3. Bumps 11 in the middle. When observing 3DXRAY, first observe the middle section 9 of the bumps. If there are continuous holes, you need to supplement the top view, combined with the top view And the X-ray photos of the bumps and multi-sections are used to determine whether the abnormal void area is continuous.

Step (8), observe the cross-section of the abnormal bumps found in 3DXRAY, pay attention to the need for a distance 13 from the target cross-section (such as 12) for grinding, and use ion beam profile grinding (CP) when approaching the target cross-section until the target cross-section 12 is exposed;

Step (9), combined with the top view, side view and cross-sectional observation of 3DXRAY, determine whether the bump is a cavity or a crack. If it is a cavity, it is qualified within the scope of the criterion. If it is a crack and has an extension trend, the bump cannot guarantee long-term. Application reliability.

The method of the invention can effectively stimulate the bump cracking caused by the mismatch of thermal expansion coefficients and the different moduli of the packaging materials, and the bump cracking will affect the service life of the product.

Claims (10)

1. A method for evaluating the reliability of bumps of a plastic package flip chip is characterized by comprising the following steps:

step one, carrying out electrical performance test on the packaged flip chip, and after the test is finished, extracting a sample for identification to carry out ultrasonic scanning inspection;

step two, reserving a certain sample as a reference, and pretreating the rest samples;

step three, after the pretreatment is finished, carrying out ultrasonic scanning inspection on the sample;

step four, carrying out electrical property test on the sample;

dividing the samples into A, B, C three groups, performing temperature circulation on group A, and performing UHAST and HAST tests on group C and group B;

sixthly, after the test is finished, carrying out an electrical property test on the sample;

seventhly, observing the specified salient points of the samples after partial temperature circulation by using 3 DXRAY;

step eight, observing the section of the bump slice with abnormal 3 DXRAY;

and step nine, observing by combining a top view, a side view and a section of the 3DXRAY, judging whether the bump is a cavity or a crack, if the bump is the cavity, the bump is qualified within a criterion range, and if the bump is the crack and has an extension trend, the bump cannot ensure the reliability of long-term application.

2. The method for evaluating the reliability of the bumps of the plastic package flip chip as recited in claim 1, wherein in the second step, the pretreatment specifically comprises: a. performing appearance inspection; b. temperature cycle: 5 cycles at-40 ℃ to 60 ℃; c. baking: baking at 125 deg.C for 24 hr; d. moisture absorption is carried out for 192 hours under the condition of 30 ℃/60 percent RH; e. reflow soldering: 3 times.

3. The method for evaluating the reliability of the bumps of the plastic package flip chip as recited in claim 1, wherein in the fifth step, the temperature cycle test conditions comprise: the total switching time from hot to cold or cold to hot must not exceed 1min and the device reaches the specified temperature within 15 min.

4. The method for evaluating the reliability of the bumps of the plastic package flip chip as recited in claim 3, wherein the temperature cycle test conditions are as follows: the test temperature is-55-125 ℃, and the cycle is 700 and 1000 times.

5. The method for evaluating the reliability of the bumps of the plastic package flip chip as recited in claim 3, wherein the temperature cycle test conditions are as follows: the test temperature is-65-150 ℃, and the circulation is carried out for 500 times.

6. The method for evaluating the bump reliability of the plastic package flip chip as recited in claim 1, wherein in the fifth step, the UHAST test conditions include: the chip is placed in a temperature and humidity box, the temperature and the humidity are set to be 130 ℃/85% RH, the temperature and the humidity are kept for 96h, and no bias voltage is applied to the chip at the moment.

7. The method for evaluating the reliability of the bumps of the plastic flip chip as recited in claim 1, wherein in the fifth step, the HAST test conditions include: the chip is placed in a temperature and humidity box, the temperature and humidity are set to be 130 ℃/85% RH, 96h is kept, 1.1Vdd bias voltage is applied to a chip power supply pin at the moment, the chip enable pin is placed at a low potential, the chip is in an out-of-operation state, the ground of the ground pin is connected with the ground pin, other adjacent IO pins are placed at a high potential and are grounded in a staggered mode, if the IO pin is adjacent to the power supply pin, the IO pin is grounded, if the IO pin is adjacent to the ground pin, the IO pin is placed at a high potential, if the IO pin is adjacent to the power supply pin and the ground pin at the same time, grounding treatment is carried out, and the situation that the chip has voltage difference between as many adjacent pins as possible is ensured.

8. The method for evaluating the bump reliability of the plastic package flip chip as recited in claim 1, wherein in the seventh step, the selecting of the bumps comprises: preferential stress release concentration locations, such as four-sided and four-cornered bumps; the area of the analog circuit is preferentially flowed with bumps with larger current, such as power supply bumps.

9. The method of claim 8, wherein 3DXRAY observation is performed by observing a middle cross section of the bump, and if there are continuous holes, a top view is taken, and the top view and an X-ray photograph of multiple cross sections of the bump are combined to determine whether the abnormal hole area is continuous.

10. The method for evaluating the reliability of the bumps of the plastic package flip chip as recited in claim 1, wherein in the step eight, the section for observing the slice specifically comprises: milling requires a distance from the target cross-section and milling with the ion beam profile as the target cross-section is approached until the target cross-section is exposed.

Images