CN114944839B - Interface circuit, interface module and application system - Google Patents

Abstract

The present invention provides an interface circuit, comprising: a first Josephson junction, a first end of which is connected to a first end of a first inductor and a first end of a second inductor and connected to a first bias current, and a second end of which is grounded; a second end of the first inductor is connected to a superconducting clock signal; a second end of the second inductor is connected to a first end of a second Josephson junction; a second end of the second Josephson junction is connected to a first end of a third Josephson junction, a first end of a third inductor and a first end of a fourth inductor; a second end of the third Josephson junction is grounded; a second end of the third inductor is connected to a CMOS data signal; a second end of the fourth inductor is connected to a first end of a fifth inductor and connected to a second bias current; and a second end of the fifth inductor generates a superconducting output signal. The interface circuit of the present invention breaks through the traditional design and provides a new non-return-to-zero CMOS-RSFQ interface circuit.

Description

Interface circuit, interface module and application system

Technical Field

The present invention relates to the field of superconducting circuit design, and in particular to an interface circuit, an interface module and an application system.

Background Art

With the rapid development of social economy and military technology, the amount of data that needs to be processed has expanded dramatically, and higher and higher requirements have been placed on the computing power of computers. Superconducting RSFQ (rapid single flux quantum) devices are mainly realized through Josephson junctions. Since the switching frequency of the Josephson junction is only in the order of picoseconds (ps), it can operate at extremely high frequencies. Superconducting RSFQ circuits are considered to be one of the alternative technologies for the next generation of digital circuits due to their low power consumption and ultra-high speed. This technology has huge advantages in power consumption and heat dissipation, making RSFQ circuits promising to realize large-scale, high-performance and low-power computer systems in the future.

However, the current integration level of superconducting RSFQ technology is still low, and it is difficult to realize the research and development of large-scale computer systems in the short term by relying solely on RSFQ devices. Therefore, the RSFQ circuit and the mainstream complementary oxide semiconductor circuit, that is, the CMOS circuit, are integrated together, and the superiority of the RSFQ circuit in high-frequency signal processing is used to implement the components with the highest frequency requirements in the system, and the CMOS circuit is used to implement the components with the second lowest frequency requirements in the system; based on this idea, the design of the interface circuit between the CMOS circuit and the RSFQ circuit has become a hot topic in current research.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an interface circuit, an interface module and an application system, which break through the traditional design and provide a new non-return-to-zero CMOS-RSFQ interface circuit.

To achieve the above-mentioned purpose and other related purposes, the present invention provides an interface circuit, which includes: a first Josephson junction, a second Josephson junction, a third Josephson junction, a first inductor, a second inductor, a third inductor, a fourth inductor and a fifth inductor; wherein the first end of the first Josephson junction is connected to the first end of the first inductor and the first end of the second inductor and is connected to a first bias current, and the second end is grounded; the second end of the first inductor is connected to a superconducting clock signal; the second end of the second inductor is connected to the first end of the second Josephson junction; the second end of the second Josephson junction is connected to the first end of the third Josephson junction, the first end of the third inductor and the first end of the fourth inductor; the second end of the third Josephson junction is grounded; the second end of the third inductor is connected to a CMOS data signal; the second end of the fourth inductor is connected to the first end of the fifth inductor and is connected to a second bias current; and the second end of the fifth inductor generates a superconducting output signal.

Optionally, the interface circuit also includes: a fourth Josephson junction, a fifth Josephson junction, a sixth inductor and a seventh inductor; wherein, the first end of the fourth Josephson junction is connected to the connection node between the second end of the fourth inductor and the first end of the fifth inductor, and the second end is grounded; the first end of the sixth inductor is connected to the second end of the fifth inductor, and the second end is connected to the first end of the fifth Josephson junction and the first end of the seventh inductor; the second end of the fifth Josephson junction is grounded; the second end of the seventh inductor generates the superconducting output signal; at this time, the second bias current is connected through the connection node between the second end of the fifth inductor and the first end of the sixth inductor.

Optionally, the interface circuit also includes: a sixth Josephson junction and an eighth inductor; wherein, the first end of the sixth Josephson junction is connected to the first end of the eighth inductor and connected to the superconducting clock signal, and the second end is grounded; the second end of the eighth inductor is connected to the second end of the first inductor; at this time, the first bias current is connected through the connection node between the second end of the eighth inductor and the second end of the first inductor.

Optionally, the interface circuit further includes: a splitter, whose input end is connected to the superconducting clock signal, a first output end is connected to the first end of the eighth inductor and outputs one path of the superconducting clock signal, and a second output end outputs another path of the superconducting clock signal.

The present invention further provides an interface module, the interface module comprising: the interface circuit as described in any one of the above items.

Optionally, the interface module further includes: a clock circuit, configured to generate the superconducting clock signal according to a CMOS clock signal.

Optionally, the clock circuit includes: a seventh Josephson junction, an eighth Josephson junction, a ninth inductor and a tenth inductor; wherein, the first end of the seventh Josephson junction is connected to the CMOS clock signal and connected to the first end of the ninth inductor, and the second end is connected to the first end of the eighth Josephson junction and connected to a third bias current; the second end of the ninth inductor is grounded; the first end of the eighth Josephson junction is connected to the first end of the tenth inductor, and the second end is grounded; the second end of the tenth inductor generates the superconducting clock signal.

Optionally, the clock circuit also includes: a ninth Josephson junction, a tenth Josephson junction and an eleventh inductor; wherein, the first end of the ninth Josephson junction is connected to the second end of the tenth inductor and the first end of the eleventh inductor and is connected to a fourth bias current, and the second end is grounded; the second end of the eleventh inductor is connected to the first end of the tenth Josephson junction and generates the superconducting clock signal; the second end of the tenth Josephson junction is grounded.

The present invention further provides an application system, comprising: a CMOS module, a superconducting module and an interface module as described in any one of the above items, wherein the interface module is connected between the CMOS module and the superconducting module.

Optionally, the application system includes a computer system.

As described above, an interface circuit, an interface module and an application system of the present invention break through the traditional design and provide a new non-return-to-zero CMOS-RSFQ interface circuit, which can be used in conjunction with a conventional interface circuit to transmit a CMOS constant-height data stream, thereby achieving the correct collection of the CMOS constant-height data stream.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing an interface circuit.

FIG. 2 shows an input and output waveform diagram of the interface circuit shown in FIG. 1 .

FIG3 shows waveforms of different input signals, where PARTA is data with a 1010 interval and PARTB is data with consecutive 1s.

FIG. 4 is a schematic diagram showing an interface circuit according to the present invention.

FIG. 5 is a schematic diagram showing another interface circuit of the present invention.

FIG6 shows the input and output waveforms of the interface circuit shown in FIG5 .

FIG. 7 is a schematic diagram showing an interface module according to the present invention.

FIG. 8 is a schematic diagram showing another interface module of the present invention.

FIG9 shows the input and output waveforms of the interface module shown in FIG8 .

FIG. 10 is a schematic diagram showing an application system of the present invention.

Component number description

10 Application System

100 CMOS Module

200 Superconducting Module

300 Interface Module

301 Interface Circuit

302 Clock Circuit

DETAILED DESCRIPTION

The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figures 1 to 10. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

FIG1 shows an interface circuit, comprising Josephson junctions J01, J02, J03, J04 and inductors L01, L02, L03; the first end of the Josephson junction J01 is connected to the first end of the inductor L01 and connected to the CMOS current signal Iin, and the second end is connected to the first end of the Josephson junction J02 and connected to the bias current I01; the second end of the inductor L01 is grounded; the first end of the Josephson junction J02 is connected to the first end of the inductor L02, and the second end is grounded; the second end of the inductor L02 is connected to the first end of the Josephson junction J03 and connected to the bias current I02; the first end of the Josephson junction J03 is connected to the first end of the inductor L03, and the second end is grounded; the second end of the inductor L03 is connected to the first end of the Josephson junction J04 and generates a superconducting pulse; the second end of the Josephson junction J04 is grounded.

Among them, the critical current of the Josephson junction J02 is larger than that of the Josephson junction J01, and the bias current I01 mainly passes through the Josephson junction J02; the bias current I01 of appropriate size is selected to make the Josephson junction J02 in a pre-critical state. When the CMOS current signal Iin is input, the current is mainly grounded through the inductor L01, and a small part will flow through the Josephson junction J01 and the Josephson junction J02. At this time, the Josephson junction J01 has no obvious change, the superconducting critical state of the Josephson junction J02 is reversed, and an RSFQ pulse is generated at the output end. At the same time, a magnetic flux quantum enters the magnetic flux loop composed of J02-L02-J03; when the CMOS current signal Iin decreases, the ring current and the bias current I01 have the same direction in the Josephson junction J01, and the opposite direction in the Josephson junction J02, so that the superconducting critical state of the Josephson junction J01 is reversed. At this time, the trapped magnetic flux quantum is released through the reversal of the Josephson junction J01, and the circuit is restored to its original state.

The interface circuit shown in Figure 1 is simulated, and the obtained input and output waveforms are shown in Figure 2; wherein, the input CMOS current signal Iin is a DC square wave, and the output end obtains a periodic RSFQ pulse; as can be seen from Figure 2, the interface circuit implements rising edge sampling, that is, the output of the RSFQ pulse only occurs at the rising edge trigger of the DC square wave.

When the interface circuit shown in FIG1 is used to transmit the input signal shown in FIG3 as a data stream, PARTA contains data that appear at intervals of 1010, and the interface circuit shown in FIG1 performs rising edge sampling on the data, only samples data once in one cycle, and converts the valid high level into an RSFQ pulse; PARTB contains data that are continuous 1s, and data loss will occur when the interface circuit shown in FIG1 performs rising edge sampling on the data, resulting in only one 1 being recognized out of the four 1s in PARTB, and in this case, three 1s will be lost.

In order to solve the problem of data loss when the interface circuit shown in FIG. 1 transmits continuous data of 1, as shown in FIG. 4, this embodiment provides a non-return-to-zero CMOS-RSFQ interface circuit 301, and the interface circuit 301 includes: a first Josephson junction J1, a second Josephson junction J2, a third Josephson junction J3, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4 and a fifth inductor L5; wherein the first end of the first Josephson junction J1 is connected to the first end of the first inductor L1 and the first end of the second inductor L2 and connected to the first bias current I1, and the second end is grounded; the second end of the first inductor L1 is connected to the first end of the second inductor L2 and connected to the first bias current I1, and the second end is grounded; the second end of the first inductor L1 is connected to the first end of the second inductor L2 and connected to the first bias current I1. A superconducting clock signal TI-RSFQ is connected; a second end of the second inductor L2 is connected to a first end of the second Josephson junction J2; a second end of the second Josephson junction J2 is connected to a first end of the third Josephson junction J3, a first end of the third inductor L3 and a first end of the fourth inductor L4; a second end of the third Josephson junction J3 is grounded; a second end of the third inductor L3 is connected to a CMOS data signal DI-COMS; a second end of the fourth inductor L4 is connected to a first end of the fifth inductor L5 and is connected to a second bias current I2; a second end of the fifth inductor L5 generates a superconducting output signal OUT-RSFQ.

In this example, the first Josephson junction J1, the second inductor L2, the second Josephson junction J2 and the third Josephson junction J3 constitute a superconducting comparator loop, and the high and low currents of the CMOS data signal DI-CMOS are used to control the working states of the second Josephson junction J2 and the third Josephson junction J3; for example, when the CMOS data signal DI-CMOS is a high current, the CMOS current flows into the superconducting comparator loop through the third inductor L3. At this time, the CMOS current is opposite to the direction of the DC current on the second Josephson junction J2 and consistent with the direction of the DC current on the third Josephson junction J3; when the CMOS data signal DI-CMOS is a low current, the CMOS current flows out of the superconducting comparator loop through the third inductor L3. At this time, the CMOS current is consistent with the direction of the DC current on the second Josephson junction J2 and opposite to the direction of the DC current on the third Josephson junction J3; the current distribution on the second Josephson junction J2 and the third Josephson junction J3 is adjusted by the high and low currents flowing through the third inductor L3, so as to realize the control of the working states of the second Josephson junction J2 and the third Josephson junction J3.

Further, as shown in FIG5 , the interface circuit 301 further includes: a fourth Josephson junction J4, a fifth Josephson junction J5, a sixth inductor L6 and a seventh inductor L7; wherein, the first end of the fourth Josephson junction J4 is connected to the connection node between the second end of the fourth inductor L4 and the first end of the fifth inductor L5, and the second end is grounded; the first end of the sixth inductor L6 is connected to the second end of the fifth inductor L5, and the second end is connected to the first end of the fifth Josephson junction J5 and the first end of the seventh inductor L7; the second end of the fifth Josephson junction J5 is grounded; the second end of the seventh inductor L7 generates the superconducting output signal OUT-RSFQ; at this time, the second bias current I2 is no longer connected through the connection node between the second end of the fourth inductor L4 and the first end of the fifth inductor L5, but is connected through the connection node between the second end of the fifth inductor L5 and the first end of the sixth inductor L6.

It should be noted that, when the interface circuit 301 includes the fourth Josephson junction J4, the fifth Josephson junction J5, the sixth inductor L6 and the seventh inductor L7, the second end of the fifth inductor L5 no longer serves as the output end of the interface circuit 301, but the second end of the seventh inductor L7 serves as the output end of the interface circuit 301 to generate the superconducting output signal OUT-RSFQ.

In this example, the third Josephson junction J3, the fourth inductor L4, the fourth Josephson junction J4, the fifth inductor L5, the sixth inductor L6 and the fifth Josephson junction J5 constitute a superconducting pulse output loop, which is used to match the input of the subsequent superconducting circuit; wherein, the third Josephson junction J3, the fourth inductor L4 and the fourth Josephson junction J4 constitute a first magnetic flux loop, and the fourth Josephson junction J4, the fifth inductor L5, the sixth inductor L6 and the fifth Josephson junction J5 constitute a second magnetic flux loop. Through the design of the secondary magnetic flux loop, stable signal output can be achieved.

When the current flowing into the superconducting comparator loop exceeds a certain value, the third Josephson junction J3 is in a critical trigger state. At this time, the superconducting clock signal TI-RSFQ will give a superconducting current to the second Josephson junction J2 and the third Josephson junction J3, so that the third Josephson junction J3 is triggered and generates a ring current, which will cause the reversal of the fourth Josephson junction J4 after a short delay, and the pulse transmission will proceed backward in sequence.

Further, as shown in FIG5 , the interface circuit 301 further includes: a sixth Josephson junction J6 and an eighth inductor L8; wherein, a first end of the sixth Josephson junction J6 is connected to a first end of the eighth inductor L8 and connected to the superconducting clock signal TI-RSFQ, and a second end is grounded; a second end of the eighth inductor L8 is connected to a second end of the first inductor L1; at this time, the first bias current I1 is no longer connected through a connection node between a first end of the first inductor L1 and a first end of the second inductor L2, but is connected through a connection node between a second end of the eighth inductor L8 and a second end of the first inductor L1.

It should be noted that, when the interface circuit 301 includes the sixth Josephson junction J6 and the eighth inductor L8, the second end of the first inductor L1 no longer serves as the clock input end of the interface circuit 301, but the first end of the eighth inductor L8 serves as the clock input end of the interface circuit 301 to access the superconducting clock signal TI-RSFQ.

In this example, input buffering is performed through the design of the sixth Josephson junction J6 and the eighth inductor L8 to achieve stable input.

Furthermore, as shown in Figure 5, the interface circuit 301 also includes: a splitter SPL, an input end of which is connected to the superconducting clock signal TI-RSFQ, a first output end is connected to the first end of the eighth inductor L8 and outputs one path of the superconducting clock signal TI-RSFQ, and a second output end outputs another path of the superconducting clock signal TI-RSFQ.

It should be noted that when the interface circuit 301 includes the splitter SPL, the first end of the eighth inductor L8 no longer serves as the clock input end of the interface circuit 301, but the input end of the splitter SPL serves as the clock input end of the interface circuit 301 to access the superconducting clock signal TI-RSFQ.

In this example, the splitter SPL is a one-to-two circuit, which is used to split the superconducting clock signal TI-RSFQ into two outputs, one of which is used as the clock input of the interface circuit 301, and the other is transmitted to the subsequent circuit.

Taking the interface circuit 301 shown in FIG5 as an example, a simulation is performed on it, and the obtained input and output waveforms are shown in FIG6 ; wherein the CMOS data signal DI-COMS is a DC square wave, and the superconducting clock signal TI-RSFQ and the superconducting output signal OUT-RSFQ are superconducting pulses.

As can be seen from FIG6 , when the CMOS data signal DI-CMOS is constantly high, the interface circuit 301 performs data sampling according to the falling edge of the superconducting clock signal TI-RSFQ. Three clock falling edges appear within the constant high period in the simulation waveform. Therefore, three corresponding superconducting output signals OUT-RSFQ are output.

As shown in FIG. 7 and FIG. 8 , this embodiment further provides an interface module 300 , and the interface module 300 includes: the interface circuit 301 as described above.

Furthermore, the interface module 300 also includes: a clock circuit 302, which is used to generate the superconducting clock signal TI-RSFQ according to the CMOS clock signal TI-CMOS.

In practical applications, the CMOS clock signal TI-CMOS is a DC square wave, the superconducting clock signal TI-RSFQ is a superconducting pulse, and the clock circuit 302 can be a conventional CMOS-RSFQ interface circuit that performs data sampling at the rising edge or the falling edge, thereby outputting the superconducting clock signal TI-RSFQ at the rising edge or the falling edge of the CMOS clock signal TI-CMOS.

Specifically, the clock circuit 302 includes: a seventh Josephson junction J7, an eighth Josephson junction J8, a ninth inductor L9 and a tenth inductor L10; wherein, the first end of the seventh Josephson junction J7 is connected to the CMOS clock signal TI-CMOS and connected to the first end of the ninth inductor L9, and the second end is connected to the first end of the eighth Josephson junction J8 and connected to the third bias current I3; the second end of the ninth inductor L9 is grounded; the first end of the eighth Josephson junction J8 is connected to the first end of the tenth inductor L10, and the second end is grounded; the second end of the tenth inductor L10 generates the superconducting clock signal TI-RSFQ.

It should be noted that, since the RSFQ circuit senses a current signal, the rising edge trigger or the falling edge trigger depends on the direction in which the input inductor (i.e., the ninth inductor L9) is placed. In this example, the clock circuit 302 is changed to a falling edge trigger by changing the direction in which the input inductor is placed. The specific working principle is roughly the same as above and will not be repeated here.

More specifically, the clock circuit 302 also includes: a ninth Josephson junction J9, a tenth Josephson junction J10 and an eleventh inductor L11; wherein, a first end of the ninth Josephson junction J9 is connected to a second end of the tenth inductor L10 and a first end of the eleventh inductor L11 and is connected to a fourth bias current I4, and a second end is grounded; a second end of the eleventh inductor L11 is connected to a first end of the tenth Josephson junction J10 and generates the superconducting clock signal TI-RSFQ; and a second end of the tenth Josephson junction J10 is grounded.

In this example, stable signal output can be achieved through the design of the ninth Josephson junction J9, the tenth Josephson junction J10 and the eleventh inductor L11.

Taking the interface module 300 shown in Figure 8 as an example, the signal conversion process of the interface module 300 described in this embodiment is as follows: the CMOS clock signal TI-CMOS generates a superconducting clock signal TI-RSFQ through the clock circuit 302 and serves as the clock input of the interface circuit 301, and the CMOS data signal DI-CMOS forms a non-return-to-zero data code through the interface circuit 301; through the mutual cooperation of the interface circuit 301 and the clock circuit 302, the correct collection of the constant high data stream of the CMOS data signal DI-CMOS can be achieved.

The interface module 300 shown in FIG8 is simulated, and the obtained input and output waveforms are shown in FIG9 ; wherein the CMOS clock signal TI-CMOS and the CMOS data signal DI-COMS are DC square waves, and the superconducting clock signal TI-RSFQ and the superconducting output signal OUT-RSFQ are superconducting pulses.

As can be seen from FIG9 , a superconducting clock signal TI-RSFQ is generated at the falling edge of the CMOS clock signal TI-CMOS. When the superconducting clock signal TI-RSFQ is valid, whether the superconducting output signal OUT-RSFQ is output is determined based on whether the collected CMOS data signal DI-CMOS is high or low, thereby achieving correct collection of the constant high data stream of the CMOS data signal DI-CMOS.

As shown in FIG. 10 , this embodiment further provides an application system 10 , which includes: a CMOS module 100 , a superconducting module 200 , and the interface module 300 as described above, wherein the interface module 300 is connected between the CMOS module 100 and the superconducting module 200 .

Specifically, the application system includes a computer system. More specifically, the CMOS module 100 includes an SRAM memory and a signal amplifier, and the superconducting module 200 includes a superconducting CPU; wherein the superconducting CPU is connected to the signal amplifier via an RSFQ-CMOS interface circuit, the signal amplifier is connected to the SRAM memory, and the SRAM memory is connected to the superconducting CPU via the CMOS-RSFQ interface circuit as described above.

In practical applications, the superconducting CPU outputs control signals, data and address bits to the signal amplifier through the RSFQ-CMOS interface circuit, and the signal amplifier amplifies its input signal until the working threshold of the SRAM memory is met to control the read and write operations of the SRAM memory, and provide the SRAM memory with the address of reading data or writing data; when the SRAM memory completes the corresponding read and write operations according to the instructions, the corresponding read data, response signal and other identification bits are transmitted back to the superconducting CPU through the CMOS-RSFQ interface circuit.

In summary, the interface circuit, interface module and application system of the present invention break through the traditional design and provide a new non-return-to-zero CMOS-RSFQ interface circuit, which can be used in conjunction with a conventional interface circuit to transmit a CMOS constant-height data stream, thereby achieving the correct collection of the CMOS constant-height data stream. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims (10)

1. An interface circuit, characterized in that the interface circuit comprises: a first Josephson junction, a second Josephson junction, a third Josephson junction, a first inductor, a second inductor, a third inductor, a fourth inductor and a fifth inductor; wherein, The first end of the first Josephson junction is connected to the first end of the first inductor and the first end of the second inductor and is connected to the first bias current, and the second end is grounded; the second end of the first inductor is connected to the superconducting clock signal; the second end of the second inductor is connected to the first end of the second Josephson junction; the second end of the second Josephson junction is connected to the first end of the third Josephson junction, the first end of the third inductor and the first end of the fourth inductor; the second end of the third Josephson junction is grounded; the second end of the third inductor is connected to the CMOS data signal; the second end of the fourth inductor is connected to the first end of the fifth inductor and is connected to the second bias current; the second end of the fifth inductor generates a superconducting output signal. 2. The interface circuit according to claim 1, characterized in that the interface circuit further comprises: a fourth Josephson junction, a fifth Josephson junction, a sixth inductor and a seventh inductor; wherein, The first end of the fourth Josephson junction is connected to the connection node of the second end of the fourth inductor and the first end of the fifth inductor, and the second end is grounded; the first end of the sixth inductor is connected to the second end of the fifth inductor, and the second end is connected to the first end of the fifth Josephson junction and the first end of the seventh inductor; the second end of the fifth Josephson junction is grounded; the second end of the seventh inductor generates the superconducting output signal; At this time, the second bias current is connected through the connection node between the second end of the fifth inductor and the first end of the sixth inductor. 3. The interface circuit according to claim 1, characterized in that the interface circuit further comprises: a sixth Josephson junction and an eighth inductor; wherein, The first end of the sixth Josephson junction is connected to the first end of the eighth inductor and connected to the superconducting clock signal, and the second end is grounded; the second end of the eighth inductor is connected to the second end of the first inductor; At this time, the first bias current is connected through the connection node between the second end of the eighth inductor and the second end of the first inductor. 4. The interface circuit according to claim 3 is characterized in that the interface circuit also includes: a splitter, an input end of which is connected to the superconducting clock signal, a first output end is connected to the first end of the eighth inductor and outputs one path of the superconducting clock signal, and a second output end outputs another path of the superconducting clock signal. 5. An interface module, characterized in that the interface module comprises: the interface circuit according to any one of claims 1 to 4. 6 . The interface module according to claim 5 , further comprising: a clock circuit for generating the superconducting clock signal according to a CMOS clock signal. 7. The interface module according to claim 6, characterized in that the clock circuit comprises: a seventh Josephson junction, an eighth Josephson junction, a ninth inductor and a tenth inductor; wherein, The first end of the seventh Josephson junction is connected to the CMOS clock signal and connected to the first end of the ninth inductor, and the second end is connected to the first end of the eighth Josephson junction and connected to the third bias current; the second end of the ninth inductor is grounded; the first end of the eighth Josephson junction is connected to the first end of the tenth inductor, and the second end is grounded; the second end of the tenth inductor generates the superconducting clock signal. 8. The interface module according to claim 7, characterized in that the clock circuit further comprises: a ninth Josephson junction, a tenth Josephson junction and an eleventh inductor; wherein, The first end of the ninth Josephson junction is connected to the second end of the tenth inductor and the first end of the eleventh inductor and is connected to the fourth bias current, and the second end is grounded; the second end of the eleventh inductor is connected to the first end of the tenth Josephson junction and generates the superconducting clock signal; the second end of the tenth Josephson junction is grounded. 9. An application system, characterized in that the application system comprises: a CMOS module, a superconducting module and an interface module according to any one of claims 5 to 8, wherein the interface module is connected between the CMOS module and the superconducting module. 10. The application system according to claim 9, characterized in that the application system comprises a computer system.