CN114937420A - Display panel and display device - Google Patents

Abstract

The invention discloses a display panel and a display device, comprising a display area and a non-display area at least partially surrounding the display area; the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form steps, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps; the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits. The electrostatic protection area is arranged at the step, so that the non-display area can be further compressed in the column direction, and a narrow frame is realized.

Description

Display panels and display devices

technical field

The present invention relates to the field of display technology, and more particularly, to a display panel and a display device.

Background technique

Traditional display devices include monitors, televisions, mobile phones, tablet computers, etc. With the development of electronic technology, the manufacture of display panels has also become mature. The display panels provided by the existing technology include liquid crystal display panels, organic light-emitting display panels, plasma display panels panel, etc.

Liquid Crystal Display (LCD), as a display panel with a relatively mature production process, occupies a large market in the display panel field due to its low cost, good production yield and good display effect. Liquid crystal display devices have many advantages such as thin body, power saving, and no radiation, and have been widely used, such as LCD TVs, mobile phones, personal digital assistants, digital cameras, computer screens or notebook computer screens, etc. In the field of flat panel display Dominant; organic light-emitting diodes, as a current-type light-emitting device, have been increasingly used in high-performance displays. OLED display panels have self-illumination, wide viewing angle, fast response speed, high contrast, wide color gamut, Low energy consumption, thin panel, rich colors, flexible display, wide operating temperature range and many other excellent features, so it is known as the next generation of "star" flat panel display technology. The OLED display panel includes an anode and a cathode, and a hole transport layer, an organic light-emitting layer and an electron transport layer arranged between the anode and the cathode. The anode provides hole injection, and the cathode provides electron injection. The holes and electrons injected by the cathode and the anode recombine in the organic light-emitting layer to form electron-hole pairs (ie excitons) at the bound energy level, and the excitons are de-excited by radiation to emit photons to generate visible light.

In recent years, smart wearable devices have become more and more popular among users based on many advantages such as easy portability, fashion and beauty. With the application of display technology in smart wearables and other portable electronic devices, there are various requirements for the shape of the display panel, followed by the appearance of special-shaped display panels.

In order to increase the beauty of the display screen and appearance of the smart wearable device, the display panel of the smart wearable device has an increasing demand for narrow bezels, but the display panel in the related art cannot compress the lower bezel, thus hindering the realization of the narrow bezel.

Therefore, there is an urgent need to provide a display panel and a display device to achieve narrow bezels.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a display panel and a display device to realize a narrow frame.

In one aspect, the present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area;

The display area includes a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area includes a plurality of steps, and the number of pixels in two adjacent pixel rows is not equal or in two adjacent pixel columns. The number of pixels is not equal to form the step, the non-display area includes a first non-display area, and the first non-display area is adjacent to the step;

The first non-display area includes an electrostatic protection area, the electrostatic protection area includes a plurality of electrostatic protection circuits, and a multiplexer is included between some of the electrostatic protection circuits.

In another aspect, the present invention also provides a display device including the above-mentioned display panel.

Compared with the prior art, the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

A display panel of the present invention includes: a display area and a non-display area at least partially surrounding the display area; the display area includes a plurality of pixel rows and a plurality of pixel columns, and the periphery of the display area includes a plurality of Steps, the number of pixels in two adjacent pixel rows is not equal or the number of pixels in two adjacent pixel columns is not equal to form the ladder, the non-display area includes a first non-display area, the The first non-display area is adjacent to the step; the first non-display area includes an electrostatic protection area, the electrostatic protection area includes a plurality of electrostatic protection circuits, and some of the electrostatic protection circuits include a multiplexer between them . The lower border area of the display panel has a stepped area and a fan-out routing area. The fan-out routing area is located between the stepped area and the display area. A multiplexer and an electrostatic protection circuit need to be set in the stepped area. The circuit occupies the space in the horizontal direction, so the multiplexer cannot be in one-to-one correspondence with the pixel columns in the display area, and must be electrically connected to the data line or touch line in the display area by winding. It will occupy vertical space, that is, the lower frame cannot be compressed in the vertical direction, which prevents the lower frame from realizing a narrow frame. In the present invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the step. The step is formed due to the unequal number of pixels in adjacent pixel rows or adjacent pixel columns. Only the multiplexer can be set in the area, which makes full use of the space at the corresponding step position in the lower frame. Of course, the multiplexer can correspond to as many pixel columns as possible to reduce the number of windings, thereby reducing the The width of the fan-out routing area in the longitudinal direction can further compress the lower frame to realize a narrow frame.

Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

1 is a schematic plan view of a display panel in the related art;

Fig. 2 is a partial enlarged view of M region in Fig. 1;

3 is a schematic plan view of a display panel provided by the present invention;

Fig. 4 is a partial enlarged view of N region in Fig. 3;

Fig. 5 is another partial enlarged view of N region in Fig. 3;

Fig. 6 is another kind of partial enlarged view of N region in Fig. 3;

Fig. 7 is another partial enlarged view of N region in Fig. 3

Fig. 8 is another partial enlarged view of N region in Fig. 3;

Fig. 9 is another partial enlarged view of N region in Fig. 3;

10 is a schematic plan view of another display panel provided by the present invention;

Fig. 11 is a partial enlarged view of the Q region in Fig. 10;

Fig. 12 is a plan view of the electrostatic protection circuit in Fig. 11;

Fig. 13 is a kind of sectional view of K-K' in Fig. 11;

Fig. 14 is another sectional view of K-K' direction in Fig. 11;

Fig. 15 is another sectional view of K-K' in Fig. 11;

16 is a partial enlarged view of the first sub-non-display area and the second sub-non-display area in FIG. 9;

17 is a schematic plan view of another display panel provided by the present invention;

FIG. 18 is a schematic plan view of a display device provided by the present invention.

Detailed ways

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification.

In all examples shown and discussed herein, any specific values should be construed as illustrative only and not limiting. Accordingly, other instances of the exemplary embodiment may have different values.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

In view of the problem that it is difficult to compress the lower frame of the display panel of the related art, the inventor has carried out the following research on the related art: Referring to FIG. 1, FIG. A partial enlarged view of the area, the display panel in FIG. 1 may be a smart wearable device, and may be circular. The display panel 0000 includes a display area AA and a non-display area BB surrounding the display area AA. The non-display area includes a lower border 801, and the lower The frame 801 includes a binding area 01, an encapsulation area 02, a step area 03 and a fan-out routing area 04 arranged in sequence. A multiplexer 050 and an electrostatic protection circuit 0400 need to be set in the step area 03, as shown in FIG. 2 . , the output end of the multiplexer 050 is electrically connected to the data lines in the display area AA. Since more multiplexers 050 and electrostatic protection circuits 0400 need to be set in the step area 03, more The spacing of the multiplexers 050 is not equal to the spacing of the pixels PX, that is, the multiplexer 050 and the pixel columns in the column direction Y are not in a one-to-one correspondence, so there needs to be routing and display in the fan-out routing area 04 The data lines in the area AA are electrically connected, and the windings are arranged along the column direction Y, so the lower frame cannot be compressed in the column direction Y.

In order to solve the above technical problems, the present invention provides a display panel and a display device, and the specific embodiments of the display panel and the display device will be described in detail below.

Referring to FIGS. 3 and 4 , FIG. 3 is a schematic plan view of a display panel provided by the present invention, and FIG. 4 is a partial enlarged view of the N region in FIG. 3 . The display panel 100 provided in this embodiment includes: a display area AA and a non-display area BB at least partially surrounding the display area AA;

The display area AA includes a plurality of pixel rows 10 and a plurality of pixel columns 20, the periphery of the display area AA includes a plurality of steps 30, and the number of pixels PX in two adjacent pixel rows 10 is not equal or in two adjacent pixel columns 20. The number of pixels PX is not equal to form a step 30, the non-display area BB includes a first non-display area BB1, and the first non-display area BB1 is adjacent to the step 30;

The first non-display area BB1 includes an electrostatic protection area 40 , the electrostatic protection area 40 includes a plurality of electrostatic protection circuits 400 , and a multiplexer 60 is included between some of the electrostatic protection circuits 400 .

Specifically, FIG. 3 only takes the display panel 100 as a circular display panel 100 as an example for illustration, of course, it can also be other special-shaped display panels 100, as long as there are two adjacent pixel rows 10 in the display panel 100 in an unequal number or the same number The number of pixels PX in two adjacent pixel columns 20 is not equal to form the steps 30 . In FIG. 3 , only the non-display area BB completely surrounds the display area AA as an example. Of course, the non-display area BB can also half surround the display area AA, such as a water drop screen or a notch screen, which is not specifically limited here. The number of pixels PX in FIG. 3 is only for schematic illustration, and is not limited to actual products.

FIG. 4 also shows the signal lines in the package area 2 (not shown in FIG. 3 ) and the first pads 51 in the bonding area 1 (as shown in FIGS. 3 and 4 ). Of course, the The flexible circuit board is bound in the binding area 1, and the second pads 52 on the flexible circuit board are electrically connected to the first pads 51 in one-to-one correspondence. In this embodiment, a chip-on-film (COF) is used as an example, that is, a die soft film that fixes a driver chip IC on a flexible circuit board, and a flexible additional circuit board is used as a package chip carrier to combine the chip with a flexible substrate circuit, or It refers to a flexible additional circuit board without a packaged chip; of course, the flexible circuit board in the present invention may also have no driver chip IC, and at this time, the driver chip IC can be directly made in the binding area 1 of the display panel 100, that is for COG technology.

In this embodiment, the display area AA includes a plurality of pixel rows 10 and a plurality of pixel columns 20, each pixel row 10 is composed of pixels PX arranged in the row direction X, and each pixel column 20 is formed by Of course, the display panel 100 also includes data lines (not shown in the figure) extending along the row direction X and scan lines (not shown in the figure) extending along the row direction X. It can be seen from FIG. 4 that the number of pixels PX in pixel row 1001 and pixel row 1002 is not equal, the number of pixels PX in pixel row 1002 and pixel row 1003 is not equal, and the number of pixels PX in pixel row 1003 and pixel row 1004 is not equal , exactly, the number of pixels PX in pixel row 1001 is less than the number of pixels PX in pixel row 1002, and the number of pixels PX in pixel row 1002 is less than the number of pixels PX in pixel row 1003, so the position of pixel row 1001 and pixel row 1002 , and the positions of the pixel row 1002 and the pixel row 1003 form a ladder 30; of course, it can also be regarded as a ladder 30 formed by two adjacent pixel columns 20. Specifically, the number of pixels PX in the pixel row 2001 and the pixel row 2002 is not equal, The number of pixels PX in pixel row 2003 and pixel row 2004 is not equal, and the number of pixels PX in pixel row 2005 and pixel row 2006 is not equal. Specifically, the number of pixels PX in pixel row 2001 is less than that in pixel row 2002. The number of pixels PX in 2003 is less than the number of pixels PX in the pixel row 2004 , and the number of pixels PX in the pixel row 2005 is less than the number of pixels PX in the pixel row 2006 , thus forming the ladder 30 .

The non-display area BB includes a first non-display area BB1, and the first non-display area BB1 is adjacent to the step 30. As shown in FIG. 3 and FIG. Correspondingly and adjacently, the first non-display area BB1 includes an electrostatic protection area 40 , and the electrostatic protection area 40 includes an electrostatic protection circuit 400 . The electrostatic protection circuit 400 is used to export the static electricity in the display panel 100 to prevent static electricity from entering the interior of the display panel 100 . Electrostatic breakdown occurs, which affects the performance of the display panel 100 . A multiplexer 60 is included between part of the electrostatic protection circuit 400 in the electrostatic protection area 40. In order to reduce the number of pads of the driver chip IC, the multiplexer 60 usually provides a signal to a plurality of data lines through one signal line , this signal line is connected to the plurality of data lines through switches, and the reception of data signals on the corresponding data lines is controlled by the switches.

In the column direction Y in FIG. 4 , the lengths of the multiplexer 60 in the first non-display area BB1 and the electrostatic protection circuit 400 in the column direction Y are inconsistent. The length is greater than the length of the multiplexer 60 in the column direction Y as an example. Of course, the length of the electrostatic protection circuit 400 in the column direction Y can be equal to the length of the multiplexer 60 in the column direction Y, which is not done here. Specific restrictions.

It can be understood that in this embodiment, the electrostatic protection circuit 400 originally arranged in the step area 3 is arranged in the first non-display area BB1 corresponding to the step 30, and the step 30 is caused by the adjacent pixel row 10 or the adjacent pixel column. The number of pixels PX in the 20 is unequal, so that only the multiplexer 60 is set in the step area 3, and the space at the position corresponding to the step 30 in the lower frame 801 is fully utilized. Of course, the multiplexer 60 can As many as possible one-to-one correspondence with the pixel columns 20, reducing the number of windings, thereby reducing the width of the fan-out routing area 4 in the longitudinal direction, so that the lower frame 801 can be further compressed to achieve a narrow frame; on the other hand, the Part of the multiplexers 60 originally arranged in the step area 3 is transferred to the first non-display area BB1, which can further increase the spacing of the multiplexers 60 in the step area 3, making it the same as the pixel row 20. A correspondence. Furthermore, due to the position of the step 30, the width of the first non-display area BB1 in the column direction Y is greater than the width of the step area 3 in the column direction Y, so the width in the column direction Y is sufficient to arrange the electrostatic protection circuit 400. , the length of the electrostatic protection circuit 400 in the column direction Y can be set to be larger, thereby maximizing the utilization of space.

In some optional embodiments, with continued reference to FIG. 4 , the electrostatic protection circuits 400 are arranged along the row direction X and extend along the column direction Y.

It can be seen from FIG. 4 that the first non-display area BB1 is only adjacent to the step area 3 in the row direction X, so this area is parallel to the step area 3, and the setting direction of the electrostatic protection circuit 400 in this area can be multiplexed with that in the step area 3. The arrangement direction of the devices 60 may be the same, and there is no need to rotate or tilt the electrostatic protection circuit 400 in the area, which is more convenient for production.

In some alternative embodiments, with continued reference to FIG. 4, the multiplexers 60 are arranged along the row direction X and extend along the column direction Y.

It can be seen from FIG. 4 that the first non-display area BB1 is only adjacent to the step area 3 in the row direction X, so the first non-display area BB1 is parallel to the step area 3, and the setting of the multiplexer 601 in the first non-display area BB1 The direction may be the same as the arrangement direction of the multiplexers 602 in the step area 3. Of course, the length of the multiplexers 601 in the first non-display area BB1 in the column direction Y may be longer than that in the step area 3. The length of the multiplexer 602 in the column direction Y is equal, or the width of the multiplexer 601 in the row direction X in the first non-display area BB1 is the same as the width of the multiplexer 602 in the row direction X in the step area 3 The widths of the two regions are equal, so that the multiplexers 60 in the two regions can be fabricated at the same time, which reduces the difficulty of fabrication.

In some optional embodiments, referring to FIG. 5 , FIG. 6 and FIG. 7 , FIG. 5 is another partial enlarged view of the N region in FIG. 3 , and FIG. 6 is another partial enlarged view of the N region in FIG. 3 7 is another partial enlarged view of the N area in FIG. 3, along the row direction X, the electrostatic protection circuit 400 and the multiplexer 60 are alternately arranged.

5 to 7 , the electrostatic protection circuits 400 and the multiplexers 60 in the first non-display area BB1 in FIG. 5 are alternately arranged one by one, and the electrostatic protection circuits 400 in the first non-display area BB1 in FIG. The multiplexers 60 are arranged at intervals, and the electrostatic protection circuits 400 and the multiplexers 60 in the first non-display area BB1 in FIG. 7 are alternately arranged in two-three-two-one, that is, along the first non-display area Two electrostatic protection circuits 400 , three multiplexers 60 , three electrostatic protection circuits 400 , and one multiplexer 60 are arranged in the direction of BB1 pointing to the step area 3 . Of course, no electrostatic protection is used here. The number of alternately arranged circuits 400 and multiplexers 60 is specifically limited, and of course, the arrangement of the electrostatic protection circuits 400 and multiplexers 60 is not specifically limited, as long as electrostatic protection is provided in the electrostatic protection area 40 The circuit 400 and the multiplexer 60 are all that is needed. Since all the electrostatic protection circuits 400 and the multiplexer 60 originally arranged in the step area 3 are partially arranged in the first non-display area BB1 corresponding to the step area 30, In this way, only the multiplexer 60 can be arranged in the step area 3, and the space at the position corresponding to the step 30 in the lower frame 801 is fully utilized. The number of windings is reduced, thereby reducing the width of the fan-out routing area 4 in the longitudinal direction, thereby further compressing the lower frame 801 to realize a narrow frame.

In some optional embodiments, referring to FIG. 8 , FIG. 8 is another partial enlarged view of the N region in FIG. 3 , the steps 30 in this embodiment include adjacent first steps 301 and second steps 302 . The number of pixels PX in the pixel row 10 of the first step 301 is m, and the number of pixels PX in the pixel row 10 of the second step 302 is n, where m and n are both positive integers, and m is greater than n;

The first non-display area BB1 includes a first sub-non-display area BB11 and a second sub-non-display area BB12, the first sub-non-display area BB11 is adjacent to the first step 301, and the second sub-non-display area BB12 is adjacent to the second step 302 adjacent;

The electrostatic protection area 40 of the first sub-non-display area BB11 includes a first electrostatic protection circuit 401; the electrostatic protection area 40 of the second sub-non-display area BB12 includes a second electrostatic protection circuit 402;

Along the row direction X, the width of the first electrostatic protection circuit 401 is smaller than the width of the second electrostatic protection circuit 402;

In the column direction Y, the length of the first electrostatic protection circuit 401 is greater than the length of the second electrostatic protection circuit 402 .

Referring to FIG. 8 , the ladder 30 includes adjacent first ladders 301 and second ladders 302 . The number of pixels PX in the pixel row 10 of the first ladder 301 is different from the number of pixels PX in the pixel row 10 of the second ladder 302 . The number of pixels PX in the pixel row 10 of the first step 301 is m, and the number of pixels PX in the pixel row 10 of the second step 302 is n, and m is greater than n, that is, the distance between the first step 301 and the binding area 1 is greater than that of the first step 301. The distance between the second step 302 and the binding area 1, the corresponding space of the first sub-non-display area BB11 in the column direction Y is greater than the distance of the second sub-non-display area BB12 in the column direction Y, and the first sub-non-display area BB11 The electrostatic protection area 40 includes a first electrostatic protection circuit 401, and the electrostatic protection area 40 of the second sub-non-display area BB12 includes a second electrostatic protection circuit 402. The first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 are both along the line The arrangement in the direction X extends in the column direction Y, that is, the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 are not arranged in rotation, which is convenient for fabrication.

The optional first sub-non-display area BB11 is located on the side of the second sub-non-display area BB12 away from the step area 3 , that is, the second sub-non-display area BB12 is adjacent to the step area 3 . This embodiment only schematically shows the width of the first multiplexer 60a in the first sub-non-display area BB11 in the row direction X and the second multiplexer in the second sub-non-display area BB12 The width of the multiplexer 60b in the row direction X is not equal, while the length of the first multiplexer 60a in the first sub-non-display area BB11 in the column direction Y and the length in the second sub-non-display area BB12 are not equal. The lengths of the second multiplexer 60b in the column direction Y are not equal, of course, the width of the first multiplexer 60a in the row direction X of the first multiplexer 60a located in the first sub non-display area BB11 may be the same as that of the second sub-display area BB11. The widths of the second multiplexers 60b in the non-display area BB12 in the row direction X are equal, while the lengths of the first multiplexers 60a in the first sub-non-display area BB11 in the column direction Y are equal to The lengths of the second multiplexers 60b in the second sub-non-display area BB12 in the column direction Y are the same, which are not specifically limited here.

In FIG. 8, the second step 302 is located at the pixel row 1001 and the pixel row 1002, and the first step 301 is located at the pixel row 1002 and the pixel row 1003, so the length of the first electrostatic protection circuit 401 in the column direction Y can be set to be larger That is, the length of the first electrostatic protection circuit 401 in the column direction Y is greater than the length of the second electrostatic protection circuit 402 in the column direction Y, but in order to ensure the electronic components in the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 Therefore, the width of the first electrostatic protection circuit 401 in the row direction X is smaller than the width of the second electrostatic protection circuit 402 in the row direction X to ensure that the first electrostatic protection circuit 401 and the second electrostatic protection circuit 402 can both Play the role of electrostatic protection.

Of course, this embodiment also has the technical effects of any of the above-mentioned embodiments, which will not be repeated here. In addition, in this embodiment, the spatial difference between the first sub-non-display area BB11 and the second sub-non-display area BB12 in the column direction Y is fully utilized to A first electrostatic protection circuit 401 and a second electrostatic protection circuit 402 with different widths and lengths are respectively provided.

In some optional embodiments, referring to FIG. 9 , FIG. 9 is another partial enlarged view of the N region in FIG. 3 , the electrostatic protection area 40 of the first sub-non-display area BB11 includes and further includes a first multiplexer 60a, the electrostatic protection area 40 of the second sub-non-display area BB12 further includes a second multiplexer 60b;

Along the row direction X, the width of the first multiplexer 60a is equal to the width of the second multiplexer 60b; along the column direction Y, the length of the first multiplexer 60a is equal to the second multiplexer 60b. the length of the device 60b.

9, the electrostatic protection area 40 of the first sub-non-display area BB11 further includes a first multiplexer 60a, the first multiplexer 60a is between the first electrostatic protection circuits 401, and the second sub-non-display area The electrostatic protection area 40 of the area BB12 further includes a second multiplexer 60b between the second electrostatic protection circuits 402 and the first multiplexer 60a in the row direction X. The width is equal to the width of the second multiplexer 60b in the row direction X, and the length of the first multiplexer 60a in the column direction Y is equal to the length of the second multiplexer 60b in the column direction Y In this way, the first multiplexer 60a and the second multiplexer 60b can be fabricated at the same time, which simplifies the fabrication process.

Optionally, the first multiplexer 60a and the second multiplexer 60b can also be fabricated simultaneously with the multiplexer 60 in the step area 3, and the width in the row direction X and the column direction Y The lengths are all equal, which is more conducive to production and further simplifies the production process.

In some optional embodiments, with continued reference to FIG. 3 and FIG. 8 , the non-display area BB includes an upper frame 802 and a lower frame 801 oppositely arranged along the column direction Y;

The display panel 100 includes K pixel rows 10, the lower frame 801 includes a stepped area 3, a fan-out routing area 4, and a first non-display area BB1, along the column direction Y, the fan-out routing area 4 is located in the stepped area 3 and the Kth Between the pixel rows 10, along the row direction X, the second step 302 is located on the side of the first step 301 close to the fan-out routing area 4;

The step area 3 includes a third multiplexer 60c, and along the row direction X, the width of the third multiplexer 60c is greater than that of the second multiplexer 60b; along the column direction Y, the third multiplexer 60c has a width greater than that of the second multiplexer 60b. The length of the multiplexer 60c is smaller than the length of the second multiplexer 60b.

3, the display panel 100 includes K pixel rows 10, the lower frame 801 includes a stepped area 3, a fan-out routing area 4, and a first non-display area BB1, along the column direction Y, the fan-out routing area 4 is located in the stepped area Between 3 and the Kth pixel row 10, that is, the fan-out routing area 4 is adjacent to the last row of pixel row 10, along the row direction X, the second step 302 is located on the side of the first step 301 close to the fan-out routing area 4 , the second sub-non-display area BB12 of the first non-display area BB1 is located on the side of the first sub-non-display area BB11 of the first non-display area BB1 close to the step area 3, and a third multiplexer is set in the step area 3 In the row direction X, the width of the third multiplexer 60c is greater than the width of the second multiplexer 60b; along the column direction Y, the length of the third multiplexer 60c is smaller than that of the second multiplexer 60c The length of the multiplexer 60b, as shown in FIG. 8, in the row direction X, since part of the multiplexer 60 in the step area 3 is arranged in the first non-display area BB1, so in the row direction The space in the step area 3 on X is sufficient, at this time along the row direction X, the width of the third multiplexer 60c is greater than the width of the second multiplexer 60b, and the second sub-non-display area BB12 The length in the column direction Y will be greater than the length of the step region 3 in the column direction Y, so the length of the second multiplexer 60b in the column direction Y may be greater than the length of the third multiplexer 60c in the column direction length on Y. Therefore, the space of the second sub-non-display area BB12 adjacent to the step area 3 is fully utilized.

In some optional embodiments, referring to FIG. 10 and FIG. 11 , FIG. 10 is a schematic plan view of another display panel provided by the present invention; FIG. 11 is a partial enlarged view of the Q area in FIG. 10 , the non-display area BB also includes a gate drive circuit 90;

The non-display area BB further includes a gate driving signal line X11 surrounding the display area AA, and the gate driving signal line X11 is electrically connected to the gate driving circuit 90 and the electrostatic protection circuit 400 respectively.

The gate driving signal line X11 is not shown in FIG. 10 , the gate driving circuit 90 is used to realize the progressive scanning of the scanning lines in the pixel PX. For the circular display panel 100 , the gates in the left frame 803 and the right frame 804 The axis of the driving circuit 90 needs to match the diameter of the circular display panel 100 , that is, the gate driving circuit 90 needs to be rotated to a certain extent. Static electricity will be generated in the process of manufacturing the display panel 100, so the gate driving signal line X11 is connected to the electrostatic protection circuit 400 by setting the electrostatic protection circuit 400. In one embodiment, each electrostatic protection circuit 400 is connected to a different gate driving signal line X11. , that is, the number of the electrostatic protection circuits 400 corresponds to the number of the gate drive signal lines X11 one-to-one, so as to ensure that each gate drive signal line X11 can realize electrostatic protection. Of course, it can also be set according to the needs of electrostatic protection. This application does not make further limitations.

In some optional embodiments, referring to FIG. 12 , FIG. 12 is a plan view of the electrostatic protection circuit in FIG. 11 , FIG. 13 is a cross-sectional view of FIG. Another cross-sectional view in the direction of K', Fig. 15 is another cross-sectional view in the direction of K-K' in Fig. 11 .

The display panel 100 includes a base substrate C01, a first metal layer C03 located on one side of the base substrate C01, a capacitive metal layer C04 located on a side of the first metal layer C03 away from the base substrate C01, and a capacitive metal layer C04 located away from the substrate. The second metal layer C05 on the side of the substrate C01, the third metal layer C06 on the side of the second metal layer C05 away from the base substrate C01, the gate driving signal line X11 is the same layer as the second metal layer C05, the electrostatic protection circuit 400 It includes a first transistor T1 and a second transistor T2 connected in parallel. The drain of the first transistor T1 and the drain of the second transistor T2 are electrically connected to the gate driving signal line X11 through the first conductive part DD, and the first conductive part DD is electrically connected to the gate driving signal line X11. The first metal layer C03 is the same layer, or the first conductive portion DD and the capacitor metal layer C04 are the same layer, or the first conductive portion DD and the third metal layer C06 are the same layer.

It can be understood that the gate driving signal line X11 is usually located in the second metal layer C05, so the first conductive portion DD needs to be arranged on the same layer as the first metal layer C03, or the same layer as the capacitor metal layer C04, or the third metal layer C06. The same layer, that is, the first conductive portion DD cannot be disposed on the second metal layer C05. 13 to 15 schematically show the structure diagrams of each film in the display panel 100, including the base substrate C01, the first metal layer C03 located on one side of the base substrate C01, and the first metal layer C03 located away from the first metal layer C03. The capacitor metal layer C04 on the side of the base substrate C01, the second metal layer C05 on the side of the capacitor metal layer C04 away from the base substrate C01, and the third metal layer C06 on the side of the second metal layer C05 away from the base substrate C01 , of course, an insulating layer is also included between the first metal layer C03, the capacitive metal layer C04, the second metal layer C05, and the third metal layer C06, and the display panel also includes an active layer C02, that is, the first transistor T1 and the second Active layer C02 of transistor T2. The display panel also includes a driving transistor T and a light-emitting element EM. The driving transistor is used to drive the light-emitting element EM to emit light. Of course, the light-emitting element EM includes an anode C07, a light-emitting layer C08 and a cathode C09. The encapsulation layer C10 in FIG. 13-FIG. 15 is used for Encapsulation to prevent water and oxygen from entering the panel. Optionally, a touch layer (not shown in the figure) can be provided on the side of the encapsulation layer C01 away from the side C01 of the base substrate. The first metal layer C03, and the first conductive part DD is electrically connected to the gate driving signal line X11 through the via hole. in the third metal layer C06.

The electrostatic protection circuit 400 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 and the source of the first transistor T1 are both electrically connected to the high-potential signal line VGH, and the drain of the first transistor T1 is connected to both. The gate drive signal line X11 is electrically connected, the gate of the second transistor T2 and the drain of the second transistor T2 are both electrically connected to the gate drive signal line X11, and the source of the second transistor T2 is electrically connected to the low potential signal line VGL , the optional first transistor T1 and the second transistor T2 are P-type transistors, and the drain of the first transistor T1 and the drain of the second transistor T2 are electrically connected to the gate driving signal line X11 through the first conductive part DD. When When the static electricity accumulated in the gate driving signal line X11 is at a low potential, the gate of the second transistor T2 is turned on at this time. If the potential on the gate driving signal line X11 is negative and lower than the low potential signal line VGL, the current will be The gate driving signal line X11 flows to the low potential signal line VGL, so that the potential of the gate driving signal line X11 is pulled up to a potential equal to that of the low potential signal line VGLVGL, thereby eliminating static charges. When the potential of the gate driving signal line X11 is high and the potential is higher than the potential of the high potential signal line VGH, and the gate-source voltage difference of the first transistor T1 is positive, the first transistor T1 is turned on, and the current is driven from the gate The signal line X11 flows to the high-potential signal line VGH, so that the potential of the gate driving signal line X11 is pulled down to a potential equal to the high-potential signal line VGH, thereby eliminating static charges.

In some optional embodiments, continue referring to FIG. 11 to FIG. 15, and referring to FIG. 16, FIG. 16 is a partial enlarged view of the first sub-non-display area and the second sub-non-display area in FIG. 9, the gate driving signal The line X11 includes a trigger signal line of the gate driving circuit 90 , a clock signal line, and a test signal line for testing the output signal of the gate driving circuit 90 .

It can be understood that the gate drive signal line X11 includes two gate drive circuit trigger signal lines (STV1 and STV2), four clock signal lines (CK1, CK2, XCK1, XCK2), and two gate drive lines for testing For the test signal lines (SOUT1, SOUT2) of the output signal of the circuit, 8 electrostatic protection circuits need to be set in one-to-one correspondence with the gate driving signal line X11 to realize electrostatic protection for the gate driving signal line X11.

In some optional embodiments, referring to FIG. 8, along the column direction Y, the length of the first electrostatic protection circuit 401 is L1, 200 μm≤L1≤250 μm, and the length of the second electrostatic protection circuit 402 is L2, 100≤ L2<200μm.

As described above, the space of the first sub-non-display area BB11 in the column direction Y is greater than the distance of the second sub-non-display area BB12 in the column direction Y. The length of the electrostatic protection circuit 401 in the column direction Y is greater than the length of the second electrostatic protection circuit 402 in the second sub-non-display area BB12 in the column direction Y, and along the column direction Y, the length of the first electrostatic protection circuit 401 is L1 , 200μm≤L1≤250μm, the length of the second electrostatic protection circuit 402 is L2, 100≤L2<200μm, which can meet the space requirements of the first sub-non-display area BB11 and the second sub-non-display area BB12 in the column direction Y.

In some optional embodiments, continue referring to FIG. 3 and FIG. 17 , FIG. 17 is a schematic plan view of another display panel provided by the present invention, and the shape of the display area AA includes a circle or a rounded rectangle.

The display area of the display panel in FIG. 3 is circular, the display area of the display panel in FIG. 17 is a rectangle with rounded corners, and a step will be formed at the position of the rounded corner R. For the setting method of the electrostatic protection circuit, please refer to the embodiment in FIG. 3 , which will not be repeated here. As long as the number of pixels in two adjacent pixel rows is unequal or the number of pixels in two adjacent pixel columns is unequal to form a step, the electrostatic protection area can be arranged in the first non-display area adjacent to the step. .

This embodiment also provides a display device including the above-mentioned display panel. Please refer to FIG. 18 , which is a schematic plan view of a display device provided by the present invention. The display device 1000 provided in FIG. 18 includes a display panel 100 , wherein the display panel 100 is the display panel 100 provided by any of the foregoing embodiments of the present invention. The embodiment of FIG. 18 only takes a smart wearable device as an example to describe the display device 1000. It can be understood that the display device 1000 provided by the embodiment of the present invention may be a computer, a TV, a vehicle-mounted display panel, and other displays with display functions. The device 1000 is not specifically limited in the present invention. The display device 1000 provided by the embodiment of the present invention has the beneficial effects of the display panel provided by the embodiment of the present invention. For details, reference may be made to the specific description of the display panel in the above-mentioned embodiments, which will not be repeated in this embodiment.

It can be seen from the above embodiments that the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

A display panel of the present invention includes: a display area and a non-display area at least partially surrounding the display area; the display area includes a plurality of pixel rows and a plurality of pixel columns, and the periphery of the display area includes a plurality of Steps, the number of pixels in two adjacent pixel rows is not equal or the number of pixels in two adjacent pixel columns is not equal to form the ladder, the non-display area includes a first non-display area, the The first non-display area is adjacent to the step; the first non-display area includes an electrostatic protection area, the electrostatic protection area includes a plurality of electrostatic protection circuits, and some of the electrostatic protection circuits include a multiplexer between them . The lower border area of the display panel has a stepped area and a fan-out routing area. The fan-out routing area is located between the stepped area and the display area. A multiplexer and an electrostatic protection circuit need to be set in the stepped area. The circuit occupies the space in the horizontal direction, so the multiplexer cannot be in one-to-one correspondence with the pixel columns in the display area, and must be electrically connected to the data line or touch line in the display area by winding. It will occupy vertical space, that is, the lower frame cannot be compressed in the vertical direction, which prevents the lower frame from realizing a narrow frame. In the present invention, the electrostatic protection circuit originally arranged in the step area is arranged in the first non-display area corresponding to the step. The step is formed due to the unequal number of pixels in adjacent pixel rows or adjacent pixel columns. Only the multiplexer can be set in the area, which makes full use of the space at the corresponding step position in the lower frame. Of course, the multiplexer can correspond to as many pixel columns as possible to reduce the number of windings, thereby reducing the The width of the fan-out routing area in the longitudinal direction can further compress the lower frame to realize a narrow frame.

Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are provided for illustration only and not for the purpose of limiting the scope of the present invention. Those skilled in the art will appreciate that modifications may be made to the above embodiments without departing from the scope and spirit of the present invention. The scope of the invention is defined by the appended claims.

Claims (13)

1. A display panel, comprising: comprising a display area and a non-display area at least partially surrounding the display area;

the display area comprises a plurality of pixel rows and a plurality of pixel columns, the periphery of the display area comprises a plurality of steps, the steps are formed by unequal numbers of pixels in two adjacent pixel rows or unequal numbers of pixels in two adjacent pixel columns, the non-display area comprises a first non-display area, and the first non-display area is adjacent to the steps;

the first non-display area comprises an electrostatic protection area, the electrostatic protection area comprises a plurality of electrostatic protection circuits, and a multiplexer is arranged between part of the electrostatic protection circuits.

2. The display panel according to claim 1, wherein the electrostatic protection circuits are arranged in a row direction and extend in a column direction.

3. The display panel according to claim 2, wherein the multiplexers are arranged in a row direction extending in a column direction.

4. The display panel according to claim 1, wherein the electrostatic protection circuits are alternately arranged with the multiplexers in the row direction.

5. The display panel according to claim 3, wherein the stairs comprise a first stair and a second stair which are adjacent, the number of pixels in the pixel rows of the first stair is m, the number of pixels in the pixel rows of the second stair is n, m and n are positive integers, and m is greater than n;

the first non-display area comprises a first sub non-display area and a second sub non-display area, the first sub non-display area is adjacent to the first ladder, and the second sub non-display area is adjacent to the second ladder;

the electrostatic protection region of the first sub non-display region includes a first electrostatic protection circuit; the electrostatic protection region of the second sub non-display region includes a second electrostatic protection circuit;

in the row direction, the width of the first electrostatic protection circuit is smaller than that of the second electrostatic protection circuit;

the length of the first electrostatic protection circuit is greater than that of the second electrostatic protection circuit along the column direction.

6. The display panel according to claim 5, wherein the electrostatic protection region of the first sub non-display region further comprises a first multiplexer, and the electrostatic protection region of the second sub non-display region further comprises a second multiplexer;

a width of the first multiplexer is equal to a width of the second multiplexer along the row direction; the length of the first multiplexer is equal to the length of the second multiplexer along the column direction.

7. The display panel according to claim 6, wherein the non-display region includes an upper bezel and a lower bezel which are disposed opposite to each other in the column direction;

the display panel comprises K pixel rows, the lower frame comprises a step area, a fan-out wiring area and the first non-display area, the fan-out wiring area is located between the step area and the Kth pixel row along the column direction, and the second step is located on one side, close to the fan-out wiring area, of the first step along the row direction;

the step region includes a third multiplexer having a width greater than a width of the second multiplexer along the row direction; a length of the third multiplexer is less than a length of the second multiplexer along the column direction.

8. The display panel according to claim 1, wherein the non-display region further comprises a gate driving circuit;

the non-display area further comprises a grid driving signal line surrounding the display area, and the grid driving signal line is electrically connected with the grid driving circuit and the electrostatic protection circuit respectively.

9. The display panel according to claim 8, further comprising a substrate base, a first metal layer on a side of the substrate base, a capacitor metal layer on a side of the first metal layer away from the substrate base, a second metal layer on a side of the capacitor metal layer away from the substrate base, a third metal layer on a side of the second metal layer away from the substrate base, the gate driving signal line and the second metal layer are on the same layer, the electrostatic protection circuit comprises a first transistor and a second transistor which are connected in parallel, a drain of the first transistor and a drain of the second transistor are electrically connected to the gate driving signal line through a first conductive portion, the first conductive part and the first metal layer are on the same layer, or the first conductive part and the capacitor metal layer are on the same layer, or the first conductive part and the third metal layer are on the same layer.

10. The display panel according to claim 8, wherein the gate drive signal line comprises a trigger signal line, a clock signal line, and a test signal line for testing an output signal of the gate drive circuit.

11. The display panel according to claim 5, wherein the first electrostatic discharge protection circuit has a length L1, 200 μm L1 μm 250 μm, and the second electrostatic discharge protection circuit has a length L2, 100L 2 < 200 μm in the column direction.

12. The display panel of claim 1, wherein the shape of the display area comprises a circle or a rounded rectangle.

13. A display device comprising the display panel according to any one of claims 1 to 12.

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