CN114925000A - Address conversion method, electronic device, and electronic equipment - Google Patents

Abstract

An address translation method, an electronic device and an electronic apparatus. The address translation method comprises the following steps: acquiring a target address to be converted; generating a read page table request using the target address and issuing the read page table request over the first interconnect; enabling the page table query unit to receive a page table reading request sent by a first interconnection, and querying at least one page table step by step from the storage device according to the page table reading request to obtain a first address corresponding to the target address; and enabling the page table query unit to return the queried first address through the first interconnection. According to the address translation method, the page table query unit reads the page table from the storage device without the bus or on-chip interconnection, or reads the page table from the storage device by fewer buses or on-chip interconnections, so that the time delay of reading the page table from the storage device by the buses or on-chip interconnections is reduced, and the efficiency of address translation is improved.

Description

Address conversion method, electronic device, and electronic equipment

technical field

Embodiments of the present disclosure relate to an address translation method, an electronic device, and an electronic device.

Background technique

In the field of computer technology, programmers can use any virtual address (Virtual Address, VA) within the specified range of the system to write programs instead of physical addresses. The address used by the Central Processing Unit (CPU) to execute the application program is virtual address. Usually different processes running in the system are given different virtual address spaces, and the virtual address space of each process covers a large range. For example, when allocating memory to a process and accessing memory, a virtual address needs to be mapped to a physical address (Physical Address, PA), and the physical address is the real physical memory access address. It has become a mainstream trend in the industry to distinguish between virtual addresses and physical addresses.

SUMMARY OF THE INVENTION

At least one embodiment of the present disclosure provides an address translation method, including: obtaining a target address to be translated; generating a page table read request using the target address, and issuing the page table read request via a first interconnect; The table query unit receives the read page table request sent through the first interconnection, and according to the read page table request, queries at least one level of page tables from the storage device step by step to obtain a page table corresponding to the target address the first address; enabling the page table query unit to return the first address obtained by the query through the first interconnection.

For example, in the address translation method provided by at least one embodiment of the present disclosure, generating the page table read request using the target address is that all the addresses corresponding to the target address are not cached in the storage management unit that performs address translation. performed in the case of the first address mentioned above.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the first interconnection includes a first interconnection unit, and the read page table request is issued through the first interconnection unit, and received through the first interconnection unit. The read page table request issued by the interconnect unit.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the first interconnection unit includes a bus or an on-chip interconnection.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the first interconnection further includes a second interconnection unit and a third interconnection unit, and the first interconnection unit communicates with the first interconnection unit via the second interconnection unit. The three interconnection units communicate; the request for reading the page table is sent through the first interconnection unit, the second interconnection unit and the third interconnection unit in sequence.

For example, in the address translation method provided in at least one embodiment of the present disclosure, the request for reading the page table sent through the third interconnection unit, the second interconnection unit, and the first interconnection unit in sequence is received.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the second interconnection unit includes an inter-die connection, and the third interconnection unit includes a bus or an on-chip interconnection.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the step-by-step query at least one-level page table to obtain the first address corresponding to the target address, and the generation of the target address by using the target address. The above read page table request is executed in different wafers respectively.

For example, in the address translation method provided by at least one embodiment of the present disclosure, the target address is a virtual address, and the first address is a physical address; or, the target address is a virtual address, and the first address is an intermediate address physical address; or, the target address is an intermediate physical address, and the first address is a physical address.

At least one embodiment of the present disclosure further provides an electronic device, including: a first interconnection; a storage management unit coupled to the first interconnection and configured to: obtain a target address, and use the target address to generate a read page table requesting, and issuing the read page table request via the first interconnect; a page table query unit, coupled to the first interconnect, and configured to: receive the read page issued via the first interconnect According to the read page table request, at least one level of page table is queried from the storage device by level to obtain a first address corresponding to the target address, and the first address obtained by the query is processed by the The first interconnect returns to the storage management unit.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the storage management unit is a system storage management unit.

For example, in the electronic device provided by at least one embodiment of the present disclosure, the page table query unit corresponds to a plurality of different storage management units.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the storage management unit and the page table lookup unit are respectively located in different wafers, and the first interconnection includes an inter-die connection.

At least one embodiment of the present disclosure further provides an electronic device, the electronic device includes the electronic device provided in any embodiment of the present disclosure, the electronic device further includes the storage device, wherein the storage device is configured to store multiple levels of page table.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the page table query unit is further configured to directly access the storage device or be coupled to the storage device through another interconnection, wherein the other interconnection Different from the first interconnect.

For example, in the electronic device provided by at least one embodiment of the present disclosure, in the case that the page table query unit directly accesses the storage device, the storage device includes a storage controller, and the storage controller includes the page table A query unit, or the storage device includes a cache, and the cache includes the page table query unit.

For example, in the electronic device provided in at least one embodiment of the present disclosure, the storage device is a double-rate synchronous dynamic random access memory.

Description of drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

Fig. 1 is a working principle diagram of a system storage management unit;

2 is a schematic flowchart of an address translation method provided by at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of an example of steps S10 to S30 in FIG. 2;

FIG. 4 is a schematic diagram of an example of step S40 in FIG. 2;

FIG. 5 is a schematic diagram of an example of steps S10 to S40 in FIG. 2;

FIG. 6 is a schematic diagram of another example of steps S10 to S40 in FIG. 2;

FIG. 7 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure;

8 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure;

FIG. 9 is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

FIG. 10 is a schematic block diagram of yet another electronic device provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of well-known functions and well-known components may be omitted. When any element of an embodiment of the present disclosure appears in more than one drawing, the element is represented by the same or a similar reference number in each drawing.

A memory management unit (Memory Management Unit, MMU) is located between an execution unit (such as a CPU or a processor core of a CPU) and a memory in a computer system, and provides translation from virtual addresses to physical addresses. The process of going from a virtual address to a physical address is called address translation (or mapping). For example, the data/instruction addresses behind the execution of the user program are all virtual addresses. The virtual addresses are issued by the execution unit, intercepted by the MMU and converted into physical addresses. The MMU can also have other functions such as memory attribute translation, permission checking, etc.

The System Memory Management Unit (SMMU) is widely used in various systems on a chip (SoC), between I/O peripherals and, for example, a bus. As a memory management unit, it is also mainly For translation from virtual addresses to physical addresses for peripherals, that is, to convert virtual addresses to corresponding physical addresses.

The translation rules (mapping rules) of virtual addresses to physical addresses are stored in the page table, which is stored in the storage device of the system. An MMU (eg, SMMU) includes a Page Walker Unit (PWU) and a Translation Lookaside Buffer (TLB). In order to realize a virtual address-to-physical address conversion, MMU first goes to the TLB to check whether the corresponding physical address has been cached. If there is a (hit) in the TLB, the conversion is completed directly. Then the MMU needs to use the virtual address through the PWU to go to the system storage device (for example, double-rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR)) one or more times to query the page table for conversion, and finally get the same as the virtual address. The physical address corresponding to the address, so that the access operation to the physical address can be realized.

FIG. 1 is a working principle diagram of a system storage management unit. As shown in Figure 1, a pre-designed circuit functional module applied to an application specific integrated circuit (ASIC) or programmable logic device (FPGA) is called an intellectual property core (Intellectual Property Core, IP core), or also called IP . IP can be any logic module or functional module used in ASIC or FPGA, such as filter, memory controller, interface program, etc. In this disclosure, an IP core is used to refer to a circuit functional module. The specific functions and structures of the functional modules are not limited.

For example, as shown in Figure 1, taking SMMU as an example, when IP wants to perform read and write access, it first sends out the virtual address VA to be accessed; after SMMU receives the virtual address VA, it needs to convert from virtual address to physical address. In order to perform this conversion, the SMMU needs to use the high-order field (usually called the index part) corresponding to the page table in the virtual address VA to read the page table into the DDR; The content, combined with the lower field of the virtual address VA corresponding to the offset address (usually referred to as the offset part), converts the virtual address VA into a physical address PA and outputs it, and then continues the physical address for subsequent access operations.

The act of reading the page table from the SMMU to the DDR is referred to as PTW (Page Table Walking). In order to implement a conversion from a virtual address VA to a physical address PA, when the operating system uses a multi-level page table, the SMMU needs to perform multiple PTW operations. For example, FIG. 1 takes as an example a common address bit width of 48 bits (bit), a page granularity of 4KB, and a total of 4 levels of page tables (level 0 page table to level 3 page table). In this example, the upper 36 bits of the virtual address are the index part, and the lower 12 bits are the offset part. The index part includes four 9-bit fields, and the order from high order to low order corresponds to the 0th level to the 3rd level page table respectively. After SMMU receives the virtual address VA sent by IP, it obtains the index part of the virtual address VA. Based on the fields of the page table corresponding to level 0 to level 3, SMMU needs to perform PTW 4 times in turn (for example, named PTW0 , PTW1, PTW2 and PTW3). For example, the SMMU does PTW to send the read page table request and the corresponding address field to the on-chip network (Network-on-chip, NoC, as an example of on-chip interconnection), and the NoC sends the read page table request to the DDR, and then in the In the DDR, the corresponding page table (one of the 0th level to the 3rd level page table) is accessed according to the read page table request, and the page table content read from the page table is retrieved from the DDR.

For example, as shown in Figure 1, PTW0 uses the corresponding level 0 field to access the level 0 page table according to the starting physical address of the multi-level page table recorded by the page table base address register, for example, and retrieves it from the level 0 page table. The content of the page table is the storage address Addr0 of the level 1 page table to be accessed by PTW1 in the DDR; PTW1 uses the corresponding level 1 field to access the level 1 page table, and the content of the page table retrieved from the level 1 page table is The storage address Addr1 of the second-level page table to be accessed by PTW2 in DDR; PTW2 uses the corresponding second-level field to access the second-level page table, and the content of the page table retrieved from the second-level page table is that PTW3 needs to be in the DDR The storage address Addr2 of the accessed third-level page table; PTW3 uses the corresponding third-level field to access the third-level page table, and the content of the page table retrieved from the third-level page table is the storage address of the target page (for example, the physical address ), the storage address of the target page plus the offset part in the virtual address VA can obtain the physical address PA corresponding to the virtual address VA.

Therefore, in order to perform address translation to obtain the physical address PA from the virtual address VA, it is necessary to first perform and complete PTW0, PTW1, PTW2 and PTW3 according to the index part in the virtual address VA. Every time the SMMU does a PTW, it has to go through the NoC and access the DDR, so it needs to experience the delay on the NoC and the delay in accessing the DDR. For example, the delay on NoC is represented by "noc_delay", and the delay of accessing DDR is represented by "ddr_delay". For the scheme shown in Figure 1, SMMU needs 4 PTWs to complete a conversion from virtual address VA to physical address PA, and the total required delay Delay0 can be calculated at least as follows:

Delay0=4*noc_delay+4*ddr_delay Formula (1)

Because in a computer system, most of the communication process between each functional circuit module must go through the bus or on-chip interconnection (such as NoC), the bus or on-chip interconnection is very busy, and there is a lot of resource competition, so every time SMMU does a PTWs create large delays on the bus or on-chip interconnects. From this, it can be seen that each time the SMMU goes to the storage device to read the page table, it takes a lot of time, resulting in a long time for the conversion of virtual addresses to physical addresses, thus reducing the efficiency and performance of the SoC.

At least one embodiment of the present disclosure provides an address translation method, the address translation method includes: obtaining a target address to be translated; using the target address to generate a page table read request, and issuing a read page table request through a first interconnection; The table query unit receives the read page table request sent through the first interconnection, and according to the read page table request, queries at least one level of page tables from the storage device step by step to obtain the first address corresponding to the target address; make the page table The query unit returns the first address obtained by the query through the first interconnection.

At least one embodiment of the present disclosure further provides an electronic device corresponding to executing the above address translation method.

At least one embodiment of the present disclosure further provides an electronic device corresponding to the above electronic device.

In the address translation method, electronic device, and electronic device provided by at least one embodiment of the present disclosure, in the process of address translation, the page table query unit is made to read the page table from the storage device without going through a bus or on-chip interconnection, or through less The bus or on-chip interconnection reads the page table from the storage device, thereby reducing the delay of reading the page table from the storage device by the bus or on-chip interconnection, improving the efficiency of address translation, and improving the efficiency and performance of, for example, SoC.

Hereinafter, at least one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used in different drawings to refer to the same elements that have been described.

FIG. 2 is a schematic flowchart of an address translation method provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 2, at least one embodiment of the present disclosure provides an address translation method for performing address translation in a computer system, for example, converting a virtual address into a physical address, so that the converted physical address can be used The target address is accessed, and the target address may point to, for example, a storage address in a storage device, or may point to a certain functional circuit module in the computer system, such as a direct memory access (DMA) unit, a PCIE device, and the like. For example, the computer system includes at least one memory management unit (MMU) (eg, SMMU) and a page table access unit (PWU) provided independently of the MMU, eg, the page table access unit is coupled and communicated with the memory management unit through an interconnect, without It is a part of the MMU or is no longer directly coupled and communicated with the MMU, so the page table access unit is not set inside the storage management unit. The above-mentioned address translation method can be performed by a memory management unit and a page table access unit. As shown in FIG. 2, the address conversion method includes the following steps S10-S40.

Step S10: obtaining the target address to be converted;

Step S20: use the target address to generate a request for reading the page table, and issue a request for reading the page table through the first interconnection;

Step S30: Make the page table query unit receive the read page table request sent through the first interconnection, and according to the read page table request, query at least one level of page tables from the storage device step by step to obtain the first page table corresponding to the target address. address;

Step S40: The page table query unit returns the first address obtained by the query through the first interconnection.

For example, the storage management unit is used in the system as a whole to perform the conversion from the target address to the first address in the above steps S10-S40, and in this process, the conversion operation is further performed by means of the PWU. For example, the storage management unit may be an SMMU, for example, the storage management unit may further include a TLB; in other embodiments, the storage management unit may also be other electronic components capable of implementing an address translation function, which is not limited in the embodiments of the present disclosure .

For example, the target address is a virtual address that needs to be converted, and the first address is a physical address; or, the target address is a virtual address that needs to be converted, and the first address is an intermediate physical address (Intermediate PhysicalAddress, IPA); Or, the target address is The intermediate physical address to be converted, the first address is the physical address.

For example, the intermediate physical address PA is a concept introduced after computer virtualization. For a computer system supporting virtualization, each virtual machine system (guest OS) cannot directly map the virtual address VA to the physical address PA of the entire system, but maps to a limited physical address space. Therefore, in a computer system that supports virtualization, the virtual machine system (guest OS) is responsible for mapping the virtual address VA to the intermediate physical address PA, and the virtual machine monitor (Hypervisor) is responsible for mapping the intermediate physical address PA to a specific physical address. From the virtual address VA to the intermediate physical address PA and from the intermediate physical address PA to the physical address PA, address translation operations are involved, respectively, and can be performed by the address translation method of at least one embodiment of the present disclosure.

For example, using the target address to generate the request to read the page table is performed under the condition that the first address corresponding to the target address is not cached in the TLB of the memory management unit that performs address translation. For example, when the storage management unit performs the conversion from the target address to the first address, if the first address corresponding to the target address is cached in the TLB of the storage management unit, the storage management unit does not generate a request to read the page table, but directly The conversion of the target address to the first address is completed inside the TLB of the storage management unit; if the first address corresponding to the target address is not cached in the TLB of the storage management unit, the storage management unit generates a request to read the page table, and executes, for example, Address conversion in steps S10 to S40.

For example, in at least one embodiment, a computer system may include a plurality of storage management units and at least one page table query unit independent of these storage management units, for example, each page table query unit may be used for a corresponding storage management unit , which can also be used for corresponding multiple different storage management units, that is, multiple storage management units can share, for example, one page table query unit.

For example, in at least one embodiment, the storage management unit and the page table lookup unit may be located in the same die, and the two are coupled and communicate with each other through an on-chip interconnect; in at least one embodiment, the storage management unit and the page table The table lookup units may also be located in different dies, respectively, and the first interconnect for coupling and communication of the storage management unit and the page table lookup unit includes die-to-die (D2D).

FIG. 3 is a schematic diagram of an example of steps S10 to S30 in FIG. 2 ; FIG. 4 is a schematic diagram of an example of step S40 in FIG. 2 .

For example, as shown in FIG. 3, in step S10, the storage management unit 110 acquires the IP or the access request for the target address 101 issued by the processor (IP/CPU) 300, thereby generating an address translation request for the target address. In step S20 , the storage management unit 110 uses the target address 101 to generate a read page table request 102 . Taking the system using n-level page tables as an example, that is, taking the storage management unit 110 needing to read the page table n times from the storage device 200 as an example, the page table read request 102 includes PTW0, PTW1, . . . , PTWn-1 ; The storage management unit 110 sends a page table read request 102 to the remote page table query unit 130 via the first interconnection 120 . In step S30 , the page table query unit 130 receives the read page table request 102 from the storage management unit 110 via the first interconnection 120 , and queries at least one level of pages from the storage device 200 by level according to the read page table request 102 . A table (ie, n is greater than or equal to 1, for example, n is equal to 3 or 4) to obtain the first address corresponding to the target address 101 . For example, in the case that the target address is a virtual address, the first address may be a physical address or an intermediate physical address.

For example, as shown in FIG. 3 , the process of querying at least one level of page tables from the storage device 200 by the page table query unit 130 to obtain the first address corresponding to the target address 101 is as follows: PTW0 records according to, for example, the page table base address register The starting physical address of the multi-level page table, use the corresponding level 0 field to access the level 0 page table, and the content of the page table retrieved from the level 0 page table is the level 1 page table to be accessed by PTW1 in the DDR The storage address Addr0; PTW1 uses the corresponding first-level field to access the first-level page table, and the content of the page table retrieved from the first-level page table is the storage address Addr1 of the second-level page table to be accessed by PTW2 in the DDR; PTW2 uses the corresponding level 2 field to access the level 2 page table, and the content of the page table retrieved from the level 2 page table is the storage address Addr2 of the level 3 page table to be accessed by PTW3 in the DDR;...;PTWn- 1 Use the corresponding n-1 level field to access the n-1 level page table, the page table content retrieved from the n-1 level page table is the storage address of the target page table, the storage address of the target page table plus The offset part in the virtual address VA can obtain the first address corresponding to the target address.

For example, as shown in FIG. 4, in step S40, the page table query unit 130 will query the result of the multi-level page table 103 (Addr0/Addr1/.../Addr n-2/first address) (here, the first address). an address), which is returned to the storage management unit 110 once through the first interconnection 120; the storage management unit 110 outputs the obtained first address 1031 for subsequent operations (such as accessing a storage device or peripheral device), thus completing the The translation of the target address 101 to the first address 1031 in FIG. 3 .

For example, the target address 101 is the virtual address VA, and the first address 1031 is the physical address PA; or, the target address 101 is the virtual address VA, and the first address 1031 is the intermediate physical address IPA; or, the target address 101 is the intermediate physical address IPA, The first address 1031 is the physical address PA.

For example, the memory management unit 110 uses the target address 101 to generate the read page table request 102 (PTW0, PTW1, . It is performed when the address 101 corresponds to the first address 1031. For example, when the storage management unit 110 performs the conversion from the target address 101 to the first address 1031, if the first address 1031 corresponding to the target address 101 is already cached in the storage management unit 110 (eg TLB), the storage management unit 110 does not Generate the read page table request 102, but directly complete the conversion from the target address 101 to the first address 1031 inside the storage management unit 110; if the storage management unit 110 does not cache the first address 1031 corresponding to the target address 101, then The storage management unit 110 generates the read page table request 102, and performs, for example, the address translation in steps S10-S40.

For example, as shown in FIG. 3 and FIG. 4 , in the address translation method provided by at least one embodiment of the present disclosure, the storage management unit 110 only needs to issue a page table read request 102 once, and the page table query unit 130 The device 200 obtains the multi-level page table 103 by querying, thereby obtaining the first address 1031 . For example, the delay on the first interconnect 120 is represented by "noc_delay", and the delay in accessing the storage device 200 is represented by "ddr_delay". The storage management unit 110 needs n times of PTW to complete one conversion from the target address 101 to the first address 1031, and the required total delay Delay1 can be expressed as:

Delay1=1*noc_delay+n*ddr_delay Formula (2)

Comparing formula (2) with formula (1), taking n=4 as an example, compared to the solution in FIG. 1, Delay1 reduces the delay of the first interconnection 120 reading the page table from the storage device 200 by three times compared to Delay0. time(3*noc_delay).

It can be seen from this that the page table query unit 130 can directly read the page table from the storage device 200 to obtain the first address 1031 without going through the first interconnection 120 , thereby reducing the time required for the first interconnection 120 to read the page table from the storage device 200 . The delay improves the conversion efficiency from the target address 101 to the first address 1031, and improves the efficiency and performance of the SoC, for example.

In another example of the above-mentioned embodiment, the storage management unit itself may include, for example, a level 0 page table, and the storage management unit itself also has (at least part of) a page table query function, then the storage management unit can perform an initial read based on the target address for To request a page table, you can directly execute PTW0 locally (that is, in the storage management unit), and then use the storage address Addr0 of the first-level page table obtained by querying the level-0 page table, and the target address (or the target address except the corresponding obtain a further read page table request, and send the further read page table request to the page table query unit independent of the storage management unit for subsequent pages The table lookup operation obtains the first address corresponding to the target address, and the first address is returned to the storage management unit. This example can also reduce the delay caused by the operation through the first interconnection in the process of querying the page table, thereby improving, for example, the efficiency and performance of the SoC.

FIG. 5 is a schematic diagram of an example of steps S10 to S40 in FIG. 2 ; FIG. 6 is a schematic diagram of another example of steps S10 to S40 in FIG. 2 .

For example, the operation of "using the target address to generate a request to read the page table" in step S20 and the operation of "inquiring at least one level of page tables step by step to obtain the first address corresponding to the target address" in step S30 can be Executed in one die, or separately in different dies. For example, FIG. 5 shows the case where the above two operations are performed in one die, at this time the storage management unit 110 and the page table lookup unit 130 are located in the same die, and the two are connected to each other through the first interconnection Coupling and communication; for example, FIG. 6 shows the situation where the above two operations are performed in different dies, and the storage management unit 110 and the page table query unit 130 are located in different dies. , the two are coupled and communicated with each other through the first interconnection and other interconnections.

For example, as shown in FIG. 5 , the first interconnection 120 includes a first interconnection unit 121 . The storage management unit 110 sends the page table read request 102 via the first interconnection unit 121 , and the page table query unit 130 receives the page table read request 102 sent through the first interconnection unit 121 .

For example, as shown in FIG. 5 , in step S10 , the storage management unit 110 acquires the target address 101 issued by the IP/CPU 300 . In step S20, the storage management unit 110 uses the target address 101 to generate a read page table request 102 (PTW0, PTW1, . . In step S30, the page table query unit 130 receives the read page table request 102 sent by the first interconnection unit 121, and queries at least one level of page tables from the storage device 200 according to the read page table request 102 to obtain the The first address corresponding to the target address 101. In step S40, the page table query unit 130 returns the multi-level page table 103 (Addr0/Addr1/.../Addrn-2/first address) obtained by the query to the storage management unit 110 at one time through the first interconnection unit 121; The storage management unit 110 outputs the obtained first address 1031, thereby completing the conversion of the target address 101 to the first address 1031.

For example, the first interconnection unit 121 may be a bus or an on-chip interconnection, or may also be other electronic components capable of implementing an address transmission function. For example, the on-chip interconnection may be a network-on-chip (NoC), and the on-chip network may be a switch (Switch). A network, a ring (ring) network, a tree (Tree) network, a mesh (Mesh) network, a torus (Torus) network, etc., are not limited in the embodiments of the present disclosure.

For example, as shown in FIG. 6 , the first interconnection 120 further includes a second interconnection unit 122 and a third interconnection unit 123 . The first interconnection unit 121 communicates with the third interconnection unit 123 via the second interconnection unit 122 . For example, the storage management unit 110 sends out the page table read request 102 through the first interconnection unit 121, the second interconnection unit 122, and the third interconnection unit 123 in sequence, and the page table query unit 130 receives the request through the third interconnection unit 123, the second interconnection unit 123, and the second interconnection unit 123. The read page table request 102 issued by the unit 122 and the first interconnection unit 121 .

For example, as shown in FIG. 6 , in step S10 , the storage management unit 110 acquires the target address 101 issued by the IP/CPU 300 . In step S20, the storage management unit 110 uses the target address 101 to generate a page table read request 102 (PTW0, PTW1, . The read page table request 102 is issued with the third interconnection unit 123 . In step S30 , the page table query unit 130 receives the page table read request 102 sent by the third interconnection unit 123 , the second interconnection unit 122 and the first interconnection unit 121 in sequence, and reads the page table request 102 from the storage device according to the read page table request 102 . In 200, at least one level of page table is queried step by step to obtain the first address corresponding to the target address 101. In step S40, the page table query unit 130 sequentially connects the multi-level page table 103 (Addr0/Addr1/.../Addrn-2/first address) obtained by the query through the third interconnection unit 123, the second interconnection unit 122 and the first address. An interconnection unit 121 returns to the storage management unit 110 at one time; the storage management unit 110 outputs the obtained first address 1031, thereby completing the conversion from the target address 101 to the first address 1031.

For example, the third interconnection unit 123 and the first interconnection unit 121 may be a bus or an on-chip interconnection, or may be other electronic components capable of implementing an address transmission function. For example, the on-chip interconnection may be a network on chip (NoC), which It can be a cross (Switch) network, a ring (ring) network, a tree (Tree) network, a mesh (Mesh) network, a torus (Torus) network, etc., which are not limited in the embodiments of the present disclosure; the second interconnection unit 122 includes inter-die connection (D2D), or may be other electronic components capable of realizing the connection function between different dies, which is not limited by the embodiment of the present disclosure.

FIG. 7 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

For example, as shown in FIG. 7 , the electronic device 100 includes a first interconnection 120 , a storage management unit 110 and a page table query unit 130 , and can execute the address translation method according to any embodiment of the present disclosure. The storage management unit 110 is coupled to the first interconnection 120 and is configured to: obtain the target address 101 ; generate a page table read request 102 using the target address 101 ; and issue a page table read request 102 via the first interconnection 120 . The page table query unit 130 is coupled to the first interconnection 120, and is configured to: receive the page table read request 102 sent by the first interconnection 120, and query at least one level from the storage device according to the read page table request 102. The page table obtains the first address 1031 corresponding to the target address 102, and returns the multi-level page table 103 obtained by the query to the storage management unit 110 via the first interconnection 120; the storage management unit 110 outputs the obtained first address 1031, thereby The conversion of the target address 101 to the first address 1031 is completed.

Likewise, in this embodiment, for example, the storage management unit 110 may be an SMMU, or may be other electronic components capable of implementing an address translation function, which are not limited in the embodiments of the present disclosure. For example, the storage management unit 110 and the page table lookup unit 130 may be located in the same die; or may be located in different dies, and the first interconnection includes inter-die connection (D2D). For example, the page table query unit 130 may be used for the same storage management unit 110 , or may be used for multiple different storage management units 110 .

FIG. 8 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.

For example, as shown in FIG. 8 , the electronic device 10 includes, for example, the electronic device 100 and the storage device 200 shown in FIG. 7 . The storage device 200 is configured to store multi-level page tables, including the multi-level page tables 103 (Addr0/Addr1/.../Addr n-2/first address) obtained by the page table query unit 130 in FIGS. 3 to 6 .

For example, as shown in FIG. 8 , the electronic device 100 obtains the target address 101 , uses the target address 101 to generate a read page table request 102 , and obtains the multi-level page table 103 from the storage device 200 through query according to the read page table request 102 to The first address 1031 corresponding to the target address 102 is obtained. The electronic device 100 outputs the obtained first address 1031 , thereby completing the conversion from the target address 101 to the first address 1031 .

For example, the storage device 200 may include DDR, or may be other storage devices capable of storing multi-level page tables, which are not limited in the embodiments of the present disclosure.

For example, in the electronic device 10 shown in FIG. 8 , the page table query unit 130 of the electronic device 100 is further configured to directly access the storage device 200 or be coupled to the storage device 200 through another interconnection (not shown in the figure), This further interconnection is different from the first interconnection 120 .

For example, for the case where the page table query unit 130 is coupled with the storage device 200 through another interconnection, the other interconnection is different from the first interconnection 120, in this case, the process of the page table query unit 130 accessing the storage device 200 does not go through The first interconnection 120 thus reduces the delay of the first interconnection 120 reading the page table from the storage device 200 , thereby improving the conversion efficiency of the target address 101 to the first address 1031 .

FIG. 9 is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 9 , in the case where the page table query unit 130 directly accesses the storage device 200, the page table query unit 130 can be integrated in the storage device 200, so it can directly access the storage device without going through another bus or on-chip interconnection 200. At this time, the process of accessing the storage device 200 by the page table query unit 130 also does not pass through the first interconnection 120, thus reducing the delay of the first interconnection 120 reading the page table from the storage device 200, thereby increasing the target address 101 to the first interconnection 120. Conversion efficiency of address 1031.

In this case, the storage device 200 may include, for example, a memory controller (MC), which includes a page table query unit 130, that is, the page table query unit 130 is integrated in the memory controller, and the memory controller is used for managing For read and write operations of the storage device, etc.; alternatively, the storage device 200 may include, for example, a cache, and the cache (cache) includes the page table query unit 130 ; or, the page table query unit 130 may also be integrated in the storage device 200 Among other components, the embodiments of the present disclosure are not limited thereto.

FIG. 10 is a schematic block diagram of yet another electronic device provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 10 , the electronic device 400 is, for example, suitable for implementing the address translation method provided by the embodiment of the present disclosure. The electronic device 400 may be a terminal device or a server or the like. It should be noted that the electronic device 400 shown in FIG. 10 is only an example, which does not impose any limitation on the function and scope of use of the embodiments of the present disclosure.

For example, as shown in FIG. 10, an electronic device 400 may include a processing device (eg, a central processing unit, a graphics processor, etc.) 41 that may be loaded into a program according to a program stored in a read only memory (ROM) 42 or from a storage device 48 A program in a random access memory (RAM) 43 executes various appropriate actions and processes. In the RAM 43, various programs and data necessary for the operation of the electronic device 400 are also stored. The processing device 41 , the ROM 42 , and the RAM 43 are connected to each other through a bus 44 . An input/output (I/O) interface 45 is also connected to bus 44 . Typically, the following devices can be connected to the I/O interface 45: input devices 46 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; including, for example, a liquid crystal display (LCD), speakers, vibration an output device 37 of a computer or the like; a storage device 48 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 49 . Communication means 49 may allow electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. Although FIG. 10 shows electronic device 400 having various means, it should be understood that not all of the illustrated means are required to be implemented or provided, and electronic device 400 may alternatively implement or implement more or less means.

For the detailed description and technical effects of the electronic device 10/400, reference may be made to the above description of the electronic device, which will not be repeated here.

For this disclosure, the following points need to be noted:

(1) In the drawings of the embodiments of the present disclosure, only the structures involved in the embodiments of the present disclosure are involved, and other structures may refer to general designs.

(2) The features of the same embodiment and different embodiments of the present disclosure may be combined with each other without conflict.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical scope of the present disclosure can easily think of changes or substitutions, which should cover within the scope of protection of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (17)

1. An address translation method, comprising:

acquiring a target address to be converted;

generating a read page table request using the target address and issuing the read page table request over a first interconnect;

enabling a page table query unit to receive the read page table request sent by the first interconnection, and querying at least one page table step by step from a storage device according to the read page table request to obtain a first address corresponding to the target address;

and enabling the page table query unit to return the queried first address through the first interconnection.

2. The method of claim 1, wherein generating the read page table request using the target address is performed in the event that the first address corresponding to the target address is not cached in a memory management unit performing address translation.

3. The method of claim 1, wherein the first interconnect comprises a first interconnect unit,

the method further includes issuing the read page table request via the first interconnect unit, and receiving the read page table request issued via the first interconnect unit.

4. The method of claim 3, wherein the first interconnect unit is a bus or an on-chip interconnect.

5. The method of claim 3, wherein the first interconnect further comprises a second interconnect unit and a third interconnect unit, the first interconnect unit communicating with the third interconnect unit via the second interconnect unit;

and sending the page table reading request sequentially through the first interconnection unit, the second interconnection unit and the third interconnection unit.

6. The method of claim 5, wherein the read page table request issued sequentially through the third interconnect unit, the second interconnect unit, and the first interconnect unit is received.

7. The method of claim 5, wherein the second interconnect unit comprises an inter-die connection and the third interconnect unit comprises a bus or an on-die interconnect.

8. The method of any of claims 5-7, wherein said generating said read page table request using said target address is performed in separate dies in association with said progressively consulting at least one page table to obtain a first address corresponding to said target address.

9. The method of claim 1, wherein the target address is a virtual address and the first address is a physical address; or,

the target address is a virtual address, and the first address is an intermediate physical address; or,

the target address is an intermediate physical address, and the first address is a physical address.

10. An electronic device, comprising:

a first interconnect;

a memory management unit coupled with the first interconnect and configured to: obtaining a target address, generating a read page table request using the target address, and issuing the read page table request over the first interconnect;

a page table walk unit coupled to the first interconnect and configured to: receiving the page table reading request sent by the first interconnection, querying at least one page table from a storage device step by step according to the page table reading request to obtain a first address corresponding to the target address, and returning the queried first address to the storage management unit through the first interconnection.

11. The electronic device of claim 10, wherein the storage management unit is a system storage management unit.

12. The electronic device of claim 10, wherein the page table walk unit corresponds to a plurality of different storage management units.

13. The electronic device of claim 11, wherein the memory management unit and the page table walk unit are each located in a different die, and the first interconnect comprises an inter-die connection.

14. An electronic device comprising the electronic apparatus of any of claims 10-13, the electronic device further comprising the memory device, wherein the memory device is configured to store a multi-level page table.

15. The electronic device of claim 14, wherein the page table walk unit is configured to access the storage directly or to be coupled with the storage through another interconnect, wherein the other interconnect is different from the first interconnect.

16. The electronic device of claim 15, wherein, for the case where the page table walk unit directly accesses the storage device, the storage device comprises a storage controller that comprises the page table walk unit, or,

the storage device includes a cache including the page table walk unit.

17. The electronic device of claim 14, wherein the storage is a double rate synchronous dynamic random access memory.

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