CN114915860A - Stacked switch unit and method for use in a stacked switch unit - Google Patents

Abstract

A stackable switch unit and a method for use in a stackable switch unit, comprising: the stackable switch unit has a plurality of signal ports, the plurality of signal ports including master/slave control ports; and, in the stackable switch unit During a boot-up procedure, it is automatically determined whether the stackable switch unit is a master switch unit or a from the switch unit.

Description

Stacked switch unit and method therefor

technical field

The present invention relates to a switch mechanism, in particular to a stackable switch unit and a method for using the stackable switch unit.

Background technique

Generally speaking, the traditional switch unit can only transmit the packets of the switch at the bottom layer of the system. In addition, if the user needs to control multiple switch units, correspondingly, multiple sets of connection interfaces are required to control the multiple switch units respectively. However, this conventional method wastes the number of ports and occupies a large circuit area at the same time.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to provide a stacked switch unit and a corresponding method to solve the problems of the prior art.

According to an embodiment of the present invention, there is disclosed a method for a stackable switch unit capable of being stacked with at least one other stackable switch unit, the method comprising: providing the stackable switch unit, the The stackable switch unit has a plurality of signal ports, and the plurality of signal ports include at least one master/slave control port; during a startup procedure of the stackable switch unit, according to at least one signal of the at least one master/slave control port The level and/or the content of at least one bit of data obtained from the at least one master/slave control port automatically determines whether the stacked switch unit is a master switch unit or a slave switch unit; and, when the stacked switch unit is a master switch unit or a slave switch unit; When the switch unit is the master switch unit, a stack configuration setting is generated, and the stack configuration setting is transmitted to all of the stack switch unit through at least one signal port of the plurality of signal ports of the stack switch unit. The connected at least one other stackable switch unit enables the stackable switch unit to complete the stack connection with the at least one other switch unit.

According to an embodiment of the present invention, there is disclosed a method for a stackable switch unit that can be stacked with at least one other stackable switch unit, and the method includes: providing the stackable switch unit , the stacked switch unit has a plurality of signal ports, and the plurality of signal ports include at least one master/slave control port; during a boot-up procedure of the stacked switch unit, according to at least one master/slave control port A signal level and/or the content of at least one bit of data obtained from the at least one master/slave control port automatically determines whether the stacked switch unit is a master switch unit or a slave switch unit; and, when the When the stackable switch unit is the slave switch unit, a signal generated from a specific master switch unit and/or another slave is received through at least one of a first signal port and a second signal port of the stackable switch unit A stack configuration setting forwarded by the switch unit, so that the stack type switch unit and the specific master switch unit or the other slave switch unit complete the stack connection, wherein the at least one other stack type switch unit includes the specific master switch unit and this other slave switch unit.

According to an embodiment of the present invention, a stackable switch unit is further disclosed, the stackable switch unit can be stacked with at least one other stackable switch unit, and the stackable switch unit includes a plurality of signal ports and a processing circuit. The plurality of signal ports include at least one master/slave control port. The processing circuit is coupled to the plurality of signal ports, and is used for: during a boot-up procedure of the stacked switch unit, according to at least one signal level of the at least one master/slave control port and/or from the at least one master / The content of at least one bit of the data obtained from the control port automatically determines whether the stacked switch unit is a master switch unit or a slave switch unit.

Description of drawings

FIG. 1 is a schematic diagram of one or more switch units according to an embodiment of the present application.

FIG. 2 is an exemplary schematic diagram of a switch device according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of a method for generating and storing stack files and programs in a flash memory according to an embodiment of the present invention.

4 is a schematic flowchart of a method for determining a switch unit as a master/slave switch unit during system startup according to an embodiment of the present invention.

FIG. 5 is a schematic flowchart of operations and communication of two stacking switch units during system startup according to an embodiment of the present invention.

【Symbol Description】

100, 100A～100C: Switching device

101, 101A～101D: Switch unit

102A～102D: Processing circuit

105: Flash

110: Control device

SA0, SA1, SB0, SB1, SC0, SC1, SD0: Signal port

S305～S320, S405～S445, S505A～S540A, S505B～S540B: Steps

Detailed ways

The present invention aims to provide a stacking/stackable switch unit, such as a network switch unit, which can completely and independently perform the operation of a network switch, and can also be configured to Working in conjunction with one or more switch units, a group of stacked switch units has the characteristics of a single switch unit/device but with a larger number of input/output ports (or pins).

The switch unit in the embodiment of the present invention has a plurality of signal ports, for example, a network switch unit with N ports (N is, for example, 16, but not limited), wherein a plurality of switch units, such as M, can be stacked to form a single switch unit, The user can directly determine the stacking topology of the M switch units according to the circuit design of one or more signal ports/pins of the M switch units or other external circuit designs. The purpose of automatic connection of all switch units, automatic determination of master/slave units, realization of stack topology and update of all switch units having or updating the same software/firmware program under the condition of data setting of switch units/devices.

Please refer to FIG. 1 , which is a schematic diagram of one or more switch units according to an embodiment of the present application. As shown in FIG. 1 , the switch apparatus 100 includes a single switch unit, while the switch apparatus 100A includes M stacked switch units (M, for example, 2), and the switch apparatus 100B includes M stacked switch units (M, for example, 4). It should be noted that the dotted boxes of the switch devices 100A and 100B indicate that when the user accesses from the outside, the stack of multiple switch units can be regarded as a single switch device (or unit), that is, the operation behavior of the user. It is similar to only a single switch unit, but its actual operation is performed by, for example, two switch units 101 in the switch device 100A (or four switch units 101 in the switch device 100B) cooperate to operate automatically to connect, determine the main/ The relationship of the slave units, implementing the stack topology, updating the software/firmware programs of all switch units, and processing network switching packets, etc.

In addition, a switch unit 101 has N signal ports (or pins), and during stacking, at least one signal port is used for stacking connection with a signal port of at least another switch unit 101, and between the signal ports The communication connection interface used is, for example, USXGMII interface, but not limited. For the overall switch device 100A, since the switch unit 101 having N signal ports uses one signal port to connect with one signal port of another switch unit 101 in a stack, the switch device 100A can have at most (2N- 2) signal ports are used as input/output; while for the overall switch device 100B, since 6 signal ports are used as stack connections (two switch units 101 connected to only one switch unit 101 use one signal port, and the other two switch units 101 connected to two switch units 101 use two signal ports), so the switch device 100B can have at most (4N-6) signal ports as input/output. In addition, it should be noted that the dotted squares shown in the switch devices 100A and 100B are used to indicate that they are formed by stacking the chip circuits of a plurality of switch units on the circuit board, but this is not a limitation of the present case. In a possible embodiment, a plurality of switch units can also be circuit-packaged after being stacked to form a chip circuit of a switch device.

Please refer to FIG. 2 , which is an exemplary schematic diagram of a switch device 100C according to an embodiment of the present invention. As shown in FIG. 2, a plurality of switch units (for example, four, but the number is not limited) 101A-101D form a stack topology to form the switch device 100C, and each switch unit 101A-101D includes a plurality of Signal ports (/or pins) and a processing circuit. For example, a switch unit 101A as the master switch unit includes processing circuitry 102A and includes a serial peripheral interface (SPI) formed using one signal port to connect to a flash memory 105 (which may be external memory), using another signal port A data transmission interface is formed to receive data from a control device 110, a buffer access interface formed by a signal port is used to receive instructions (or commands) from the control device 110, and at least one signal as a stack connection Ports SA0 and SA1 and other signal ports, wherein one of signal port SA0 and signal port SA1 (such as SA1, but not limited) is connected to another switch unit (such as 101B) through, for example, a USXGMII interface (but not limited); control The device 110 is, for example, an external electronic control unit or a single-chip device for sending commands and data to the master switch unit 101A to control the data transmission and operation behavior of the master switch unit 101A and all other slave switch units 101B-101D.

In addition, a switch unit 101B serving as a slave switch unit includes, for example, a processing circuit 102B, at least one signal port SB0 and SB1 connected as a stack, and other signal ports, wherein the signal port SB0 is connected to the signal port SA1 of the master switch unit 101A, and The signal port SA1 is connected to the signal port SC0 of the other switch unit 101C through, for example, but not limited to, a USXGMII interface. In addition, a switch unit 101C as another slave switch unit includes, for example, a processing circuit 102C, at least one signal port SC0 and SC1 connected as a stack, and other signal ports, wherein the signal port SC0 is connected to the signal port SB1 of the switch unit 101B, And the signal port SC1 is connected to the signal port SD0 of the further switch unit 101D through, for example (but not limited to) a USXGMII interface. In addition, a switch unit 101D as yet another slave switch unit includes, for example, a processing circuit 102D, at least one signal port SD0 connected as a stack, and other signal ports.

It should be noted that, in this embodiment, the switch units 101A to 101D are all switch units with the same number of signal ports (or pins). When the processing circuits 102A to 102D of a switch unit 101A to 101D enter the stack mode, they will be connected according to the signal level on one or more signal ports (or pins) and/or at least one signal port (or pin) respectively. to the data stored in a memory (eg flash memory 105) to determine whether it is a master switch unit or a slave switch unit in stack mode, if it is a master switch unit, then the master switch unit 101A shown in FIG. 2 The two signal ports are respectively connected to the control device 110 to form the data transmission interface and the register access interface, and one of the signal ports is connected to the flash memory 105 as an SPI interface; if it is used as a slave switch unit, as shown in the figure As shown in the slave switch units 101B to 101D shown in 2, these slave switch units are not connected to the control device 110 and the flash memory 105, so each of the slave switch units 101B to 101D has three more free signal ports than the master switch unit 101A. , but can additionally be used as other input/output. It should be noted that the different placement positions of the signal ports in the switch units 101A to 101D shown in FIG. 2 are only for convenience and conciseness to illustrate the structural relationship of the stack connections, and are not a limitation of the present application.

In practice, the N signal ports of each switch unit further include one or more master/slave control ports (or pins), and each switch unit can pass the signals on the one or more master/slave control ports. The signal level and/or the received data bits determine the role of the master/slave switch unit to automatically connect with one or more other switch units and automatically complete the stack topology, software/firmware program update , when the user performs a stack topology of N switch units, the user can directly set the signal power on one or more master/slave control ports of each switch unit according to an external control circuit or a simple external circuit. The level and/or the received data bits can achieve the purpose of automatically connecting all switch units and automatically completing the stack topology and software/firmware program updates during system startup.

In an embodiment of the present invention, the above-mentioned one or more master/slave control ports (or pins) include at least one strapping pin and/or are coupled to, for example, a one-time programmable (one-time programmable) pin. -time programmable (OTP) circuit at least one control pin, it should be noted that the one-time programmable is only used for example, but not the limitation of this case; the data in the flash memory 105 can be written and recorded only once data, or it can be read and written repeatedly. The at least one multiplexing pin corresponds to at least one specific operation function of a stacked switch unit, and the one-time programmable circuit is, for example, the aforementioned flash memory 105 . Examples of at least one multiplexing pin and at least one control pin of a switch unit in the embodiments of the present invention are shown in the following table, for example, including four multiplexing pins and a one-time programmable circuit OTP pin:

As shown in the above table, the four multiplexed pins P5_TXD[3], P4_TXD[0], P4_TXD[1] and P4_TXD[2] of a switch unit respectively indicate whether to use the multiplexed pins to determine whether the switch unit is in the stack master/slave role, whether to use the first signal port (represented by S0, such as the signal ports SA0, SB0, SC0, SD0, etc. in each switch unit shown in FIG. 2) for stack connection, whether to use the second signal The ports (represented by S1, such as the signal ports SA1, SB1, SC1, etc. in each switch unit shown in Figure 2) are connected to the stack and determine the master/slave role when stacking, for example, when the multiplexing pin P5_TXD When the signal level of [3] is the first level (such as logic level "0", but not limited), it means disabled, that is, the multiplexed pin is not used to determine the master/slave switch unit, and when the multiplexed connection When the signal level of pin P5_TXD[3] is the second level (eg logic level "1", but not limited), it means enable, that is, use multiplexed pins to determine the master/slave switch unit.

When the signal level of the multiplexing pin P4_TXD[0] is the first level (eg logic level "0", but not limited), it means that the first signal port S0 is disabled for stack connection, and when the multiplexing pin is When the signal level of P4_TXD[0] is the second level (for example, logic level "1", but not limited), it means that the first signal port S0 is enabled for stack connection, for example, the main switch unit 101A shown in FIG. The first signal port SA0 is not connected in a stack, therefore, the signal level of the multiplexing pin P4_TXD[0] of the master switch unit 101A will be at the first level “0” to indicate that it is disabled. For example, as shown in FIG. 2 The first signal port SB0 of the slave switch unit 101B is connected in a stack, so the signal level of the multiplexed pin P4_TXD[0] of the slave switch unit 101B will be at the second level "1" to indicate enable.

When the signal level of the multiplexing pin P4_TXD[1] is the first level (eg logic level "0", but not limited), it means that the first signal port S1 is disabled for stack connection, and when the multiplexing pin is When the signal level of P4_TXD[1] is the second level (for example, logic level "1", but not limited), it indicates that the second signal port S1 is enabled for stack connection, for example, the master switch unit 101A shown in FIG. 2 The second signal port SA1 is connected in a stack, so the signal level of the multiplexing pin P4_TXD[1] of the master switch unit 101A will be at the second level “1” to indicate enabling, and for example, as shown in FIG. 2, the slave The second signal port SD1 of the switch unit 101D is not connected in a stack, so the signal level of the multiplexed pin P4_TXD[1] of the slave switch unit 101D will be at the first level “0” to indicate disable.

When the signal level of the multiplexing pin P4_TXD[2] is the first level (eg logic level "0", but not limited), it means that the switch unit is a master switch unit, and when the multiplexing pin P4_TXD[2] 2] When the signal level is the second level (such as logic level "1", but not limited), it means that the switch unit is a slave switch unit. For example, if the above-mentioned multiplexing pins are used to define the master/slave switch unit, for example, the signal level of the multiplexing pin P4_TXD[2] of the master switch unit 101A shown in FIG. 2 will be at the first level “0” to indicate that the switch unit is set as a master switch unit. The signal level of the multiplexing pin P4_TXD[2] of the slave switch unit 101D shown in 2 will be at the second level "1" to indicate that the switch unit is set as a slave switch unit.

As for the OTP pin, the OTP pin is connected to the flash memory 105 through the SPI interface shown in FIG. 2, for example, and the flash memory 105 uses, for example, four bits of a specific address 0xC4 (but not limited) to represent the above embodiment information (for example, master/slave roles, signal port disable/enable, etc.). For example, the bit 0xC4[7] of the specific address 0xC4 indicates which pin is selected to determine the master/slave role of the switch unit. When the content of the bit 0xC4[7] is the first data content (such as "1", but not When it is limited), it means that the master/slave role is selected according to the multiplexing pin. On the contrary, when the content of bit 0xC4[7] is the second data content (such as "0", but not limited), it means that the selection is based on the OTP pin. Determines the master/slave role; in addition, bit 0xC4[2] of the specific address 0xC4 indicates whether to use the first signal port S0 for stack connection, for example, when the content of bit 0xC42] is "1", it indicates that the first signal port S0 is disabled for Stack connection, on the contrary, when the content of bit 0xC4[2] is "0", it means that the first signal port S0 is enabled for stack connection; in addition, bit 0xC4[3] of the specific address 0xC4 indicates whether to use the second signal port S1 for stacking For example, when the content of bit 0xC4[3] is "1", it means that the second signal port S1 is disabled for stack connection, on the contrary, when the content of bit 0xC4[3] is "0", it means that the second signal port S1 is enabled Make stack connections. For example, the content of the bit 0xC4[2] of the address 0xC4 to which the OTP pin of the switch unit 101A shown in FIG. 2 is connected is “1” to indicate that the first signal port SA0 is not used for stack connection, and the address of the address 0xC4 is “1”. The content of bit 0xC4[3] is "0" to indicate that the second signal port SA1 is enabled for stack connection. Furthermore, bit 0xC4[6] of address 0xC4 is used to determine the master/slave role of the stack. When the content of bit 0xC4[6] is "0", it means that the switch unit is set as a master switch unit, otherwise, when the bit 0xC4[6] is "0" When the content of 0xC4[6] is "1", it means that the switch unit is set as a slave switch unit. For example, the content of bit 0xC4[6] of the address 0xC4 to which the OTP pin of the switch unit 101A shown in FIG. 2 is connected is “1” to indicate that the switch unit 101A is set as a master switch unit.

In this way, through the above-mentioned one or more control pins (multiplexed pins and/or OTP pins) of each switch unit, the user can design a SoC on the circuit board and use an input/output The output interface is, for example, a general-purpose input/output interface (GPIO interface) to set the signal level of the multiplexed pin to set the master/slave role relationship of the switch units 101A-101D. , or the signal level of the multiplexed pin can be initialized and set directly through the resistance grounding design method. Therefore, for example, regarding the use of multiplexed pins, when the group of switch units 101A to 101D is in a system booting process, each switch unit 101A to 101D can be individually multiplexed according to its multiplexing mode after the stacking mode is performed. The signal level on the pin is automatically determined as a master unit or a slave unit and the enable or disable of the signal port for stack connection is determined, and after the master/slave role of the switch unit is determined, the processing of the master switch unit 101A The circuit 102A can then transmit the data or program code to the processing circuit 102B of the next slave switch unit 101B, and then the data or program code from the processing circuit 102B of the switch unit 101B to the processing circuit 102C of the next slave switch unit 101C, and finally The processing circuit 102C of the slave switch unit 101C transfers data or program code to the processing circuit 102D of the last slave switch unit 101D.

Furthermore, in terms of OTP pins, the switch unit 101A can obtain the bit of address 0xC4 through the OTP pins, for example, to determine whether it is the master switch unit and which signal port to use for stack connection, and can also use OTP pins. The pins obtain the stacking binary file and other related software/firmware programs from the flash memory 105, and then the master switch unit 101A can transfer the obtained binary files and other related software/firmware programs to its connection The slave switch unit, such as 101B, is then forwarded to other slave switch units 101C to 101D step by step, so that all master/slave switch units can obtain the corresponding stack configuration settings and related software/firmware program.

Please refer to FIG. 3 . FIG. 3 is a schematic flowchart of a method for generating and storing stack files and programs in the flash memory 105 according to an embodiment of the present invention. It should be noted that the steps of the method flow can be performed by the manufacturer of the switch unit or by the user of the switch unit. In other words, the generation of stack files and programs can be performed at the manufacturer's factory, or at the Client-side execution is not a limitation of this case. As shown in FIG. 3, in step S305, the manufacturer or the user can determine the stack topology through an electronic device such as a computer device or other control device. For example, the manufacturer can customize it according to the needs of its customers The stack topology is, for example, a stack topology of three switch units, including the master switch unit 101A and the slave switch units 101B to 101C, or in another embodiment, the user can decide the stack topology by himself and add it to the circuit The signal level design of the aforementioned control port is performed on the board, for example, the master switch unit is 101A and the slave switch units 101B and 101C. In step S310, the manufacturer or the user uses an electronic device, such as a computer device, to generate the setting of the stacking configuration. Then, in step S315, the manufacturer or user uses an electronic device, such as a computer device, to set the stacking configuration. Set other configuration settings, such as patch code, configuration of master switch unit 101A, configuration of slave switch unit 101B and configuration of slave switch unit 101C, data of software/firmware programs, etc. Setting, finally in step S320, the manufacturer or the user uses an electronic device such as a computer device to generate and write a stack file and related programs into the flash memory 105, the stack file and related programs include a stack configuration. Data such as settings, patch codes and other configuration settings of the master/slave switch unit.

Please refer to FIG. 4 . FIG. 4 is a schematic flowchart of a method for determining a switch unit as a master/slave switch unit during system startup according to an embodiment of the present invention. In step S405, when the switch unit is in the stack mode, the steps of the method flow are started. In step S410, the switch unit first obtains an address in an external memory device from the OTP pin, such as the data content of the bit of 0xC4, if bit 0xC4[7] indicates "0" (refer to the previous paragraphs. Pin setting/definition table and explanation, the same will be described later), it means that the OTP pin is selected to determine the master/slave role, and then step S420 will be performed; on the contrary, if the bit 0xC4[7] indicates "1", It means that the multiplexed pin is selected to determine the master/slave role, and then step S415 will be performed. In step S415, the switch unit determines which level the signal level on the multiplexing pin P5_TXD[3] is, if the signal level on the multiplexing pin P5_TXD[3] is the logic level "0", It means that the multiplexing pin is disabled; on the contrary, if the signal level on the multiplexing pin P5_TXD[3] is a logic level "1", it means that the multiplexing pin is enabled, in other words, if bit 0xC4[7] indicates that "1" and the signal level on the multiplexing pin P5_TXD[3] is a logic level "0", it means that neither the OTP pin nor the multiplexing pin is used to determine the stack structure, that is, in this case The stack structure is disabled at startup, and the flow goes to step S445.

In step S420, if the two bits 0xC4[3:2] obtained on the OTP pins all indicate "1", it means that both the first signal port S0 and the second signal port S1 are disabled for stack connection, in other words, if Bit 0xC4[7] indicates "0" but all bits 0xC4[3:2] indicate "1", which means that the stack structure is disabled at power-on in this case, and the flow proceeds to step S445. And if any one of the two bits 0xC4[3:2] does not indicate "1", the flow goes to step S430, and the data on the OTP pin is used to set the stack configuration, and then the flow goes to step S440, Enable stack structure and complete stack mode.

In step S425, if the signal levels on the two multiplexing pins P4_TXD[1:0] are both logic level "0", it means that both the first signal port S0 and the second signal port S1 are disabled for stack connection, In other words, if the signal level of the multiplexing pin P5_TXD[3] is logic level "1" but the signal levels on the two multiplexing pins P4_TXD[1:0] are both logic level "0", it means In this case, the stack structure is disabled when powering on, and the flow goes to step S445. And if any one of the signal levels on the two multiplexing pins P4_TXD[1:0] is not the logic level "0", the process proceeds to step S435, and the signal level on the multiplexing pins is used to set The stack is configured, and then the flow proceeds to step S440 to enable the stack structure and complete the stack mode. It should be noted that the process steps shown in FIG. 4 are executed by a processing circuit in a switch unit.

Please refer to FIG. 5 . FIG. 5 is a schematic flowchart of the operation and communication of two stacking switch units during system startup according to an embodiment of the present invention. As shown in FIG. 5 , taking the switch unit 101A and the switch unit 101B shown in FIG. 2 as an example, when the system boot procedure is executed, both the switch unit 101A and the switch unit 101B will enter the stack mode. The flow operation proceeds to step S505A, and the flow operation of the switch unit 101B proceeds to step S505B. In step S505A, the switch unit 101A will perform the boot stack setting, and is set as a master switch unit in this example, if successful, go to step S510A, otherwise, if the setting fails, go to step S540A, end Flow; in step S505B, the switch unit 101B will also perform the boot stack setting, and is set as a slave switch unit in this example, if successful, go to step S510B, otherwise, if the setting fails, go to step S510B S540B, the process ends.

In step S510A, the master switch unit 101A performs the connection and communication of the stack interface. Similarly, in step S510B, the slave switch unit 101B also performs the connection and communication of the stack interface. Therefore, in steps S515A and S515B, the master switch unit 101A transmits the settings of the stack configuration to the connected at least one slave switch unit (ie, including the slave switch unit 101B), and correspondingly the slave switch unit 101B will be sent from the connected at least one switch unit (may be a master/slave switch unit). , in this embodiment, the main switch unit 101A) receives the setting of the stack configuration. It should be noted that the master switch unit 101A can generate the stack configuration according to the data stored in the flash memory 105 , or directly download the stack configuration from the flash memory 105 .

Next, in steps S520A and S520B, the master switch unit 101A and the slave switch unit 101B determine whether to perform the encryption/decryption operation for transmission. The switch unit 101A will generate an encryption key and send the encryption key to the connected at least one slave switch unit, such as the slave switch unit 101B, and the slave switch unit 101B will be sent by the connected at least one switch unit (which can be a master/slave switch). unit) to receive the encryption key in order to perform subsequent decryption operations. Then, the flow proceeds to step S530A and step S530B. If it is determined in steps S520A and S520B that the transmission is not performed in an encrypted manner, the flow can directly go to steps S530A and S530B.

The master switch unit 101A transmits the firmware program (for example, obtained from the flash memory 105 ) to the connected at least one slave switch unit, such as the slave switch unit 101B, in step S530A, and the slave switch unit 101B receives the data from the slave switch unit 101B in step S530B. The firmware program of at least one connected switch unit (master/slave switch unit) is updated, and its firmware program is updated. It should be understood that if the master switch unit 101A determines in step S520A that the transmission is to be performed in an encrypted manner, in step S530A the master switch unit 101A encrypts the firmware program with an encryption key and then transmits it to the slave switch unit; The switch unit 101A determines in step S520A not to transmit in an encrypted manner, and in step S530A the master switch unit 101A can directly transmit the unencrypted firmware program to the slave switch unit.

Next, the master switch unit 101A will transmit other configuration settings to the connected at least one slave switch unit in step S535A, such as the slave switch unit 101B, and the slave switch unit 101B will receive the data from the connected at least one slave switch unit 101B in step S535B. Other configuration settings of a switch unit (which can be a master/slave switch unit), and the application implements the other configuration settings. If in S520A and step S520B, the master switch unit 101A and the slave switch unit 101B determine that the transmission is performed by an encryption operation, other configuration setting exchanges in steps S535A and S535B are also performed by corresponding encryption/decryption operations; In S520A and step S520B, it is determined that the transmission is not performed in an encrypted operation, and other configuration settings exchanges in steps S535A and S535B are performed in an unencrypted operation.

The master switch unit 101A completes the process steps of its stack mode in step S540A. The slave switch unit 101B can then determine whether the firmware program is encrypted in step S536. If it is determined that the firmware program is encrypted, the flow proceeds to step S537, and in step S537, the firmware program is decrypted according to the previously received encryption key. The firmware program can be applied to the slave switch unit 101B (for example, to update the firmware program of the slave switch unit 101B). On the contrary, if it is determined that the firmware program is not encrypted, step S540B is performed, and the slave switch unit 101B completes its stacking mode in step S540B. process steps. In one embodiment, a switch unit includes a default firmware program, and when the firmware program is updated, if the updated firmware program from the master switch unit is encrypted, it will be encrypted in step S537 according to the encrypted password. key to decrypt the updated firmware program.

It should be noted that the process steps shown in FIG. 5 are executed by the processing circuit 102A in the switch unit 101A and the processing circuit 102B in the switch unit 101B respectively.

It should be understood that the foregoing embodiments are only examples and are not used to limit the present invention. In some embodiments, the master switch unit 101A and the individual slave switch units 101B to 101D can perform a one-to-one key exchange, so that the individual slave switch units 101B to 101D hold different keys, so that the master switch unit 101A can communicate with The data transmission performed by the individual slave switch units 101B to 101D will not be decrypted by other slave switch units. For example, other slave switch units can be prevented from obtaining information of a specific switch unit. It should be noted that in an embodiment, , the firmware program information can be acquired by other slave switch units. Therefore, the master switch unit 101A and the other slave switch units 101B to 101D can encrypt/decrypt the firmware program based on the same key.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A method for use in a stackable switch unit capable of being stacked with at least one other stackable switch unit, wherein the method comprises: The stackable switch unit is provided, the stackable switch unit has a plurality of signal ports, the plurality of signal ports include at least one master/slave control port; During a boot-up procedure of the stacked switch unit, according to the content of at least one signal level of the at least one master/slave control port and/or at least one bit of data obtained from the at least one master/slave control port , to automatically determine whether the stacked switch unit is a master switch unit or a slave switch unit; and When the stackable switch unit is the master switch unit, a stack configuration setting is generated, and the stack configuration setting is transmitted to the stack through at least one signal port of the plurality of signal ports of the stackable switch unit the at least one other stackable switch unit to which the switch unit is connected, so that the stackable switch unit and the at least one other switch unit complete the stack connection. 2. The method of claim 1, further comprising: During the booting procedure of the stacked switch unit, according to the at least one signal level of the at least one master/slave control port and/or the at least one bit of data obtained from the at least one master/slave control port content to determine whether to use a first signal port and a second signal port of the stackable switch unit as a stack connection. 3. The method of claim 1, further comprising: When the stackable switch unit is the slave switch unit, a stack configuration device generated by a specific master switch unit or transferred by another slave switch unit is received through a first signal port of the stackable switch unit. In order to make the stackable switch unit complete the stack connection with the specific master switch unit or the other slave switch unit. 4. The method of claim 1, further comprising: When the stackable switch unit is connected to the at least one other stackable switch unit, a firmware program of a switch unit is transmitted to the at least one switch unit through the at least one signal port of the stackable switch unit, so that the The stackable switch unit has the same firmware program as the at least one other stackable switch unit. 5. A method for a stackable switch unit capable of being stacked with at least one other stackable switch unit, wherein the method comprises: The stackable switch unit is provided, the stackable switch unit has a plurality of signal ports, the plurality of signal ports include at least one master/slave control port; During a boot-up procedure of the stacked switch unit, according to the content of at least one signal level of the at least one master/slave control port and/or at least one bit of data obtained from the at least one master/slave control port , to automatically determine whether the stacked switch unit is a master switch unit or a slave switch unit; and When the stackable switch unit is the slave switch unit, a signal generated from a specific master switch unit and/or another signal is received through at least one of a first signal port and a second signal port of the stackable switch unit. A stack configuration setting forwarded by a slave switch unit enables the stackable switch unit to complete a stack connection with the particular master switch unit or the other slave switch unit, wherein the at least one other stackable switch unit includes the particular master switch unit switch unit and the other slave switch unit. 6. A stackable switch unit capable of being stacked with at least one other stackable switch unit, wherein the stackable switch unit comprises: a plurality of signal ports, the plurality of signal ports including at least one master/slave control port; and A processing circuit, coupled to the plurality of signal ports, is used for: During a boot-up procedure of the stacked switch unit, according to the content of at least one signal level of the at least one master/slave control port and/or at least one bit of data obtained from the at least one master/slave control port , automatically determine whether the stacked switch unit is a master switch unit or a slave switch unit. 7. The stackable switch unit of claim 6, wherein when the stackable switch unit is the master switch unit, the processing circuit is configured to generate a stack configuration setting and pass the stackable switch unit At least one signal port of the plurality of signal ports transmits the stack configuration setting to the at least one other stackable switch unit to which the stackable switch unit is connected, so that the stackable switch unit and the at least one other switch unit Complete the stack connection. 8. The stackable switch unit of claim 6, wherein the at least one master/slave control port comprises a plurality of multiplexing pins, wherein: a first multiplexing pin for determining whether the stackable switch unit is the master switch unit or the slave switch unit from the multiplexing pins, the first multiplexing pin is located at a first When the level is at a level, it means that the multiplexed pins are not used, and when the first multiplexed pin is at a second level, it means that the multiplexed pins are used; A second multiplexing pin is used to determine whether a first signal port of the stackable switch unit is enabled. When the second multiplexing pin is at the first level, it means it is disabled or disabled. When the multiplexing pin is at the second level, it is enabled; A third multiplexing pin is used to determine whether a second signal port of the stackable switch unit is enabled. When the third multiplexing pin is at the first level, it indicates that it is disabled or disabled. When the multiplexing pin is at the second level, it is enabled; and A fourth multiplexing pin is used to determine a master/slave role of the stacked switch unit. When the fourth multiplexer pin is at the first level, it represents a master switch unit role, and the fourth multiplexer is connected to When the pin is at the second level, it represents a slave switch unit role. 9. The stackable switch unit of claim 6, wherein the stackable switch unit is externally coupled to a flash memory device, the at least one master/slave control port comprises at least one control pin coupled to the flash memory device, The at least one control pin is used to read out a specific data stored in a specific address in the flash memory device, wherein the specific data includes: A first bit is used to determine whether the stackable switch unit is the master switch unit or the slave switch unit from a plurality of multiplexed pins included in the at least one master/slave control port, the first bit When a first data content is indicated, the plurality of multiplexing pins are used, and when the first bit indicates a second data content, the at least one control pin is used; A second bit is used to determine whether a first signal port of the stackable switch unit is enabled, the second bit indicates that the first data content is disabled or disabled, and the second bit indicates the second Data content indicates enable; A third bit is used to determine whether a second signal port of the stackable switch unit is enabled, the third bit indicates that the first data content is disabled or disabled, and the third bit indicates the second signal port data content means enabling; and A fourth bit is used to determine a master/slave role of the stacked switch unit. The fourth bit indicates a master switch unit role when the first data content is indicated, and the fourth bit indicates the second data content. Indicates a slave switch unit role. 10 . The stackable switch unit of claim 6 , wherein when the stackable switch unit is the slave switch unit, the processing circuit passes through a first signal port and a second signal port of the stackable switch unit. 11 . At least one of the signal ports receives a stack configuration setting generated from a specific master switch unit and/or forwarded by another slave switch unit, so that the stack switch unit and the specific master switch unit or the other A slave switch unit completes the stacking connection, wherein the at least one other stackable switch unit includes the specific master switch unit and the other slave switch unit.

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