CN114915358A - Radio monitoring system, method, device and storage medium - Google Patents

Abstract

The invention provides a radio monitoring system, comprising a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, and a host computer; the radio frequency front end is used to receive a signal to be analyzed through an antenna, and process the signal to be analyzed to obtain Intermediate frequency signal; AD data acquisition module is used to convert the intermediate frequency signal into IQ data, FPGA processor is used to store the IQ data and play it back based on the corresponding playback mode, and perform spectrum analysis on the IQ data during playback, and get the analysis results As well as analyzing the results, the DDR3 memory chip is used to store the IQ data received by the FPGA processor, and the host computer is used to run the human-computer interaction software, obtain user instructions based on the running human-computer interaction software, and issue them to the FPGA processor. User commands, and display of spectral waveforms based on analysis results.

Description

A radio monitoring system, method, device and storage medium

technical field

This specification relates to the field of radio monitoring, in particular to a radio monitoring system, method, device and storage medium.

Background technique

With the advancement of science and technology, the wireless communication industry has also achieved considerable development. The increasingly complex radio environment drives the radio monitoring system to comprehensively improve the goals of higher sensitivity, more convenient product form, and more abundant functions. For the spectrum analysis of radio signals, the purpose is to expand the superimposed and interleaved signals in the time domain to the frequency domain, so that the signals of different frequency components can be separated and further analyzed, so as to identify, locate, measure and orient the signals.

Therefore, it is desirable to provide a radio monitoring system, method, device and storage medium, which can realize controllable spectrum analysis speed, high-speed and large-capacity storage of IQ data, control the storage management of IQ data through an FPGA processor, and control the storage management of IQ data in playback mode. The IQ data performs normal, fast and slow spectrum analysis, which can better cope with signal search and detailed analysis, and further enrich the applicable scenarios of the radio monitoring system.

SUMMARY OF THE INVENTION

One or more embodiments of this specification provide a radio monitoring system, including a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, and a host computer;

The radio frequency front end is connected in communication with the AD data acquisition module, and the radio frequency front end is used for receiving the signal to be analyzed through the antenna, and performing at least one of amplifying, filtering, and frequency mixing processing on the signal to be analyzed, to get the intermediate frequency signal;

The AD data acquisition module is connected in communication with the FPGA processor, and the AD data acquisition module is used to convert the intermediate frequency signal into IQ data and upload it to the FPGA processor;

The FPGA processor is respectively connected to the DDR3 memory chip and the host computer for communication, and the FPGA processor is used to store the IQ data and play back based on the corresponding playback mode, and to perform the IQ data during playback. The data is subjected to spectrum analysis, and an analysis result is obtained and the analysis result is uploaded to the host computer; the playback mode includes at least one of a normal-speed spectrum analysis mode, a fast spectrum analysis mode, and a slow-speed spectrum analysis mode;

The DDR3 memory chip is used to store the IQ data received by the FPGA processor, and the data source during playback by the FPGA processor includes the IQ data stored by the DDR3 memory chip;

The upper computer is used for running human-computer interaction software, obtains user instructions based on the running human-computer interaction software, issues the user instructions to the FPGA processor, and displays spectrum waveforms based on the analysis results.

In some embodiments, the IQ data is sequentially stored in the DDR3 memory chip with reference to the acquisition timing; the FPGA processor is further configured to perform the following operations when performing spectrum analysis on the IQ data in the playback. : obtain the playback mode; according to the storage order of the IQ data in the DDR3 memory chip, read a plurality of data packets with reference to the corresponding reading rules based on the playback mode; wherein, in the plurality of data packets The points and/or lengths of the IQ data contained in each data packet are the same, and the sum of the lengths of all the IQ data in the multiple data packets does not exceed the preset storage length; in each of the data packets The number of points of the IQ data included is 2 ⁿ ; the IQ data in the acquired plurality of data packets is played back, and the IQ data is subjected to spectrum analysis during the playback.

In some embodiments, the reading rule includes an interval value; the acquiring the playback mode further includes acquiring the interval value; the interval value may be based on a length value or a number of points of the IQ data The value represents; the fetch interval value represents the length value or point value of the IQ data in the interval between the first IQ data in the two adjacent data packets.

In some embodiments, when the playback mode is the normal-speed spectrum analysis mode, the value of the fetch interval is equal to the length value or point value of the IQ data contained in one of the data packets; the playback mode is the fast spectrum. In the analysis mode, the fetch interval value is greater than the length value or point value of the IQ data contained in the data packet; when the playback mode is the slow spectrum analysis mode, the fetch interval value is less than one The length value or point value of the IQ data contained in the data packet.

In some embodiments, the value of the fetch interval is determined based on a first prediction model, the first prediction model is a machine learning model, and the first prediction model is used based on the data collection rate, transmission delay, and verification error rate. at least one of , noise rate, size and quantity of MTU, and determine the value of the fetch interval.

In some embodiments, the preset storage length does not exceed the total length of the IQ data that the DDR3 memory chip can store.

In some embodiments, the preset storage length is determined based on a second prediction model, the first prediction model is a machine learning model, and the first prediction model is used based on the data characteristics of the IQ data, the fetching The preset storage length is determined by at least one of an interval value, the number of points of the IQ data contained in one of the data packets, and the characteristics of the AD data acquisition module.

In some embodiments, the FPGA processor is connected to the DDR3 memory chip through a PCIe interface.

In some embodiments, the AD data acquisition module is communicated with the FPGA processor through a jesd204b interface.

One or more embodiments of this specification provide a radio monitoring method, which is implemented based on an FPGA processor in the aforementioned radio monitoring system. The radio monitoring method includes: accepting IQ data uploaded by the AD data acquisition module; IQ data is stored and sent to the DDR3 memory chip; the playback mode and reading rules are obtained based on the host computer; based on the playback mode, multiple data packets are read from the DDR3 memory chip with reference to the corresponding read rules ; Play back the IQ data in the acquired multiple data packets, and perform spectrum analysis on the IQ data in the playback; upload the analysis result to the host computer.

One or more embodiments of this specification provide a computer-readable storage medium, where the storage medium stores computer instructions, and after the computer reads the computer instructions in the storage medium, the computer executes the radio monitoring method.

One or more embodiments of the present specification provide a radio monitoring apparatus, the apparatus includes a processor and a memory; the memory is used for storing instructions, which when executed by the processor, cause the apparatus to implement the Operations corresponding to the radio monitoring method.

Description of drawings

The present specification will be further described by way of example embodiments, which will be described in detail with reference to the accompanying drawings. These examples are not limiting, and in these examples, the same numbers refer to the same structures, wherein:

1 is a schematic diagram of an application scenario of a radio monitoring system according to some embodiments of the present specification;

FIG. 2 is an exemplary structural diagram of a radio monitoring system according to some embodiments of the present specification;

FIG. 3 is a schematic diagram of a first prediction model according to some embodiments of the present specification;

4 is a schematic diagram of a first prediction model according to two embodiments of the present specification;

FIG. 5 is an exemplary flowchart of a radio monitoring method according to some embodiments of the present specification;

6 is an exemplary structural diagram of an FPGA processing device for a radio monitoring system according to some embodiments of the present specification;

7 is an exemplary flowchart of a spectrum analysis method for a radio monitoring system according to some embodiments of the present specification;

8 is a schematic diagram of data packet reading in a normal-speed spectrum analysis mode according to some embodiments of the present specification;

9 is a schematic diagram of data packet reading in a fast spectrum analysis mode according to some embodiments of the present specification;

FIG. 10 is a schematic diagram of data packet reading in a slow spectrum analysis mode according to some embodiments of the present specification.

Detailed ways

In order to illustrate the technical solutions of the embodiments of the present specification more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present specification. For those of ordinary skill in the art, without creative efforts, the present specification can also be applied to the present specification according to these drawings. other similar situations. Unless obvious from the locale or otherwise specified, the same reference numbers in the figures represent the same structure or operation.

It is to be understood that "system", "device", "unit" and/or "module" as used herein is a method used to distinguish different components, elements, parts, parts or assemblies at different levels. However, other words may be replaced by other expressions if they serve the same purpose.

As shown in the specification and claims, unless the context clearly dictates otherwise, the words "a", "an", "an" and/or "the" are not intended to be specific in the singular and may include the plural. Generally speaking, the terms "comprising" and "comprising" only imply that the clearly identified steps and elements are included, and these steps and elements do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

Flowcharts are used in this specification to illustrate operations performed by a system according to an embodiment of this specification. It should be understood that the preceding or following operations are not necessarily performed in the exact order. Instead, the various steps can be processed in reverse order or simultaneously. At the same time, other actions can be added to these procedures, or a step or steps can be removed from these procedures.

FIG. 1 is a schematic diagram of an application scenario 100 of a radio monitoring system according to some embodiments of this specification.

In some embodiments, the application scenario 100 may be configured as radio monitoring or the like. It can be applied in corresponding communication control scenarios such as radio monitoring, radio identification, and radio management. The application scenario 100 may include a server 110 , a network 120 , a user terminal 130 , a storage device 140 and a signal source 150 . Server 110 may include processing engine 112 . In some embodiments, server 110, user terminal 130, storage device 140, and signal source 150 may connect and/or communicate with each other via a wireless connection (eg, network 120), a wired connection, or a combination thereof.

Server 110 may be used to implement radio monitoring. In some embodiments, it can be specifically used to monitor radios such as satellites. This monitoring technology can be applied to government departments, national defense forces, news media, customs, diplomacy, combat readiness communications, and many other fields.

The server 110 refers to a system with computing capabilities. In some embodiments, the server 110 may be a single server or a group of servers. The server group may be centralized or distributed (eg, server 110 may be a distributed system). In some embodiments, server 110 may be local or remote. For example, the server 110 may access information and/or data stored in the user terminal 130 and/or the storage device 140 via the network 120 . As another example, the server 110 may be directly connected to the user terminal 130 and/or the storage device 140 to access stored information and/or data. In some embodiments, server 110 may be implemented on a cloud platform. For example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distribution cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof. In some embodiments, server 110 may be implemented on computing device 200 having one or more of the components shown in FIG. 2 herein.

In some embodiments, server 110 may include processing engine 112 . Processing engine 112 may process information and/or data related to wireless signals. For example, the processing engine 112 may implement radio monitoring in the telematics data acquired by the signal source 150 . In some embodiments, processing engine 112 may include one or more processing engines (eg, a single-core processing engine or a multi-core processor). For example only, the processing engine 112 may include one or more hardware processors, such as a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), digital signal processor (DSP), field programmable gate array (FPGA), programmable logic device (PLD), controller, microcontroller unit, reduced instruction set computer (RISC), microprocessor, etc. or any combination thereof.

Network 120 may facilitate the exchange of information and/or data. In some embodiments, one or more components in application scenario 100 (eg, server 110 , user terminal 130 , storage device 140 , and signal source 150 ) may send information and/or data over network 120 to other components in application scenario 100 . other components. For example, the processing engine 112 may send the analysis results of the monitored radios to the user terminal 130 via the network 120 . In some embodiments, the network 120 may be a wired network or a wireless network, or the like, or any combination thereof. By way of example only, the network 120 may include a cable network, a wired network, a fiber optic network, a telecommunications network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network ( WAN), Public Switched Telephone Network (PSTN), Bluetooth™ network, ZigBee network, Near Field Communication (NFC) network, or the like, or any combination thereof. In some embodiments, network 120 may include one or more network access points. For example, network 120 may include wired or wireless network access points such as base stations and/or Internet exchange points 120-1, 120-2, . . . through which one or more components of application scenario 100 may be accessed Points are connected to the network 120 to exchange data and/or information.

In some embodiments, the user terminal 130 may include a mobile device 130-1, a tablet computer 130-2, a laptop computer 130-3, a desktop computer 130-4, the like, or any combination thereof. In some embodiments, mobile device 140-1 may include a smart home device, wearable device, mobile device, virtual reality device, augmented reality device, etc., or any combination thereof. In some embodiments, smart home devices may include smart lighting devices, smart appliance control devices, smart monitoring devices, smart TVs, smart cameras, walkie-talkies, etc., or any combination thereof. In some embodiments, the wearable device may include a bracelet, footwear, glasses, helmet, watch, clothing, backpack, smart accessory, etc., or any combination thereof. In some embodiments, mobile devices may include mobile phones, personal digital assistants (PDAs), gaming devices, navigation devices, point-of-sale (POS) devices, laptops, desktops, etc., or any combination thereof. In some embodiments, a virtual reality device and/or an augmented virtual reality device may include a virtual reality headset, virtual reality glasses, virtual reality goggles, augmented reality helmet, augmented reality glasses, augmented reality goggles, etc., or any combination thereof. For example, virtual reality devices and/or augmented reality devices may include GoogleGlass ^™ , RiftCon ^™ , Fragments ^™ , GearVR ^™ , and the like.

In some embodiments, user terminal 130 may be a mobile terminal configured to acquire radio signals. User terminal 130 may send and/or receive information related to radio signal monitoring and identification to processing engine 112 or a processor installed in user terminal 130 via a user interface. For example, the user terminal 130 may transmit radio signal data captured by the user terminal 130 to the processing engine 112 or processor installed in the user terminal 120 via the user interface. The user interface may be in the form of an application implemented on the user terminal 130 for identifying satellites. A user interface implemented on the user terminal 130 may facilitate communication between the user and the processing engine 112 . For example, a user may input and/or import radio signal data to be identified via the user interface. The processing engine 112 may receive incoming signal data via a user interface. As another example, a user may input a request to identify a radio signal via a user interface implemented on the user terminal 130 . In some embodiments, in response to the identification request, the user terminal 130 may directly process the radio signal data via the processor of the user terminal 130 based on signal acquisition means installed in the user terminal 130 as described elsewhere in this application. In some embodiments, in response to the identification request, the user terminal 130 may send the identification request to the processing engine 112 for determining the radio signal based on the signal acquisition device installed by the signal source 150 or elsewhere herein. In some embodiments, the user interface may facilitate presenting or displaying information and/or data (eg, signals) received from the processing engine 112 related to radio monitoring. For example, the information and/or data may include results indicating the content of radio monitoring, or indicating that radio monitoring is performed, or the like. In some embodiments, the information and/or data may be further configured to cause the user terminal 130 to display the results to the user.

Storage device 140 may store data and/or instructions. In some embodiments, storage device 140 may store data obtained from signal source 150 . The storage device 140 may store data and/or instructions that the processing engine 112 may execute or use to perform the example methods described in this application. In some embodiments, storage device 140 may include mass storage, removable storage, volatile read-write memory, read-only memory (ROM), the like, or any combination thereof. Exemplary mass storage may include magnetic disks, optical disks, solid state drives, and the like. Exemplary removable storage may include flash drives, floppy disks, optical disks, memory cards, compact disks, magnetic tapes, and the like. Exemplary volatile read-write memory may include random access memory (RAM). Exemplary RAMs may include dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), static random access memory (SRAM), thyristor random access memory (T-RAM), and zero capacitance Random Access Memory (Z-RAM), etc. Exemplary ROMs may include masked read only memory (MROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), optical disk only Read-only memory (CD-ROM) and digital versatile disk read-only memory, etc. In some embodiments, the storage device 140 may execute on a cloud platform. For example only, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distribution cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

In some embodiments, storage device 140 may be connected to network 120 to communicate with one or more components in application scenario 100 (eg, server 110 , user terminal 130 ). One or more components in application scenario 100 may access data or instructions stored in storage device 140 via network 120 . In some embodiments, storage device 140 may be directly connected to or in communication with one or more components in application scenario 100 (eg, server 110, user terminal 130). In some embodiments, storage device 140 may be part of server 110 .

The signal source 150 is a signal terminal that sends out a radio signal. For example, the signal source can be a satellite, a signal generator, a base station, and the like. The radio signal generated by the signal source 150 can be collected based on the corresponding signal collection device.

It should be noted that the above description is intended to be illustrative, and not to limit the scope of the present application. Numerous alternatives, modifications and variations will be apparent to those skilled in the art. The features, structures, methods and other characteristics of the exemplary embodiments described herein may be combined in various ways to obtain additional and/or alternative exemplary embodiments. For example, the signal source 150 may be configured with a storage module, a processing module, a communication module, and the like. However, these changes and modifications do not depart from the scope of this application.

FIG. 2 is an exemplary structural diagram of a radio monitoring system according to some embodiments of the present specification.

As shown in FIG. 2 , the radio monitoring system 200 may include a radio frequency front end 210 , an AD data acquisition module 220 , an FPGA processor 230 , a DDR3 memory chip 240 , and a host computer 250 .

In some embodiments, the RF front end 210 may be used to receive radio signals from a signal source (eg, signal source 15). In some embodiments, the RF front end may consist of a series of components between a radio frequency transceiver and an antenna, such as It may include a power amplifier (PA), an antenna switch (Switch), a filter (Filter), a duplexer (Duplexer and Diplexer), a low noise amplifier (LNA), and the like. In some embodiments, the radio frequency front end is connected in communication with the AD data acquisition module, and the radio frequency front end is used for receiving the signal to be analyzed through an antenna, and performing amplifying, filtering, and frequency mixing processing on the signal to be analyzed. at least one processing to obtain an intermediate frequency signal.

In some embodiments, the AD data acquisition module 220 may be designed with an ADI high-speed AD chip. In some embodiments, the AD data acquisition module 220 is connected in communication with the FPGA processor, and the AD data acquisition module is configured to convert the intermediate frequency signal into IQ data and upload it to the FPGA processor.

In some embodiments, the FPGA processor 230 may be respectively connected to the DDR3 memory chip and the host computer for communication, and the FPGA processor is configured to store the IQ data and play back the IQ data based on the corresponding playback mode. Perform spectrum analysis on the IQ data during playback, and obtain analysis results and upload the analysis results to the host computer; the playback modes include a normal-speed spectrum analysis mode, a fast spectrum analysis mode, and a slow-speed spectrum analysis mode. at least one of.

More details on the FPGA processor 230 can be found in FIGS. 5-7 and their descriptions.

In some embodiments, the DDR3 memory chip 240 is configured to store the IQ data received by the FPGA processor, and the data source during playback by the FPGA processor includes the IQ data stored by the DDR3 memory chip .

The DDR3 memory chip is used as the IQ data storage unit, which has low cost, small board size, storage capacity that can be expanded to several GB, and storage speed that supports more than ten GB/s, which can meet the storage of original IQ data at high sampling rates. Different sampling rates can support storage time from several seconds to several minutes, which fully meets the routine monitoring needs of radio signals.

In some embodiments, the host computer 250 may be used to run human-computer interaction software, obtain user instructions based on the running human-computer interaction software, and issue the user instructions to the FPGA processor, and based on the analysis The result shows the spectrum waveform.

In some embodiments, the radio monitoring system in the embodiments of this specification can support the normal-speed spectrum analysis mode and the fast and slow spectrum analysis modes in the data playback process. Different playback modes have different operation steps. The main difference is that Jump control of IQ data fetch interval during playback.

It should be noted that the above description of the system and its components is only for the convenience of description, and does not limit the description to the scope of the illustrated embodiments. It can be understood that for those skilled in the art, after understanding the principle of the system, it is possible to arbitrarily combine the various components, or form a subsystem to connect with other components without departing from the principle. For example, the RF front end and AD data acquisition module can be integrated in one component. For another example, each component may share one storage device, and each component may also have its own storage device. Such deformations are all within the protection scope of this specification.

FIG. 5 is an exemplary flowchart of a radio monitoring method according to some embodiments of the present specification. In some embodiments, the process 500 may be executed by the FPGA processor 230 . In some embodiments, process 500 may include the following steps:

Step 510: Accept the IQ data uploaded by the AD data collection module.

In some embodiments, the radio monitoring system may first collect the received signal through the antenna based on the radio frequency front end, and then perform processing such as amplifying, filtering, and frequency mixing on the collected signal based on the radio frequency front end, and then output an intermediate frequency signal.

In some embodiments, the RF front-end can transmit the intermediate frequency signal obtained by it to an AD data acquisition module designed with an ADI high-speed AD chip, and the AD data acquisition module performs signal conversion processing on the received intermediate frequency signal, and then obtains the corresponding The digital signal is IQ data.

In some embodiments, the AD data acquisition module can re-send the IQ data processed by the AD data acquisition module to an FPGA processor as a signal processing unit.

Step 520, the IQ data is stored and sent to the DDR3 memory chip.

In some embodiments, the FPGA processor can cache the real-time IQ data uploaded by the AD data acquisition module, and at the same time, forward the data to the DDR3 memory chip.

In some embodiments, the DDR3 memory chip can store all IQ data uploaded by the AD data acquisition module. In some embodiments, the DDR3 memory chip may store the IQ data according to the collection timing of the radio signal corresponding to the IQ data.

Step 530: Obtain the playback mode and the reading rule based on the host computer.

In some embodiments, the user can input the required playback mode based on the host computer, and the host computer transmits the playback mode entered by the user to the FPGA processor. In some embodiments, reading rules corresponding to various playback modes may be pre-stored in the radio monitoring system, and the FPGA processor may determine the corresponding reading rules based on the playback mode after determining the playback mode. In some embodiments, the playback mode may include at least one of a normal speed spectrum analysis mode, a fast spectrum analysis mode, and a slow speed spectrum analysis mode. See step 540 for a specific description of the playback mode.

A read rule refers to a rule for the FPGA processor to read IQ data from a data source. In some embodiments, the read rule may include a fetch interval value. In some embodiments, the fetch interval value may be expressed based on a length value or a point value of the IQ data. The fetch interval value represents the length value or point value of the IQ data in the interval between the first IQ data in two adjacent data packets.

Step 540: Read a plurality of data packets from the DDR3 memory chip based on the playback mode with reference to the corresponding read rule.

In some embodiments, the FPGA processor may read a plurality of data packets according to the storage order of the IQ data in the DDR3 memory chip and with reference to the corresponding read rule based on the playback mode; wherein the plurality of data packets are The points and/or lengths of the IQ data contained in each data packet in the data packets are the same, and the sum of the lengths of all the IQ data in the multiple data packets does not exceed the preset storage length; The number of points of the IQ data contained in the data packet is 2 ⁿ , such as 2048 points, 4096 points, and the like. In some embodiments, the number of data points contained in one data packet is the number of FFT processing points in one packet of subsequent FFT processing (ie, the FFT length of one packet).

In some embodiments, reading multiple data packets with reference to the corresponding reading rule based on the playback mode is mainly based on reading multiple data packets based on a fetch interval value determined by the reading rule corresponding to the playback mode.

In some embodiments, when the playback mode is the normal-speed spectrum analysis mode, the value of the fetch interval is equal to the length value or the point value of the IQ data contained in one of the data packets. For example, when the number of points of the IQ data contained in one of the data packets is 2048 points, the value of the fetch interval may be equal to 2048 points. That is, in the normal-speed spectrum analysis mode, each data packet read by the FPGA processor is continuous data in the DDR3 memory chip.

For example only, when the playback mode is the normal-speed spectrum analysis mode, after the FPGA processor has finished reading a packet of FFT-length IQ data, it continues to read the next packet of FFT-length IQ data from adjacent addresses until The sum of the lengths of all the IQ data in the multiple data packets does not exceed the preset storage length, and the preset storage length may refer to the data length reaching the storage boundary, that is, the preset storage length does not exceed the DDR3 memory chip. The total length of the stored IQ data, or the required data length. For more description about the preset storage length, refer to FIG. 4 and its description, which will not be repeated here.

It should be noted that the preset storage length refers to the data length that reaches the storage boundary. If the data length of all the read data reaches the storage boundary, if the remaining IQ data cannot form a complete FFT length, then the last Packet data is discarded and no subsequent spectrum analysis is performed to avoid spectrum leakage.

In some embodiments, when the playback mode is the fast spectrum analysis mode, the fetch interval value is greater than the length value or point value of the IQ data contained in one of the data packets; for example, one of the data packets When the number of points of the IQ data contained in the IQ data is 2048 points, the value of the fetch interval may be equal to 3000 points. In some embodiments, the number interval value of the fast spectrum analysis mode can be based on a preset, such as set by the user. In some embodiments, the number interval value of the fast spectrum analysis mode can also be determined by a machine learning model. OK, see Figure 3 and its description for a specific description.

In some embodiments, the fetch interval value can also be expressed based on the address jump amount. For example, in the fast spectrum analysis mode, the address jump amount can be equal to the difference between the fetch interval value and a packet of FFT length values. For example, when the playback mode is the fast spectrum analysis mode, the address jump amount can be greater than the length of a packet of FFT. After the IQ data of a packet of FFT length is read, the FPGA processor will skip a segment of data at adjacent addresses. The length of the piece of data is the difference between the fetch interval value and the value of the FFT length of a packet, that is, the address jump amount, and then starts to read the IQ data of the FFT length of the next packet, until all the IQ data in the multiple data packets are The sum of the length of the data does not exceed the preset storage length. In this case, the readable times of the entire DDR3 memory chip storage space is reduced, and by sampling the data, it is equivalent to improving the speed of spectrum analysis.

In some embodiments, when the playback mode is the slow spectrum analysis mode, the fetch interval value is smaller than the length value or point value of the IQ data contained in one of the data packets, for example, one of the data When the number of points of the IQ data contained in the package is 2048 points, the value of the fetch interval may be equal to 1500 points. In some embodiments, the value of the fetch interval of the slow spectrum analysis mode can be based on a preset, such as set by the user, in some embodiments, the value of the fetch interval of the slow spectrum analysis mode can also be learned by machine learning The model is determined, and the specific description is shown in Figure 3 and its description.

In some embodiments, when the playback mode is the slow spectrum analysis mode, the fetch interval value may also be expressed based on the address jump amount. For example, in the slow spectrum analysis mode, the address jump amount may be equal to one packet of FFT The difference between the length value and the fetch interval value. Just as an example, when the playback mode is the slow spectrum analysis mode, the address jump amount is less than the length of a packet of FFT, and after a packet of IQ data with the length of FFT is read, it will jump back a segment of addresses from the end address (that is, address jumps). amount) to start reading the IQ data with the FFT length of the next packet, until the sum of the lengths of all the IQ data in the multiple data packets does not exceed the preset storage length. In this case, the readback addresses have overlapping parts, and a certain segment of IQ data will be read many times, and the read times of the entire DDR3 memory chip will increase, which is equivalent to slowing down the speed of spectrum analysis.

Similarly, it should be noted that when the playback mode is the fast spectrum analysis mode or the slow spectrum analysis mode, the preset storage length refers to the data length that reaches the storage boundary, and if the data length of all the read data reaches the storage boundary , if the remaining IQ data cannot form a complete packet of FFT length, the last packet of data is discarded, and subsequent spectrum analysis is not performed to avoid spectrum leakage.

Step 550: Play back the acquired IQ data in the multiple data packets, and perform spectrum analysis on the IQ data during playback to obtain an analysis result.

In some embodiments, the FPGA processor, as a signal processing unit, can control the storage and playback of IQ data, and control the speed of spectrum analysis in playback mode according to settings, such as selecting fast, normal, and slow spectrum analysis. speed, and finally get the corresponding spectral analysis results.

Step 560, upload the analysis result to the host computer

In some embodiments, the FPGA processor can upload the spectrum analysis result to the host computer through the PCIe interface, and the host computer can further display the graph in the application software, so that the user can intuitively understand the relevant indicators of the signal.

In some embodiments of the present invention, a radio monitoring system for fast and slow spectrum analysis and IQ recording and playback is designed by using FPGA and DDR3 memory chip. The system can switch the spectrum analysis speed in the IQ playback state to target different radio monitoring tasks: in the application scenarios of fast signal search and signal identification, fast spectrum analysis can be selected to save retrieval time; When changing signals for detailed analysis, slow spectrum analysis can be selected to obtain finer-grained technical indicators and observation effects. DD

It should be noted that the above description about the process 500 is only for example and illustration, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to the process 500 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

FIG. 3 is a schematic diagram of a first prediction model 300 according to some embodiments of the present specification.

In some embodiments, the first prediction model may be a model for predicting the fetch interval value. For example, Convolutional Neural Networks (CNN), Deep Neural Networks (DNN), etc., or a combination thereof.

In some embodiments, the input of the first prediction model may include one of data collection rate, transmission delay, check error rate, noise rate, size and number of MTU, playback mode, number of data points in a data packet, or variety. In some embodiments, the output of the first prediction model may include estimated fetch interval values.

In some embodiments, the data acquisition rate may refer to the rate at which data is transmitted to the FPGA processor based on the AD data acquisition module, for example, may refer to the number of data points transmitted per unit time, and the transmission rate may be determined by bit rate and baud rate express. For example, the transmission rate can be 100bit/s or 5B. In some embodiments, the transmission delay refers to the total time required by the data sender (eg, AD data acquisition module) from the start of sending the data frame to the completion of sending the data frame, and the transmission delay is related to the size of the sent data frame. For example, if the data frame size is 2000bit and the transmission rate is 200bit/s, the transmission delay is 1s. In some embodiments, the verification error rate is the ratio of the data with errors obtained by verifying whether the transmitted data is correct during data transmission. In some embodiments, the method of checking the transmitted data may include parity checking, code sum checking, cyclic redundancy checking, and the like. In some embodiments, the check error rate may include a bit error (bit) rate, a character error rate, and the like.

In some embodiments, the noise ratio refers to a ratio of data points where errors occur due to external noise interference during data transmission. For example, if the size of the transmitted data frame is 100 bits, and the data points with errors caused by external noise interference are 20 bits, the noise rate is 20%.

In some embodiments, the data size of the data frame may be related to a maximum transmission unit (Maximum Transmission Unit, MTU). The data size of the data frame is not larger than the size of the MTU. For example, the data size of the data frame is equal to or close to the size of the MTU. MTU refers to the maximum packet size that a communication protocol can pass above a certain layer. The MTU can describe the payload size that the sender can accept. The size of the MTU can be in bytes.

In some embodiments, the playback mode may include a normal-speed spectrum analysis mode, a fast spectrum analysis mode, and a slow-speed spectrum analysis mode. For more descriptions of the playback modes, please refer to FIG. 5 and its description.

In some embodiments, the number of data points in a data packet refers to the number of points and/or the length of the IQ data contained in each data packet, and generally takes a value of 2 ⁿ . More details on the number of data points in a data packet See Figure 5 and its description.

In some embodiments, the first prediction model may be obtained by training a plurality of labeled training samples. For example, a plurality of training samples with labels can be input into the initial first prediction model, a loss function can be constructed by using the labels and the results of the initial first prediction model, and parameters of the initial first prediction model can be iteratively updated based on the loss function. When the loss function of the initial first prediction model satisfies the preset condition, the model training is completed, and the trained first prediction model is obtained. The preset conditions may be that the loss function converges, the number of iterations reaches a threshold, and the like.

In some embodiments, the training samples may include at least multiple groups of historical sample data, and each group of historical sample data may include the historical data collection rate, historical transmission delay, historical verification error rate, and historical noise rate corresponding to a historical playback mode , the size and number of historical MTUs, and the number of data points in a packet. The label may be the fetch interval value corresponding to the historical playback mode. Labels can be obtained based on manual annotations.

Through the first prediction model, the fetch interval value of the data point can be accurately predicted, thereby determining a more appropriate reading rule to read the data, reducing the possibility of continuous data loss or invalidity, and reducing the unread data. Impact on the validity of the overall data analysis.

FIG. 4 is a schematic diagram of a process 400 of training and executing a second prediction model according to some embodiments of the present specification.

In some embodiments, the value of the preset storage length can be predicted based on the second prediction model. In some embodiments, the preset storage length does not exceed the total length of the IQ data that the DDR3 memory chip can store. In some embodiments, the size of the preset storage length can be adjusted. For example, the preset memory length is adjusted from 2 ¹⁰ to 2 ²⁰ . In some embodiments, a preset storage length is set for the storage capacity of the DDR3 memory chip. For example, the larger the storage capacity of the DDR3 memory chip, the larger the preset storage length.

In some embodiments, the preset memory length may be estimated based on the second prediction model. In some embodiments, the second prediction mode may be implemented by a deep neural network (Deep Neural Networks, DNN), a convolutional neural network (Convolutional Neural Networks, CNN), or the like.

In some embodiments, the input 430 of the second prediction module 440 may be the data characteristics of the IQ data, the fetch interval value, the number of IQ data points contained in one data packet, the characteristics of the AD data acquisition module, and the storage of the DDR3 memory chip. capacity, etc., the output 450 may be a preset storage length. The data features of the IQ data refer to features that characterize the features of the IQ data, for example, may include collection time, length, type, and the like. The data features of the IQ data can be acquired based on the AD data acquisition module. The features of the AD data acquisition module may include features such as chip model, processing speed, capacity, etc. that characterize the performance of the AD data acquisition module. The features of the AD data acquisition module can be obtained based on the specification of the AD data acquisition module. For descriptions on the value of the fetch interval, the number of IQ data points contained in a data packet, the storage capacity of the DDR3 memory chip, etc., please refer to FIG. 3, FIG. 5, etc., and will not be repeated here.

In some embodiments, the second prediction model 440 may be trained based on a large number of labeled training samples 410 . For example, the training samples 410 with labels are input into the initial second prediction module 420, a loss function is constructed by the labels and the prediction results of the initial second prediction module 420, and the parameters of the model are iteratively updated based on the loss function. When the trained model meets the preset conditions, the training ends. The preset conditions are that the loss function converges, the number of iterations reaches a threshold, and the like.

In some embodiments, the training samples may include at least the data characteristics of the sample IQ data, the sampling interval value, the number of IQ data points contained in the sample data package, the characteristics of the sample AD data acquisition module, and the storage capacity of the sample DDR3 memory chip. . The label can be the actual set storage length. Labels can be generated based on historical data obtained from storage systems, and labels can also be manually annotated.

Some embodiments of this specification can realize the data characteristics based on IQ data, the value of fetch interval, the number of IQ data points contained in a data packet, the characteristics of AD data acquisition module, and the storage of DDR3 memory chips by processing the preset storage length. Capacity and other information to determine the preset storage length, which can effectively improve the accuracy of the preset storage length, reduce the difficulty of manual calculation, and improve the efficiency of data processing.

FIG. 6 is a diagram showing an exemplary structure of an FPGA processing apparatus used in a radio monitoring system according to some embodiments of the present specification.

As shown in FIG. 6 , the FPGA processing device (ie the aforementioned FPGA processor) may include a bandwidth matching and buffering module 610 , a spectrum analysis playback control module 620 , a data source selection module 630 , a digital signal processing module 640 and an external connection module 650 .

In some embodiments, the bandwidth matching and buffering module is respectively connected in communication with the data source selection module and the spectrum analysis playback control module, and the bandwidth matching and buffering module can be used for receiving digital signals and processing received digital signals. The digital signal is buffered.

In some embodiments, the data source selection module is respectively connected in communication with the spectrum analysis playback control module and the digital signal processing module. The data source selection module may be configured to determine the data source read when the spectrum analysis playback control module performs data playback and spectrum analysis. In some embodiments, the data source selection module may accept user-set data source information based on peripheral devices such as a host computer.

In some embodiments, the spectrum analysis playback control module is in communication with a storage device of the radio monitoring system. In some embodiments, the spectrum analysis playback control module may be configured to read a plurality of data packets from the data source based on a playback mode and refer to a reading rule corresponding to the playback mode, and perform a corresponding analysis on the obtained plurality of data packets. The digital signal in the data packet is played back, and an analysis result is obtained by performing spectrum analysis on the digital signal in the playback. For a specific description, reference may be made to FIG. 7 and its description, which will not be repeated here.

In some embodiments, the digital signal processing module includes a digital filtering unit, an FFT unit, and a detection unit connected in sequence. In some embodiments, the digital signal processing module is configured to perform digital filtering, fast Fourier transform, and wave detection on the playback data in the spectrum analysis playback control module.

In some embodiments, the external connection module is configured to implement communication between the FPGA processing device and at least some devices in the radio monitoring system other than the FPGA processing device. For example, the external connection module may include PCIe interface, jesd204b interface, etc., the FPGA processing device may be connected with the DDR3 memory chip through the PCIe interface, and the AD data acquisition module and the FPGA processing device may be communicated and connected through the jesd204b interface.

It should be noted that the above description of the system and its components is only for the convenience of description, and does not limit the description to the scope of the illustrated embodiments. It can be understood that for those skilled in the art, after understanding the principle of the system, it is possible to arbitrarily combine the various components, or form a subsystem to connect with other components without departing from the principle. For example, the data source selection module and the spectrum analysis playback control module can be integrated in one component. For another example, each component may share one storage device, and each component may also have its own storage device. Such deformations are all within the protection scope of this specification.

FIG. 7 is an exemplary flowchart of a radio monitoring method according to some embodiments of the present specification. In some embodiments, the process 700 may be executed by an FPGA processing device. In some embodiments, process 700 may include the following steps:

Step 710: Acquire storage parameters of the data to be analyzed.

The data to be analyzed refers to the data to be subjected to spectrum analysis, such as the aforementioned IQ data or data such as digital signals. In some embodiments, the storage parameters may include parameters such as storage start point, storage length, and the like. In some embodiments, the storage parameters may be set by the user based on the host computer.

Step 720: Store the data to be analyzed based on the storage parameter.

In some embodiments, after the FPGA processing device acquires the storage parameters, the corresponding storage can be performed. For example, the FPGA processing device may store the data to be analyzed based on the storage starting point and storage length set by the user obtained from the host computer.

Step 730 acquires a playback instruction, where the playback instruction includes a playback mode and a data source; the playback mode includes a normal-speed spectrum analysis mode, a fast spectrum analysis mode, and a slow-speed spectrum analysis mode.

In some embodiments, the playback instruction may be based on user settings through the host computer, for example, the user sends the FPGA processing device through the host computer to use the fast spectrum analysis mode for playback.

Step 740, determining an address offset based on the playback mode.

The address offset refers to the data offset that needs to be spaced between each data packet when the FPGA processing device reads data. In some embodiments, the address offset can be represented by the address jump amount. Regarding the address jump amount For more descriptions, refer to FIG. 5, which will not be repeated here.

Step 750, based on the address offset, read data of a preset length from the data source as a data packet.

After the playback mode is determined, the address offset can be determined based on the playback mode, and the FPGA processing device can read data of a preset length from the data source based on the address offset and use it as a data packet. Refer to FIG. 5 for more descriptions about the data of the preset length and the data packets, and details are not repeated here.

Step 760, determine whether the sum of the data lengths in all the read data packets satisfies the preset condition, if so, stop data reading, otherwise, determine the start reading of the next data packet based on the address offset address and read the next packet.

In some embodiments, the FPGA processing apparatus needs to judge the sum of the lengths of all the data currently read after each completion of reading the data of one data packet, specifically to judge the length of all the data packets that have been read. Whether the sum of the data lengths satisfies the preset condition, if so, stop data reading and enter step 770, otherwise, determine the starting read address of the next data packet based on the address offset and read the next data packet, And perform step 760 again.

Step 770: After the data reading is completed, playback and spectrum analysis are performed on the read data to obtain an analysis result.

In some embodiments, the FPGA processing device can play back the read data, and perform spectrum analysis during the playback to obtain the analysis result, and send the analysis result to the upper computer, and the upper computer further displays the corresponding graphics , so that users can intuitively understand the corresponding information.

The specific operations performed by the FPGA processing device will be described below in conjunction with different playback modes:

When the playback mode is the constant-speed spectrum analysis mode, the FPGA processing device is configured to perform the following operations:

Acquire the storage parameters of the digital signal based on the external connection module, where the storage parameters include a storage starting point and a storage length;

Based on the storage parameter, the digital signal is stored by the bandwidth matching and buffering module;

Judging whether the length of the stored digital signal satisfies the storage length;

In response, an interrupt signal based on the external connection module is sent to the radio monitoring system for a storage completion signal. For example, after the storage length meets the set requirement, the FPGA processing device generates a storage completion signal and notifies the upper computer in an interrupt mode.

Wherein, the above-mentioned storage process can be performed multiple times, and each time the storage parameters are stored, there is a corresponding file in the radio monitoring system to record the storage parameters.

When performing spectrum analysis in the playback state, the data source selection module acquires the data source for playback based on the external connection module, and starts the playback control process. For example, the data source selection module selects the data source to be played back through the host computer based on the user's selection, and starts the playback control process.

The spectrum analysis playback control module reads data from the data source with the length of one packet of FFT as the amount of continuous readback data.

Wherein, during data reading, after the digital signal of each packet of FFT length is read, the spectrum analysis playback control module determines whether the read total amount and the storage boundary meet preset conditions.

In response to not meeting the preset condition, the spectrum analysis playback control module starts continuous reading of the digital signal of the FFT length of the next packet, and the start reading address of the digital signal of the FFT length of the next packet is adjacent to it. The starting read address of the digital signal of the last packet of FFT length is separated from the data amount of one packet of FFT length; that is, the address offset is the length of one packet of FFT.

Among them, the total amount of readback data satisfies the following formula:

total_num=n*fft_length

Among them, total_num is the total amount of read-back data, n is the number of packets of data of the FFT length that are completely read, and fft_length is the number of processing points of the FFT unit, that is, the length of one packet of FFT. Figure 8 shows a schematic diagram of reading data in the constant-speed spectrum analysis mode.

The digital signal processing module replaces the real-time sampling data with the playback data read by the spectrum analysis playback control module, and sequentially performs digital filtering, fast Fourier transform, and detection processing on the playback data based on the digital filtering unit, the FFT unit, and the detection unit.

Based on the external connection module returning the playback data to the radio monitoring system to perform spectrum analysis to obtain analysis results.

When the playback mode is the fast spectrum analysis mode, the FPGA processing device is configured to perform the following operations:

The storage parameters of the digital signal are acquired based on the external connection module, where the storage parameters include a storage start point and a storage length.

Based on the storage parameter, the digital signal is stored by the bandwidth matching and buffering module;

It is judged whether the length of the stored digital signal satisfies the storage length.

In response, an interrupt signal based on the external connection module is sent to the radio monitoring system for a storage completion signal.

Wherein, the above-mentioned storage process can be performed multiple times, and each time the storage parameters are stored, there is a corresponding file in the radio monitoring system to record the storage parameters.

When the spectrum analysis is performed in the playback state, the data source selection module acquires the playback data source and the fast coefficient based on the external connection module, and starts the playback control process. In some embodiments, the fast coefficients may be represented by fetch interval values.

The spectrum analysis playback control module reads data from the data source with the length of one packet of FFT as the amount of continuous readback data.

Wherein, during data reading, after the digital signal of each packet of FFT length is read, the spectrum analysis playback control module determines whether the read total amount and the storage boundary meet preset conditions.

In response to not meeting the preset condition, the spectrum analysis playback control module starts continuous reading of the digital signal of the FFT length of the next packet, and the start reading address of the digital signal of the FFT length of the next packet is adjacent to it. The data volume corresponding to the fast coefficient at the starting read address of the digital signal with the FFT length of the last packet.

Among them, the total amount of readback data satisfies the following formula:

total_num=n*fft_length (1)

total_addr_offset=(n-1)*read_gap+fft_length (2)

Among them, in formula 1, total_num is the total amount of read back data, n is the number of packets of data with the FFT length read completely, and fft_length is the number of processing points of the FFT unit;

In Equation 2, total_addr_offset is the total address offset, read_gap is the fast coefficient, and read_gap is greater than fft_length; Figure 9 is a schematic diagram of reading data in the fast spectrum analysis mode.

The digital signal processing module replaces the real-time sampling data with the playback data read by the spectrum analysis playback control module, and sequentially performs digital filtering, fast Fourier transform, and detection processing on the playback data based on the digital filtering unit, the FFT unit, and the detection unit.

Based on the external connection module returning the playback data to the radio monitoring system to perform spectrum analysis to obtain analysis results.

When the playback mode is the slow spectrum analysis mode, the FPGA processing device is configured to perform the following operations:

The storage parameters of the digital signal are acquired based on the external connection module, where the storage parameters include a storage start point and a storage length.

Based on the storage parameter, the digital signal is stored by the bandwidth matching and buffering module;

It is judged whether the length of the stored digital signal satisfies the storage length.

In response, an interrupt signal based on the external connection module is sent to the radio monitoring system for a storage completion signal.

Wherein, the above-mentioned storage process can be performed multiple times, and each time the storage parameters are stored, there is a corresponding file in the radio monitoring system to record the storage parameters.

When the spectrum analysis is performed in the playback state, the data source selection module acquires the playback data source and the fast coefficient based on the external connection module, and starts the playback control process.

The spectrum analysis playback control module reads data from the data source with the length of one packet of FFT as the amount of continuous readback data.

Wherein, during data reading, after the digital signal of each packet of FFT length is read, the spectrum analysis playback control module determines whether the read total amount and the storage boundary meet preset conditions.

In response to not meeting the preset condition, the spectrum analysis playback control module starts continuous reading of the digital signal of the FFT length of the next packet, and the start reading address of the digital signal of the FFT length of the next packet is adjacent to it. The data volume corresponding to the fast coefficient at the starting read address of the digital signal with the FFT length of the last packet.

Among them, the total amount of readback data satisfies the following formula:

total_num=n*fft_length (3)

total_addr_offset=(n-1)*read_gap+fft_length (4)

Wherein, in Equation 3, total_num is the total amount of read-back data, n is the number of packets of data of the FFT length that are completely read, and fft_length is the number of processing points of the FFT unit.

In Equation 4, total_addr_offset is the total address offset, read_gap is the fast coefficient, and read_gap is less than fft_length. Figure 10 shows a schematic diagram of reading data in slow spectrum analysis mode.

The digital signal processing module replaces the real-time sampling data with the playback data read by the spectrum analysis playback control module, and sequentially performs digital filtering, fast Fourier transform, and detection processing on the playback data based on the digital filtering unit, the FFT unit, and the detection unit.

Based on the external connection module returning the playback data to the radio monitoring system to perform spectrum analysis to obtain analysis results.

In some embodiments of the present invention, the frequency spectrum analysis function can be switched by design. The normal-speed spectrum analysis is used in common application scenarios, and the fast and slow-speed spectrum analysis is used in application scenarios with special requirements, which can improve the analysis performance of the system. Moreover, the fast and slow coefficients support a wide range, the fastest can support dozens of times the spectrum analysis speed, and the slowest can support point-by-point spectrum scanning analysis, and the speed between them can be set arbitrarily. Users can freely switch between technical solutions of rapid retrieval and detailed analysis according to actual needs.

The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is merely an example, and does not constitute a limitation of the present specification. Although not explicitly described herein, various modifications, improvements, and corrections to this specification may occur to those skilled in the art. Such modifications, improvements, and corrections are suggested in this specification, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of this specification.

Meanwhile, the present specification uses specific words to describe the embodiments of the present specification. Such as "one embodiment," "an embodiment," and/or "some embodiments" means a certain feature, structure, or characteristic associated with at least one embodiment of this specification. Therefore, it should be emphasized and noted that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places in this specification are not necessarily referring to the same embodiment . Furthermore, certain features, structures or characteristics of the one or more embodiments of this specification may be combined as appropriate.

Furthermore, unless explicitly stated in the claims, the order of processing elements and sequences described in this specification, the use of alphanumerics, or the use of other names is not intended to limit the order of the processes and methods of this specification. While the foregoing disclosure discusses by way of various examples some embodiments of the invention that are presently believed to be useful, it is to be understood that such details are for purposes of illustration only and that the appended claims are not limited to the disclosed embodiments, but rather The requirements are intended to cover all modifications and equivalent combinations falling within the spirit and scope of the embodiments of this specification. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described systems on existing servers or mobile devices.

Similarly, it should be noted that, in order to simplify the expressions disclosed in this specification and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of this specification, various features may sometimes be combined into one embodiment, in the drawings or descriptions thereof. However, this method of disclosure does not imply that the subject matter of the description requires more features than are recited in the claims. Indeed, there are fewer features of an embodiment than all of the features of a single embodiment disclosed above.

Some examples use numbers to describe quantities of ingredients and attributes, it should be understood that such numbers used to describe the examples, in some examples, use the modifiers "about", "approximately" or "substantially" to retouch. Unless stated otherwise, "about", "approximately" or "substantially" means that a variation of ±20% is allowed for the stated number. Accordingly, in some embodiments, the numerical parameters set forth in the specification and claims are approximations that can vary depending upon the desired characteristics of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and use a general digit reservation method. Notwithstanding that the numerical fields and parameters used in some embodiments of this specification to identify the breadth of their ranges are approximations, in specific embodiments such numerical values are set as precisely as practicable.

For each patent, patent application, patent application publication, and other material, such as article, book, specification, publication, document, etc., cited in this specification, the entire contents of which are hereby incorporated by reference into this specification are hereby incorporated by reference. Application history documents that are inconsistent with or conflict with the contents of this specification are excluded, as are documents (currently or hereafter appended to this specification) limiting the broadest scope of the claims of this specification. It should be noted that, if there is any inconsistency or conflict between the descriptions, definitions and/or use of terms in the accompanying materials of this specification and the contents of this specification, the descriptions, definitions and/or use of terms in this specification shall prevail .

Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations are also possible within the scope of this specification. Accordingly, by way of example and not limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to those expressly introduced and described in this specification.

Claims (10)

1. A radio monitoring system is characterized by comprising a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip and an upper computer;

the radio frequency front end is in communication connection with the AD data acquisition module, and is used for receiving a signal to be analyzed through an antenna and performing at least one of amplification, filtering and frequency mixing on the signal to be analyzed to obtain an intermediate frequency signal;

the AD data acquisition module is in communication connection with the FPGA processor and is used for converting the intermediate frequency signal into IQ data and uploading the IQ data to the FPGA processor;

the FPGA processor is in communication connection with the DDR3 storage chip and the upper computer respectively, and is used for storing the IQ data, playing back the IQ data based on a corresponding playback mode, performing frequency spectrum analysis on the IQ data in the playback process, obtaining an analysis result and uploading the analysis result to the upper computer; the playback mode comprises at least one of a normal-speed spectrum analysis mode, a fast-speed spectrum analysis mode and a slow-speed spectrum analysis mode;

the DDR3 storage chip is used for storing the IQ data received by the FPGA processor, and a data source during playback of the FPGA processor comprises the IQ data stored by the DDR3 storage chip;

the upper computer is used for operating the human-computer interaction software, acquiring a user instruction based on the operation of the human-computer interaction software, issuing the user instruction to the FPGA processor, and displaying a frequency spectrum waveform based on the analysis result.

2. The radio monitoring system according to claim 1, wherein the IQ data are sequentially stored with reference to an acquisition timing sequence within the DDR3 memory chip;

the FPGA processor, in implementing the spectral analysis of the IQ data in the playback, is further configured to:

acquiring the playback mode;

reading a plurality of data packets according to the storage sequence of the IQ data in the DDR3 storage chip and referring to corresponding reading rules based on the playback mode; the number of points and/or the length of the IQ data contained in each data packet in the plurality of data packets are the same, and the sum of the lengths of all the IQ data in the plurality of data packets does not exceed a preset storage length; the number of points of the IQ data included in each of the data packets is 2 ⁿ ；

And playing back the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the playback.

3. A radio monitoring system according to claim 2, wherein the reading rules include a fetch interval value;

the obtaining the playback mode further comprises obtaining the fetch interval value;

the fetch interval value may be based on a length value or a point value representation of the IQ data;

the value of the access interval represents the length value or the point value of the IQ data at the interval between the first IQ data in two adjacent data packets.

4. A radio monitoring system according to claim 3,

when the playback mode is a constant-speed spectrum analysis mode, the fetch interval value is equal to a length value or a point value of the IQ data contained in one data packet;

when the playback mode is a fast spectrum analysis mode, the fetch interval value is greater than a length value or a point value of the IQ data contained in one data packet;

when the playback mode is a slow spectrum analysis mode, the fetch interval value is smaller than a length value or a point value of the IQ data included in one data packet.

5. A radio monitoring system according to claim 3, wherein the fetch interval value is determined based on a first predictive model, the first predictive model being a machine learning model, the first predictive model being configured to determine the fetch interval value based on at least one of data acquisition rate, transmission delay, check error rate, noise rate, size and number of MTUs.

6. The radio monitoring system according to claim 2, wherein the predetermined storage length does not exceed a total length of the IQ data that can be stored in the DDR3 memory chip.

7. A radio monitoring system according to claim 6, wherein the predetermined storage length is determined based on a second prediction model, the first prediction model is a machine learning model, and the first prediction model is configured to determine the predetermined storage length based on at least one of data characteristics of the IQ data, the fetch interval value, the number of points of the IQ data included in one of the data packets, and characteristics of the AD data acquisition module.

8. A radio monitoring method implemented by an FPGA processor in a radio monitoring system according to any one of claims 1-7, the radio monitoring method comprising:

receiving IQ data uploaded by the AD data acquisition module;

storing the IQ data and sending the IQ data to the DDR3 storage chip;

acquiring a playback mode and a reading rule based on the upper computer;

reading a plurality of data packets from the DDR3 memory chip according to the playback mode and corresponding reading rules;

replaying the IQ data in the obtained data packets, and performing spectrum analysis on the IQ data in the replaying process to obtain an analysis result;

and uploading the analysis result to the upper computer.

9. A computer-readable storage medium storing computer instructions which, when read by a computer, cause the computer to perform the radio monitoring method of claim 8.

10. A radio monitoring device, the device comprising a processor and a memory; the memory is configured to store instructions that, when executed by the processor, cause the apparatus to perform operations corresponding to the radio monitoring method of claim 8.

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