CN114900883B

CN114900883B - Method and device for processing candidate synchronization signal blocks

Info

Publication number: CN114900883B
Application number: CN202210590820.5A
Authority: CN
Inventors: 周化雨; 潘振岗
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2019-12-12
Filing date: 2019-12-12
Publication date: 2025-05-30
Anticipated expiration: 2039-12-12
Also published as: CN114900883A; CN111130716A; WO2021114732A1; CN111130716B

Abstract

The embodiment of the invention discloses a method and a device for processing candidate synchronous signal blocks, wherein the method comprises the steps of determining candidate synchronous signal block indexes, wherein the candidate synchronous signal block indexes are from 0 to N-1, and N is 4, 8, 10, 16, 20, 32 or 40. By implementing the embodiment of the invention, the coverage performance of the candidate synchronous signal blocks is improved.

Description

Candidate synchronous signal block processing method and device

Technical Field

The invention relates to the technical field of communication, in particular to a method and a device for processing candidate synchronous signal blocks.

Background

In a wireless communication system, a User Equipment (UE) may implement time-frequency synchronization with a Base Station (BS) through a candidate synchronization signal block. The synchronization signal Block (Synchronization Signal/PBCH Block, SS/PBCH Block) or candidate synchronization signal Block (CANDIDATE SS/PBCH Block) may include a primary synchronization signal (Primary Synchronization Signal, PSS), a secondary synchronization signal (Secondary Synchronization Signal, SSs) and a physical broadcast channel (Physical Broadcast Channel, PBCH).

In a scenario supporting low complexity terminal access, such as NR-Light (NR Light access), the terminal may have only one receive antenna. At this time, the reception performance of the terminal may be reduced, resulting in a lower coverage performance of the candidate sync signal block.

Disclosure of Invention

The embodiment of the invention discloses a processing method and a processing device for candidate synchronous signal blocks, which are beneficial to improving the coverage performance of the candidate synchronous signal blocks.

In a first aspect, an embodiment of the present invention discloses a method for processing a candidate synchronization signal block, which may include determining a candidate synchronization signal block index, where the candidate synchronization signal block index ranges from 0 to N-1, and N is 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the specific implementation of determining the candidate synchronization signal block index may be to determine the candidate synchronization signal block index according to a PBCH-DMRS sequence and/or a PBCH load.

In one implementation, where the subcarrier spacing of the candidate synchronization signal block is 15kHz, the aforementioned N may be 4, 8, 10, 16, or 20.

In one implementation, a specific implementation of determining the candidate synchronization signal block index may be to determine 2 or 3 LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, a specific implementation of determining the candidate sync signal block index may be to determine 1,2, or 3 MSB bits of the candidate sync signal block index according to the load of the PBCH.

In one implementation, the specific implementation of determining 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH may be that if N is 10,1 MSB bit of the candidate synchronization signal block index is determined according to the load of the PBCH, if N is 16,1 MSB bit of the candidate synchronization signal block index is determined according to the load of the PBCH, and if N is 20, 2 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, N may be 4, 8, 10, 16, 20, 32, or 40 with a subcarrier spacing of 30kHz for the candidate synchronization signal block.

In one implementation, the specific implementation of determining 1,2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH may be that if N is 10 or 16, 1 MSB bit of the candidate synchronization signal block index is determined according to the load of the PBCH, if N is 20, 2 MSB bits of the candidate synchronization signal block index is determined according to the load of the PBCH, if N is 32, 2 MSB bits of the candidate synchronization signal block index is determined according to the load of the PBCH, and if N is 40, 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, the method may further include determining a number of repetitions of a candidate synchronization signal block set within a transmission window, the candidate synchronization signal block set may include a plurality of candidate synchronization signal blocks.

In one implementation, the specific implementation of determining the number of repetitions of the candidate synchronization signal block set within the transmission window may be that the number of repetitions of the candidate synchronization signal block set within the transmission window is determined according to a duration of the transmission window.

In one implementation, the specific implementation of determining the repetition number of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window may be that the number of the candidate synchronization signal blocks transmitted in the transmission window is determined according to the duration of the transmission window, and the repetition number of the candidate synchronization signal block group in the transmission window is determined according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the method may further include receiving first signaling sent by the network device, the first signaling may be used to indicate a number of repetitions of the candidate set of synchronization signal blocks within the transmission window.

In one implementation, the method may further include determining a number of repetitions of a set of a plurality of candidate sync signal block groups, which may include a plurality of candidate sync signal blocks, within a transmission window.

In one implementation, the specific implementation of determining the number of repetitions of the set of candidate sync signal blocks within the transmission window may be that the number of candidate sync signal blocks transmitted within the transmission window is determined according to a duration of the transmission window, and the number of repetitions of the set within the transmission window is determined according to the number of candidate sync signal blocks included in the set of candidate sync signal blocks and the number of candidate sync signal blocks transmitted within the transmission window.

In one implementation, an extended index of a candidate synchronization signal block is determined, and a pseudo co-sited relationship or synchronization signal block index of the candidate synchronization signal block is determined according to the extended index of the candidate synchronization signal block.

In one implementation manner, the specific implementation manner of determining the expansion index of the candidate synchronization signal block may be that the expansion index of the candidate synchronization signal block is determined to be i=x1×i1+i2 according to the duration of the expansion transmission window, the duration of the transmission window and the period of the transmission window, where X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the expansion transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In one implementation manner, the specific implementation manner of determining the expansion index of the candidate synchronization signal block may be that according to the duration of the expansion transmission window and the period of the half frame or frame received by the candidate synchronization signal block, the expansion index of the candidate synchronization signal block is determined to be i=x2×i3+i4, where X2 is the number or maximum number of candidate synchronization signal blocks in one half frame or one frame, i3 is the index of the period of the half frame or frame received by the candidate synchronization signal block in the duration of the expansion transmission window, and i4 is the index of the candidate synchronization signal block.

In one implementation, determining the pseudo co-sited relationship of the candidate synchronization signal blocks according to the extended index of the candidate synchronization signal blocks may be performed by if a plurality of candidate synchronization signal blocks have the same (a mod Q) value, where a is the extended index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo).

In one implementation, determining the synchronization signal block index of the candidate synchronization signal block according to the expansion index of the candidate synchronization signal block may be performed by determining the synchronization signal block index of the candidate synchronization signal block to be (a mod Q), where a is the expansion index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo).

In a second aspect, an embodiment of the present invention discloses a processing apparatus for a candidate synchronization signal block, where the apparatus includes a unit configured to perform the method described in the first aspect.

In a third aspect, an embodiment of the present invention discloses a terminal, which includes a memory for storing a computer program, the computer program including program instructions, and a processor configured to invoke the program instructions to perform the method according to the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer program instructions for use by a processing apparatus for candidate synchronization signal blocks described in the third aspect, including a program for executing the method of the first aspect.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart of a method for processing a candidate synchronization signal block according to an embodiment of the present invention;

fig. 2 is a flowchart of another method for processing a candidate synchronization signal block according to an embodiment of the present invention;

Fig. 3 is a schematic structural diagram of a processing apparatus for candidate synchronization signal blocks according to an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for processing a candidate synchronization signal block according to an embodiment of the invention. The method is applied to a terminal, and specifically, as shown in fig. 1, the method for processing the candidate synchronization signal block according to the embodiment of the invention may include, but is not limited to, the following steps:

S101, the terminal (also called User Equipment, UE) determines candidate synchronization signal block indexes, where the candidate synchronization signal block indexes range from 0 to N-1, and N is 4, 8, 10, 16, 20, 32 or 40. The candidate sync signal block index may refer to an index (or number) of the candidate sync signal blocks within one field (HALF FRAME, or half radio frame) or one frame (frame, or radio frame), that is, the candidate sync signal blocks have N numbers within one field or one frame. In general, a frame is also called a "radio frame" and has a duration of 10 ms, and a field is also called a "half radio frame" and has a duration of 5 ms.

In the embodiment of the present invention, each candidate synchronization signal block has a predetermined or candidate time domain position, which may also be referred to as a time domain position of the candidate synchronization signal block. The terminal detects candidate sync signal blocks and determines candidate sync signal block indexes.

In an embodiment of the present invention, a field or a frame may include N candidate synchronization signal blocks, which may be sequentially numbered in order from 0 to N-1, or candidate synchronization signal block indexes from 0 to N-1. That is, the base station may transmit at most N candidate sync signal blocks in one field or one frame. Where N may be 4, 8, 10, 16, 20, 32, 40 or other values.

In a scenario supporting low complexity terminal access, such as a fifth Generation mobile communication technology (5 th-Generation, 5G), a New Radio (NR) Light access (NR-Light), the terminal may have only one receiving antenna. At this time, the reception performance of the terminal may be reduced, resulting in a lower coverage performance of the candidate sync signal block. Compared with the prior art, at most 4 or 8 candidate synchronous signal blocks can be sent in one field or one frame, and more candidate synchronous signal blocks can be sent in one field or one frame by adopting the embodiment of the invention. Therefore, by implementing the embodiment of the invention, the terminal is facilitated to receive more candidate synchronous signal blocks, and the coverage performance of the candidate synchronous signal blocks is improved.

In embodiments of the present invention, a terminal may refer to various forms of user equipment, access terminals, subscriber units, subscriber stations, mobile Stations (MS), remote stations, remote terminals, mobile devices, user terminals, terminal devices (terminal equipment), wireless communication devices, user agents, or user equipment. The terminal device may also be a cellular phone, a cordless phone, a session initiation protocol (Session Initiation Protocol, SIP) phone, a wireless local loop (Wireless Local Loop, WLL) station, a Personal digital assistant (Personal DIGITAL ASSISTANT, PDA), a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G network, or a terminal device in a future evolved public land mobile network (Public Land Mobile Network, PLMN), etc., which the embodiments of the present invention are not limited to.

The network device may be an entity on the network side for transmitting or receiving signals, e.g. the network device may be an access network device such as a base station. An apparatus for providing a base station function in a 2G network includes a base transceiver station (Base transceiver station, abbreviated BTS) and a base station controller (Base Station Controller, abbreviated BSC). An apparatus for providing a base station function in a 3G network includes a node B (NodeB) and a radio network controller (Radio Network Controller, RNC for short). The apparatus for providing a base station function in a 4G network includes an Evolved NodeB (eNB for short). In a wireless local area network (Wireless Local Area Network, WLAN for short), a device providing a base station function is an Access Point (AP for short). The apparatus for providing a base station function in the 5G NR includes a node B (gNB) that continues to evolve, and the base station in the embodiment of the present invention may also refer to an apparatus for providing a base station function in a new communication system in the future, and so on.

It should be noted that, the technical solution provided by the embodiment of the present invention may be applicable to 3G, 4G or 5G communication systems, and may also be applicable to various communication systems that evolve subsequently. It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B, and that three cases, a alone, a and B together, and B alone, may exist. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship. The term "plurality" as used in the embodiments of the present invention means two or more.

In one implementation, the terminal may also determine a number of repetitions of a candidate sync signal block group within the transmission window, the candidate sync signal block group including a plurality of candidate sync signal blocks. The number of candidate sync signal blocks included in each candidate sync signal block may be the same. In this way, the terminal can determine the number of repetitions of the candidate sync signal block group, thereby performing a receiver combining algorithm to enhance the terminal reception performance. The receiver combining algorithm includes the receiver accumulating or soft combining the detected values of the signals or channels in the plurality of candidate synchronous signal blocks, and detecting or demodulating or decoding the combined values to improve the receiving performance. Typically, a candidate set of synchronization signal blocks consists of non-Co-sited (non Quasi Co-Located, non-QCL) or synchronization signal blocks using different beams. For example, in some scenarios, if multiple synchronization signal blocks have the same average gain (AVERAGE GAIN), QCL-type a properties, and QCL-TypeD properties, then the multiple synchronization signal blocks are co-sited, otherwise the multiple synchronization signal blocks are non-co-sited. It should be noted that the above definition of the pseudo co-sited is only for example, and does not limit the embodiments of the present invention. In other possible implementations, the proposed co-site may be defined in other ways.

In general, the transmission window may be a time window. The transmission window may be a discovery burst transmission window (Discovery Burst Transmission Window), a discovery signal transmission window (Discovery Signal Transmission Window), a candidate sync block transmission window (SS/PBCH Block Transmission Window), or other windows, which are not limited by the embodiments of the present invention. In general, the transmission window has a property of being a duration (or duration) indicating the length of time of the window. The duration of the transmission window may be provided by the higher layer parameters DiscoveryBurst-WindowLength-r 16. When the subcarrier spacing of the candidate synchronization signal block is 15kHz and N is 8 or 10, the duration of the transmission window may be 5 milliseconds at maximum. When the subcarrier spacing of the candidate synchronization signal block is 15kHz and N is 16 or 20, the duration of the transmission window may be 10ms at maximum. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 8 or 10, the duration of the transmission window may be 2.5 milliseconds at maximum. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 16 or 20, the duration of the transmission window may be 5 milliseconds at maximum. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 32 or 40, the duration of the transmission window may be 10ms at maximum. Generally, the duration of the transmission window determines the number or maximum number of candidate sync signal blocks within the transmission window given the subcarrier spacing of the candidate sync signal blocks. In general, the transmission window also has a period in nature, indicating that the window occurs with a certain period. The period of the transmission window may be provided by the higher layer parameters ssb-periodicityServingCell. The period of the transmission window may be the period of the field or frame received by the candidate sync block (periodicity of THE HALF FRAMES for reception of the SS/PBCH blocks, provided by the higher layer parameters ssb-periodicityServingCell), or one period of the field or frame received by the candidate sync block, which is independent of the higher layer configuration.

The terminal may determine the number of candidate sync signal blocks within the transmission window based on the duration (or duration) of the transmission window. That is, the duration of the transmission window has a correspondence with the number of candidate sync signal blocks transmitted within the transmission window. For example, when the subcarrier spacing of the candidate sync signal blocks is 30kHz, if the duration of the transmission window is 5ms, the number of candidate sync signal blocks in the transmission window is determined to be 20, if the duration of the transmission window is 4ms, the number of candidate sync signal blocks in the transmission window is determined to be 16, if the duration of the transmission window is 3ms, the number of candidate sync signal blocks in the transmission window is determined to be 12, if the duration of the transmission window is 2ms, the number of candidate sync signal blocks in the transmission window is determined to be 8, if the duration of the transmission window is 1ms, the number of candidate sync signal blocks in the transmission window is determined to be 4, and if the duration of the transmission window is 0.5ms, the number of candidate sync signal blocks in the transmission window is determined to be 2. For another example, when the subcarrier spacing of the candidate sync signal blocks is 15kHz, if the duration of the transmission window is 5ms, the number of candidate sync signal blocks in the transmission window is determined to be 10, if the duration of the transmission window is 4ms, the number of candidate sync signal blocks in the transmission window is determined to be 8, if the duration of the transmission window is 3ms, the number of candidate sync signal blocks in the transmission window is determined to be 6, if the duration of the transmission window is 2ms, the number of candidate sync signal blocks in the transmission window is determined to be 4, if the duration of the transmission window is 1ms, the number of candidate sync signal blocks in the transmission window is determined to be 2, and if the duration of the transmission window is 0.5ms, the number of candidate sync signal blocks in the transmission window is determined to be 1.

In one implementation, the specific implementation manner of determining the repetition number of the candidate synchronous signal block group in the transmission window by the terminal may be that the repetition number of the candidate synchronous signal block group in the transmission window is determined according to the duration of the transmission window. Wherein the duration of the transmission window may be provided by a high-level parameter. For example, the higher layer parameter may inform the terminal that the duration of the transmission window is 1ms, and the terminal may determine that the duration of the transmission window is 1ms.

Specifically, the terminal can determine the number of candidate synchronous signal blocks transmitted in the transmission window according to the duration of the transmission window, and determine the repetition times of the candidate synchronous signal block group in the transmission window according to the number of candidate synchronous signal blocks included in the candidate synchronous signal block group and the number of candidate synchronous signal blocks transmitted in the transmission window. In general, the number (M) of candidate sync signal blocks transmitted within the transmission window may refer to the number of candidate sync signal blocks that the terminal can receive at most within the transmission window.

In one implementation, the protocol may specify a number of candidate sync signal blocks (Q1) that the candidate sync signal block group includes. In general, the number of candidate sync signal blocks included in each candidate sync signal block may be the same. The terminal may divide the number of candidate sync signal blocks (M) transmitted within the transmission window by the number of candidate sync signal blocks (Q1) included in the candidate sync signal block group (i.e., M/Q1) as the number of repetitions of the candidate sync signal block group within the transmission window. Alternatively, Q1 may be 1,2, 4 or 8. Optionally, the terminal may acquire third signaling sent by the network device, where the third signaling may be used to indicate Q1. The third signaling may be existing signaling in the protocol, such as signaling indicating a Quasi Co-sited (Quasi Co-Located, QCL) relationship of the candidate synchronization signal block. Alternatively, the third signaling may be existing signaling in the protocol, such as signaling indicating the pseudo co-sited relationship of the candidate synchronization signal block, but the signaling may be redefined to indicate Q1. Alternatively, the third signaling may be a newly defined signaling. For example, when the subcarrier spacing of the candidate synchronization signal block is 30kHz, if the duration of the transmission window is 5ms (m=20), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 10, if the duration of the transmission window is 4ms (m=16), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 8, if the duration of the transmission window is 3ms (m=12), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 6, if the duration of the transmission window is 2ms (m=8), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 4, if the duration of the transmission window is 1ms (m=4), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 2, and if the duration of the transmission window is 0.5ms (m=2), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group within the transmission window is 1. For another example, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 5ms (m=10), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 5, if the duration of the transmission window is 4ms (m=8), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 4, if the duration of the transmission window is 3ms (m=6), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 3, if the duration of the transmission window is 2ms (m=4), q1=2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 2, and if the duration of the transmission window is 1ms (m=2), q1=2. Or the terminal may round up (i.e., ceil (M/Q1)) or down (i.e., floor (M/Q1)) or round down (i.e., round (M/Q1)) the number (M) of candidate sync signal blocks transmitted within the transmission window divided by the number (Q1) of candidate sync signal blocks included in the candidate sync signal block group as the number of repetitions of the candidate sync signal block group within the transmission window.

In one implementation, the terminal receives a first signaling sent by the network device, where the first signaling may be used to indicate a number of repetitions of the candidate synchronization signal block set within the transmission window. I.e. the terminal may determine the number of repetitions of the candidate set of synchronization signal blocks within the transmission window, based on the indication of the first signaling. In this way, the terminal can quickly determine the repetition number of the candidate synchronization signal block group in the transmission window according to the indication content of the first signaling. Wherein the first signaling may be a signaling newly defined by the protocol.

In one implementation, the terminal may also determine a number of repetitions of a set of a plurality of candidate sync signal block groups, the candidate sync signal block groups including a plurality of candidate sync signal blocks, within a transmission window. In general, the number of candidate sync signal block groups included in each set may be the same. Therefore, the terminal determines the repetition number of the set in the transmission window, and further can determine the repetition number of the candidate synchronization signal block group in the transmission window. In this way, the number of repetitions of the terminal candidate synchronization signal block set within the transmission window indicated by additional signaling can be avoided, i.e. a saving of signaling is facilitated.

In one implementation, the specific implementation of determining the number of repetitions of the set of the plurality of candidate synchronization signal block groups in the transmission window by the terminal may be that the number of candidate synchronization signal blocks transmitted in the transmission window is determined according to the duration of the transmission window, and the number of repetitions of the set in the transmission window is determined according to the number of candidate synchronization signal blocks included in the set of the plurality of candidate synchronization signal block groups and the number of candidate synchronization signal blocks transmitted in the transmission window. In general, the number (M) of candidate sync signal blocks transmitted within the transmission window may refer to the number of candidate sync signal blocks that the terminal can receive at most within the transmission window.

In one implementation, the protocol may specify a number (Q2) of candidate sync signal blocks included in a set of multiple candidate sync signal block groups. In general, the number of candidate sync signal blocks included in each set may be the same. The terminal may divide the number of candidate sync signal blocks (M) transmitted within the transmission window by the number of candidate sync signal blocks (Q2) included in the set of a plurality of candidate sync signal block groups (i.e., M/Q2) as the number of repetitions of the set of candidate sync signal block groups within the transmission window. Generally, Q2 is an integer multiple of Q1. For example, when the subcarrier spacing of the candidate synchronization signal block is 30kHz, if the duration of the transmission window is 5ms (m=20), q1=2, q2=4, the terminal may determine that the number of repetitions of the set of the candidate synchronization signal block group in the transmission window is 5, if the duration of the transmission window is 4ms (m=16), q1=2, q2=4, the terminal may determine that the number of repetitions of the set of the candidate synchronization signal block group in the transmission window is 4, if the duration of the transmission window is 3ms (m=12), q1=2, q2=4, the terminal may determine that the number of repetitions of the set of the candidate synchronization signal block group in the transmission window is 3, if the duration of the transmission window is 2ms (m=8), q1=2, q2=4, the terminal may determine that the number of repetitions of the set of the candidate synchronization signal block group in the transmission window is 2, and if the duration of the transmission window is 1 (m=4), q1=2, q2=4, the terminal may determine that the number of repetitions of the set of the candidate synchronization signal block group in the transmission window is 1. For another example, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 4ms (m=8), q1=2, q2=4, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 2, and if the duration of the transmission window is 2ms (m=4), q1=2, q2=4, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 1. Or the terminal may divide the number (M) of candidate sync signal blocks transmitted in the transmission window and the number (Q2) of candidate sync signal blocks included in the set of a plurality of candidate sync signal block groups to obtain the result, which is rounded up (i.e., ceil (M/Q2)) or rounded down (i.e., floor (M/Q2)) or rounded down (i.e., round (M/Q2)) as the number of repetitions of the set of candidate sync signal block groups in the transmission window.

In one implementation, the terminal may also receive second signaling from the network device, which may be used to indicate the location within the set of candidate synchronization signal blocks where the candidate synchronization signal blocks were actually transmitted. I.e. the second signaling may be used to indicate the time-frequency position at which the candidate synchronization signal block was actually transmitted. In this way, the terminal can perform rate configuration (such as physical downlink shared channel (Physical Downlink SHARED CHANNEL, PDSCH) resource mapping), collision processing (such as collision processing of physical downlink control channel (Physical Downlink Control Channel, PDCCH) and candidate synchronization signal blocks) or other corresponding processing on the position where the candidate synchronization signal blocks are actually transmitted, which is beneficial to improving the probability of successfully receiving the candidate synchronization signal blocks at the position where the candidate synchronization signal blocks are actually transmitted. Wherein the second signaling may be existing signaling in the protocol, which may be redefined as a position for indicating the actual transmission candidate synchronization signal block. Alternatively, the second signaling may be newly defined signaling.

Further, the terminal may determine an extended index of the candidate sync signal block and determine a quasi co-sited relationship of the candidate sync signal block or a sync signal block index (SS/PBCH block index). In general, if multiple candidate synchronization signal blocks are Co-sited (Quasi Co-Located, QCL), then the multiple candidate synchronization signal blocks are sent out by the same beam (beam). In general, multiple candidate sync signal blocks are co-sited, and then they have the same sync signal block index. The synchronization signal block index may be regarded as a beam index. The synchronization signal block may be indexed byGiven, whereinFor the PBCH-DMRS sequence index,Mod represents a modulo or remainder operation (modulo) for the number of candidate sync blocks within the set of candidate sync blocks, or the sync block index may be defined byGiven, whereinFor the candidate sync signal block index,Mod represents a modulo or remainder operation (modulo) for the number of sync signal blocks within the set of candidate sync signal blocks. In general terms, the process is carried out,May be given by the higher layer parameter ssbPositionQCL-Relationship-r 16. After the terminal obtains the synchronization signal block index or the beam index, the terminal can further obtain other channels/signals corresponding to the synchronization signal block index or the beam index, such as corresponding PDCCH monitoring time, physical Random access channel (Physical Random ACCESS CHANNEL, PRACH) sending time, etc., to improve system coverage and flexibility, and can also combine measurement results for the same synchronization signal block or beam, to improve measurement performance.

In one implementation, an extended index (or numbering) of candidate synchronization signal blocks is determined, and a co-sited relationship or synchronization signal block index of the candidate synchronization signal blocks is determined from the extended index of the candidate synchronization signal blocks. In general, if multiple candidate sync signal blocks are co-sited, then the multiple candidate sync signal blocks are sent out by the same beam (beam).

In one implementation manner, the specific implementation manner of determining the expansion index of the candidate synchronization signal block may be that the expansion index of the candidate synchronization signal block is determined to be i=x1×i1+i2 according to the duration (or called duration) of the expansion transmission window, the duration of the transmission window and the period of the transmission window, wherein X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the expansion transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block. The duration of the extended transmission window may be a duration or period or duration of a higher layer configuration. In general, the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, or a positive integer multiple of the period of the half frame (periodicity of THE HALF FRAMES for reception of the SS/PBCH blocks) that the candidate sync signal block receives. Since the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, there may be multiple transmission windows within the extended transmission window, and the index of the transmission window within the duration of the extended transmission window (i.e., i 1) may be derived from the duration of the extended transmission window and the period of the transmission window together.

In one implementation manner, the specific implementation manner of determining the expansion index of the candidate synchronization signal block may be that according to the duration of the expansion transmission window and the period of the half frame or frame received by the candidate synchronization signal block, the expansion index of the candidate synchronization signal block is determined to be i=x2×i3+i4, where X2 is the number or maximum number of candidate synchronization signal blocks in one half frame or one frame, i3 is the index of the period of the half frame or frame received by the candidate synchronization signal block in the duration of the expansion transmission window, and i4 is the index of the candidate synchronization signal block. The duration of the extended transmission window may be a duration or period or duration of a higher layer configuration. In general, the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, or a positive integer multiple of the period of the half frame (periodicity of THE HALF FRAMES for reception of the SS/PBCH blocks) that the candidate sync signal block receives.

In one implementation, determining the pseudo co-sited relationship of the candidate synchronization signal blocks according to the extended index of the candidate synchronization signal blocks may be performed by if a plurality of candidate synchronization signal blocks have the same (a mod Q) value, where a is the extended index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate sync signal blocks within the candidate sync signal block group. Q may be given by the higher layer parameter ssbPositionQCL-relation-r 16, i.e. Q is

In one implementation, determining the synchronization signal block index of the candidate synchronization signal block according to the expansion index of the candidate synchronization signal block may be performed by determining the synchronization signal block index of the candidate synchronization signal block to be (a mod Q), where a is the expansion index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate sync signal blocks within the candidate sync signal block group. Q may be given by the higher layer parameter ssbPositionQCL-relation-r 16, i.e. Q is

By expanding the transmission window, the candidate sync signal block index can be expanded, i.e., the expanded index of the candidate sync signal block can be obtained. That is, by expanding the transmission window, the candidate synchronization signal block index can be expanded in the time domain, which corresponds to the time required for one round of multi-beam transmission of the candidate synchronization signal block, such as from 5 milliseconds to 20 milliseconds. Thus, the downlink transmission is dispersed in a longer period of time, and the uplink and downlink proportion of the system is optimized. For example, when a subcarrier interval of a candidate synchronization signal block is 30kHz, if a duration of a transmission window is 5ms, a period of the transmission window is 10ms, an extension index of the candidate synchronization signal block is determined to be i=20×i1+i2, where i1 may be 0 or 1, i2 may be a certain integer from 0 to 19, if a duration of the transmission window is 4ms, a period of the transmission window is 10ms, a duration of the extension transmission window is 20ms, it is determined that an extension index of the candidate synchronization signal block is i=16×i1+i2, where i1 may be 0 or 1, i2 may be a certain integer from 0 to 15, if a duration of the transmission window is 3ms, a period of the extension transmission window is 10ms, it is determined that an extension index of the candidate synchronization signal block is i=12×i1+i2, where i1 may be 0 or 1, i2 may be an integer from 0 to 11 ms, and if a period of the extension index of the extension window is 0+2 is 1, and if a certain integer from 0.2 is 0, i 1+2 may be an extension window is 0, and if a period of the extension window is 0+2, and if a period of the extension index of the extension window is 0+1+2 is 0, it is 0.1, and if a period of the extension window is 0+2 may be determined that a certain integer from 0 to 1, and a period of the extension window is 0+2 may be 0.

For example, when the subcarrier interval of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 5ms, the period of the transmission window is 10ms, the extension index of the candidate synchronization signal block is determined to be i=10×i1+i2, where i1 may be 0 or 1, i2 may be a certain integer from 0 to 9, if the duration of the transmission window is 4ms, the period of the transmission window is 10ms, the duration of the extension transmission window is 20ms, the extension index of the candidate synchronization signal block is determined to be i=8×i1+i2, where i1 may be 0 or 1, i2 may be a certain integer from 0 to 7, if the duration of the transmission window is 3, the period of the transmission window is 10ms, the extension index of the candidate synchronization signal block is determined to be i=6, where i1 may be 0 or 1, i2 may be an integer from 0 to 5ms, and if the duration of the extension index is 1, i1 may be 0, i2 is 0, i1 may be an integer from 0, i2 is 0, and if the duration of the extension index is 1, i2 is 0, i 1+2 is an integer from 0, and if the duration of the extension index is 0, i 1+2 is 0, and the duration of the extension window is 0ms, and the duration of the extension window is 20ms may be determined to be 0, and the duration of the extension window is 0 ms.

By implementing the embodiment of the invention, the terminal is facilitated to receive more candidate synchronous signal blocks, thereby being beneficial to improving the coverage performance of the candidate synchronous signal blocks.

Referring to fig. 2, fig. 2 is a flowchart illustrating another method for processing a candidate synchronization signal block according to an embodiment of the invention. The method is applied to a terminal, and specifically, as shown in fig. 2, the method for processing the candidate synchronization signal block according to the embodiment of the invention may include, but is not limited to, the following steps:

S201, the terminal determines candidate synchronous signal block indexes (or called numbers) according to the PBCH-DMRS sequence and/or the load of the PBCH, wherein the candidate synchronous signal block indexes are from 0 to N-1, and N is 4, 8, 10, 16, 20, 32 or 40. The candidate sync signal block index may refer to an index of a candidate sync signal block within one half frame or one frame.

Specifically, when the terminal is initially accessed, the terminal may determine one or more candidate synchronization signal block indexes of N candidate synchronization signal blocks in one field or one frame according to a Physical Broadcast Channel (PBCH) -Demodulation reference signal (Demodulation REFERENCE SIGNAL, DMRS) sequence and a PBCH load.

In one implementation, the candidate sync signal block index may have 2 (when N is equal to 4) or 3 (when N is greater than 4) least significant bits (LEAST SIGNIFICANT Bit, LSB) bits, and/or 1,2, or 3 most significant bits (Most Significant Bit, MSB) bits.

In one implementation, the terminal determines the specific implementation mode of the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH, and the method comprises the step of determining 2 (when N is equal to 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, the terminal determines a specific embodiment of the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH, including determining 1,2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH.

In one implementation, the value of N may relate to the subcarrier spacing of the candidate synchronization signal block. The subcarrier spacing of the candidate synchronization signal blocks may be 15kHz, 30kHz, or other values, which are not limited in this embodiment of the invention. Specifically, in the case where the subcarrier spacing of the candidate synchronization signal block is 15kHz, N may be 4, 8, 10, 16 or 20. In case the subcarrier spacing of the candidate synchronization signal block is 30kHz, N may be 4, 8, 10, 16, 20, 32 or 40.

Note that N may refer to the number of candidate sync signal blocks that can be transmitted at most in one radio frame, or N may refer to the number of candidate sync signal blocks that can be transmitted at most in half a radio frame. Specifically, in the case where the subcarrier spacing of the candidate synchronization signal blocks is 15kHz, at most 4 or 8 or 10 candidate synchronization signal blocks can be transmitted in one half radio frame, and at most 16 or 20 candidate synchronization signal blocks can be transmitted in 1 radio frame. In the case where the subcarrier spacing of the candidate synchronization signal blocks is 30kHz, at most 4, 8, 10, 16 or 20 candidate synchronization signal blocks can be transmitted in half a radio frame, and at most 32 or 40 candidate synchronization signal blocks can be transmitted in 1 radio frame.

In one implementation, in the case where the subcarrier spacing of the candidate synchronization signal block is 15kHz, if n=4, that is, a value of 2 bits may represent the candidate synchronization signal block index in half a radio frame, so 2 LSB bits are determined according to the PBCH-DMRS sequence.

In one implementation, if n=8, that is, a value of 3 bits indicates the candidate synchronization signal block index in half a radio frame, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, 3 LSB bits are determined according to the PBCH-DMRS sequence.

In one implementation, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if n=10, that is, a value of 4 bits indicates the candidate synchronization signal block index in half a radio frame, 3 LSB bits are determined according to the PBCH-DMRS sequence, and 1 MSB bit is determined according to the PBCH load. In this case, the terminal can bit the PBCH payload1 MSB bit as a candidate sync signal block index in half a radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 15kHz, if n=16, that is, a value of 4 bits indicates the candidate synchronization signal block index in 1 radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the PBCH load. In this case, the terminal can bit the PBCH payload1 MSB bit as a candidate sync signal block index in1 radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 15kHz, if n=20, that is, a value of 5 bits indicates the candidate synchronization signal block index in 1 radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 2 MSB bits are determined from the PBCH load. In this case, the terminal can bit the PBCH payload 2 MSB bits as candidate sync signal block index in1 radio frame.

In the above manner, the MSB bit of the candidate sync signal block index may be carried by 1 or 2 bits in the PBCH payload.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=4, that is, a value of 2 bits, the candidate synchronization signal block index in half a radio frame can be represented, and thus, 2 LSB bits are determined from the PBCH-DMRS sequence.

If n=8, that is, if the subcarrier spacing of the candidate synchronization signal block is 30kHz, the candidate synchronization signal block index in half a radio frame can be represented by a value of 3 bits, and therefore, 3 LSB bits are determined from the PBCH-DMRS sequence.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=10, that is, a value of 4 bits indicates the candidate synchronization signal block index in half a radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the PBCH load. In this case, the terminal can bit the PBCH payload1 MSB bit as a candidate sync signal block index in half a radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=16, that is, a value of 4 bits indicates the candidate synchronization signal block index in half a radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the PBCH load. In this case, the terminal can bit the PBCH payload1 MSB bit as a candidate sync signal block index in half a radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=20, that is, a value of 5 bits indicates the candidate synchronization signal block index in half a radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 2 MSB bits are determined from the PBCH load. In this case, the terminal can bit the PBCH payload 2 MSB bits as candidate sync signal block index in half a radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=32, that is, a value of 5 bits indicates the candidate synchronization signal block index in 1 radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 2 MSB bits are determined from the PBCH load. In this case, the terminal can bit the PBCH payload 2 MSB bits as candidate sync signal block index in1 radio frame.

When the subcarrier spacing of the candidate synchronization signal block is 30kHz, if n=40, that is, a value of 6 bits indicates the candidate synchronization signal block index in 1 radio frame, 3 LSB bits are determined from the PBCH-DMRS sequence, and 3 MSB bits are determined from the PBCH load. In this case, the terminal can bit the PBCH payload 3 MSB bits as candidate sync signal block index in1 radio frame, or the terminal may load PBCH with bits3 MSB bits as candidate Sync Block index in 1 radio frame, whereinFor the bits indicated for the field.

In the above manner, the MSB bit of the candidate sync signal block index may be carried by 1, 2, or 3 bits in the PBCH payload.

By implementing the embodiment of the invention, the candidate synchronization signal block index can be determined through the PBCH-DMRS sequence and/or the load of the PBCH, namely, the network equipment does not need to indicate the terminal candidate synchronization signal block index through additional information or signaling, thereby being beneficial to reducing the data quantity transmitted in the network.

Further, the terminal may determine an extended index of the candidate sync signal block and determine a quasi co-sited relationship or a sync signal block index (SS/PBCH block index) of the candidate sync signal block. In general, if multiple candidate synchronization signal blocks are co-sited, then the multiple candidate synchronization signal blocks are sent out by the same beam (beam). In general, a plurality of candidate sync signal blocks are co-sited, then the plurality of candidate sync signal blocks have the same sync signal block index. The synchronization signal block index may be regarded as a beam index.

In one implementation, a terminal may determine an extended index (or numbering) of candidate synchronization signal blocks and determine a co-sited relationship or synchronization signal block index of the candidate synchronization signal blocks based on the extended index of the candidate synchronization signal blocks. In general, if multiple candidate synchronization signal blocks are co-sited, then the multiple candidate synchronization signal blocks are sent out by the same beam (beam).

In one implementation, determining the pseudo co-sited relationship of the candidate synchronization signal blocks according to the extended index of the candidate synchronization signal blocks may be performed by if a plurality of candidate synchronization signal blocks have the same (a mod Q) value, where a is the extended index of the candidate synchronization signal blocks and Q is a higher layer parameter. In general, Q may be the number of candidate sync signal blocks within the candidate sync signal block group. Q may be given by the higher layer parameter ssbPositionQCL-relation-r 16, i.e. Q is

In one implementation, the specific implementation of determining the synchronization signal block index of the candidate synchronization signal block according to the expansion index of the candidate synchronization signal block may be that the synchronization signal block index of the candidate synchronization signal block is (a mod Q), where a is the expansion index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate sync signal blocks within the candidate sync signal block group. Q may be given by the higher layer parameter ssbPositionQCL-relation-r 16, i.e. Q is

Referring to fig. 3, fig. 3 is a schematic structural diagram of a processing device of a candidate synchronization signal block according to an embodiment of the present invention, where the processing device of the candidate synchronization signal block may be a terminal or a device (e.g. a chip) with a terminal function. Specifically, as shown in fig. 3, the processing apparatus 30 of the candidate synchronization signal block may include:

A processing module 301, configured to determine a candidate synchronization signal block index, where the candidate synchronization signal block index ranges from 0 to N-1, and N is 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the processing module 301 is configured to determine the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the PBCH payload.

In one implementation, where the subcarrier spacing of the candidate synchronization signal block is 15kHz, the N may be 4, 8, 10, 16, or 20.

In one implementation, the processing module 301 is configured to determine the candidate synchronization signal block index, and may specifically be configured to determine 2 or 3 LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, the processing module 301 is configured to determine 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH when determining the candidate synchronization signal block index.

In one implementation, the processing module 301 is configured to determine 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the PBCH load, and may specifically be configured to determine 1 MSB bit of the candidate synchronization signal block index according to the PBCH load if N is 10, determine 1 MSB bit of the candidate synchronization signal block index according to the PBCH load if N is 16, and determine 2 MSB bits of the candidate synchronization signal block index according to the PBCH load if N is 20.

In one implementation, the processing module 301 is configured to determine 2 (when N is equal to 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, the processing module 301 is configured to determine 1,2 or 3 MSB bits of the candidate synchronization signal block index according to the PBCH load, and may specifically be configured to determine 1 MSB bit of the candidate synchronization signal block index according to the PBCH load if N is 10 or 16, determine 2 MSB bits of the candidate synchronization signal block index according to the PBCH load if N is 20, determine 2 MSB bits of the candidate synchronization signal block index according to the PBCH load if N is 32, and determine 3 MSB bits of the candidate synchronization signal block index according to the PBCH load if N is 40.

In one implementation, the processing module 301 may also be configured to determine a number of repetitions of a candidate synchronization signal block set within a transmission window, where the candidate synchronization signal block set may include a plurality of candidate synchronization signal blocks.

In one implementation, the processing module 301 is configured to determine the number of repetitions of the candidate synchronization signal block group within the transmission window, and may be specifically configured to determine the number of repetitions of the candidate synchronization signal block group within the transmission window according to a duration of the transmission window.

In one implementation, the processing module 301 is configured to determine, according to a duration of a transmission window, a number of repetitions of a candidate synchronization signal block set within the transmission window, where the number of repetitions of the candidate synchronization signal block set within the transmission window is determined according to the duration of the transmission window, and according to a number of candidate synchronization signal blocks included in the candidate synchronization signal block set and a number of candidate synchronization signal blocks transmitted within the transmission window.

In one implementation, the processing device 30 of the candidate synchronization signal block may further include a communication module 302. The communication module 302 may be configured to receive first signaling sent by a network device, where the first signaling may be configured to indicate a number of repetitions of a candidate set of synchronization signal blocks within a transmission window.

In one implementation, the processing module 301 may be further configured to determine a number of repetitions of a set of a plurality of candidate synchronization signal block groups, where the candidate synchronization signal block groups may include a plurality of candidate synchronization signal blocks, within a transmission window.

In one implementation, the processing module 301 is configured to determine the number of repetitions of a set of a plurality of candidate synchronization signal block groups within a transmission window, and may specifically be configured to determine the number of candidate synchronization signal blocks to be transmitted within the transmission window according to a duration of the transmission window, determine the number of repetitions of the set within the transmission window according to the number of candidate synchronization signal blocks included in the set of the plurality of candidate synchronization signal block groups, and the number of candidate synchronization signal blocks to be transmitted within the transmission window.

In one implementation, the processing module 301 may be further configured to determine an extension index of a candidate synchronization signal block, and determine a pseudo co-sited relationship or a synchronization signal block index of the candidate synchronization signal block according to the extension index of the candidate synchronization signal block.

In one implementation, the processing module 301 is configured to determine, when determining the extension index of the candidate synchronization signal block, specifically, determine the extension index of the candidate synchronization signal block to be i=x1×i1+i2 according to the duration of the extension transmission window, the duration of the transmission window, and the period of the transmission window, where X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extension transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In one implementation, the processing module 301 is configured to determine, when determining the extension index of the candidate synchronization signal block, specifically, determine that the extension index of the candidate synchronization signal block is i=x2×i3+i4 according to the duration of the extension transmission window and the period of the field or frame received by the candidate synchronization signal block, where X2 is the number or maximum number of candidate synchronization signal blocks in one field or frame, i3 is the index of the period of the field or frame received by the candidate synchronization signal block in the duration of the extension transmission window, and i4 is the index of the candidate synchronization signal block.

In one implementation, the processing module 301 is configured to determine the pseudo co-sited relationship of the candidate synchronization signal blocks according to the extended index of the candidate synchronization signal blocks, and may specifically be configured to determine that if a plurality of candidate synchronization signal blocks have the same (a mod Q) value, the plurality of candidate synchronization signal blocks have the pseudo co-sited relationship, where a is the extended index of the candidate synchronization signal blocks, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo).

In one implementation, the processing module 301 is configured to determine, when determining a synchronization signal block index of a candidate synchronization signal block according to an extension index of the candidate synchronization signal block, specifically determine that the synchronization signal block index of the candidate synchronization signal block is (a mod Q), where a is the extension index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo).

The embodiments of the present invention and the embodiments of the methods shown in fig. 1-2 are based on the same concept, and the technical effects brought by the embodiments are the same, and the specific principles are not repeated herein, referring to the description of the embodiments shown in fig. 1-2.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention. The terminal 40 may comprise a memory 401, a processor 402 and a communication interface 403, the memory 401, the processor 402 and the communication interface 403 being connected by one or more communication buses. Wherein the communication interface 403 is controlled by the processor 402 to transmit and receive information.

Memory 401 may include read-only memory and random access memory, and provides instructions and data to processor 402. A portion of memory 401 may also include non-volatile random access memory.

The Processor 402 may be a central processing unit (Central Processing Unit, CPU), the Processor 402 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor, but in the alternative, the processor 402 may be any conventional processor or the like. Wherein:

memory 401 is used to store program instructions.

A processor 402 for calling program instructions stored in the memory 401 to cause the terminal 40 to:

A candidate sync signal block index is determined, the candidate sync signal block index ranging from 0 to N-1, N being 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the candidate synchronization signal block index, and specifically may cause the terminal 40 to perform determining the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the PBCH load.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the candidate synchronization signal block index, and in particular may cause the terminal 40 to perform the operation of determining 2 (when N is equal to 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, the processor 402 is configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform determining the candidate synchronization signal block index, and may specifically cause the terminal 40 to perform determining 1,2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to determine 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH, and specifically may cause the terminal 40 to determine 1 MSB bit of the candidate synchronization signal block index according to the load of the PBCH if N is 10, determine 1 MSB bit of the candidate synchronization signal block index according to the load of the PBCH if N is 16, and determine 2 MSB bits of the candidate synchronization signal block index according to the load of the PBCH if N is 20.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the candidate synchronization signal block index, and specifically may cause the terminal 40 to perform determining 2 or 3 LSB bits of the candidate synchronization signal block index according to the PBCH-DMRS sequence.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to determine 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH, and specifically may cause the terminal 40 to determine 1 MSB bit of the candidate synchronization signal block index according to the load of the PBCH if N is 10 or 16, determine 2 MSB bits of the candidate synchronization signal block index according to the load of the PBCH if N is 20, determine 2 MSB bits of the candidate synchronization signal block index according to the load of the PBCH if N is 32, and determine 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH if N is 40.

In one implementation, the processor 402 may also be configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to determine a number of repetitions of a candidate set of synchronization signal blocks within a transmission window, the candidate set of synchronization signal blocks may include a plurality of candidate synchronization signal blocks.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the number of repetitions of the candidate set of synchronization signal blocks within a transmission window, and may specifically cause the terminal 40 to perform determining the number of repetitions of the candidate set of synchronization signal blocks within the transmission window based on a duration of the transmission window.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the number of repetitions of the candidate synchronization signal block group within the transmission window according to the duration of the transmission window, and may specifically cause the terminal 40 to perform determining the number of candidate synchronization signal blocks to be transmitted within the transmission window according to the duration of the transmission window, determining the number of candidate synchronization signal blocks to be included in the candidate synchronization signal block group, and determining the number of repetitions of the candidate synchronization signal block group within the transmission window according to the number of candidate synchronization signal blocks to be transmitted within the transmission window.

In one implementation, the processor 402 may also be configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to receive first signaling sent by a network device, the first signaling being operable to indicate a number of repetitions of a candidate set of synchronization signal blocks within a transmission window.

In one implementation, the processor 402 may also be configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to determine a number of repetitions of a set of candidate sync signal blocks within a transmission window, the candidate sync signal block set may include a plurality of candidate sync signal blocks.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the number of repetitions of a set of a plurality of candidate synchronization signal block groups within a transmission window, and may specifically cause the terminal 40 to determine the number of repetitions of the set within the transmission window based on the duration of the transmission window, the number of candidate synchronization signal blocks transmitted within the transmission window, the number of candidate synchronization signal blocks included in the set of a plurality of candidate synchronization signal block groups, and the number of candidate synchronization signal blocks transmitted within the transmission window.

In one implementation, the processor 402 may also be configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to determine an extended index of a candidate synchronization signal block from which to determine a co-sited relationship or synchronization signal block index of the candidate synchronization signal block.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the extension index of the candidate synchronization signal block, and specifically may cause the terminal 40 to determine, according to the duration of the extension transmission window, the duration of the transmission window, and the period of the transmission window, that the extension index of the candidate synchronization signal block is i=x1×i1+i2, where X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extension transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In one implementation, the processor 402 is configured to invoke the program instructions stored in the memory 401 to cause the terminal 40 to perform determining the extension index of the candidate synchronization signal block, and specifically may cause the terminal 40 to determine, according to the duration of the extension transmission window and the period of the field or frame received by the candidate synchronization signal block, that the extension index of the candidate synchronization signal block is i=x2×i3+i4, where X2 is the number or maximum number of candidate synchronization signal blocks in one field or frame, i3 is the index of the period of the field or frame received by the candidate synchronization signal block in the duration of the extension transmission window, and i4 is the index of the candidate synchronization signal block.

In one implementation, the processor 402 is configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform determining a pseudo co-sited relationship of a candidate synchronization signal block according to an extended index of the candidate synchronization signal block, and may specifically cause the terminal 40 to perform an operation of modulo or remainder operation (modulo) if a plurality of candidate synchronization signal blocks have the same (a mod Q) value, where a is the extended index of the candidate synchronization signal block, Q is a higher layer parameter, and mod represents a pseudo co-sited relationship.

In one implementation, the processor 402 is configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform determining a synchronization signal block index of a candidate synchronization signal block according to an extension index of the candidate synchronization signal block, and may specifically cause the terminal 40 to determine that the synchronization signal block index of the candidate synchronization signal block is (a mod Q), where a is the extension index of the candidate synchronization signal block, Q is a higher-layer parameter, and mod represents a modulo or remainder operation (modulo).

It should be noted that, in the embodiment corresponding to fig. 4, details of implementation of each step and details of the implementation of each step may be referred to the embodiments shown in fig. 1-2 and the foregoing, and will not be described herein again.

The embodiments of the present invention also provide a computer readable storage medium storing a computer program comprising program instructions that, when executed by a processor, cause the processor to perform the steps as performed in the method embodiments shown in fig. 1-2.

The above disclosure is only a few examples of the present invention, and it is not intended to limit the scope of the present invention, but it is understood by those skilled in the art that all or a part of the above embodiments may be implemented and equivalents thereof may be modified according to the scope of the present invention.

Claims

1. A method for processing a candidate synchronization signal block, the method comprising:

Determining the expansion index of a candidate synchronous signal block, and determining the quasi co-station address relation of the candidate synchronous signal block or the synchronous signal block index of the candidate synchronous signal block according to the expansion index of the candidate synchronous signal block;

The candidate sync signal block index is from 0 to N-1, the N being 4, 8, 10, 16, 20, 32 or 40;

the method comprises the steps of determining a quasi co-station address relation of a candidate synchronous signal block according to an expansion index of the candidate synchronous signal block, wherein the quasi co-station address relation of the candidate synchronous signal block comprises the step of determining the synchronous signal block index of the candidate synchronous signal block according to the expansion index of the candidate synchronous signal block if a plurality of candidate synchronous signal blocks have the same (A mod Q) value, wherein A is the expansion index of the candidate synchronous signal block, Q is a high-layer parameter, and mod represents modulo or remainder operation.

2. The method according to claim 1, wherein the method further comprises:

And determining candidate synchronous signal block indexes according to the PBCH-DMRS sequence and/or the load of the PBCH.

3. The method according to claim 1, wherein the method further comprises:

And determining 2 or 3 LSB bits of the candidate synchronous signal block index according to the PBCH-DMRS sequence.

4. The method according to claim 1, wherein the method further comprises:

Depending on the load of the PBCH, 1,2 or 3 MSB bits of the candidate sync signal block index are determined.

5. The method of claim 4, wherein the subcarrier spacing of the candidate sync signal blocks is 15kHz, and wherein the determining 1, 2 or 3 MSB bits of the candidate sync signal block index based on the load of the PBCH comprises:

if the N is 10, determining 1 MSB bit of the candidate synchronous signal block index according to the load of the PBCH;

If the N is 16, determining 1 MSB bit of the candidate synchronous signal block index according to the load of the PBCH;

And if the N is 20, determining 2 MSB bits of the candidate synchronous signal block index according to the load of the PBCH.

6. The method of claim 4, wherein the subcarrier spacing of the candidate sync signal blocks is 30kHz, and wherein the determining 1, 2 or 3 MSB bits of the candidate sync signal block index based on the load of the PBCH comprises:

If the N is 10 or 16, determining 1 MSB bit of the candidate synchronous signal block index according to the load of the PBCH;

if the N is 20, determining 2 MSB bits of a candidate synchronous signal block index according to the load of PBCH;

if the N is 32, determining 2 MSB bits of a candidate synchronous signal block index according to the load of PBCH;

If the N is 40, determining 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH.

7. The method according to claim 1, wherein the method further comprises:

the number of repetitions of a candidate synchronization signal block set within a transmission window is determined, the candidate synchronization signal block set comprising a plurality of candidate synchronization signal blocks.

8. The method of claim 7, wherein determining the number of repetitions of the candidate set of synchronization signal blocks within the transmission window comprises:

and determining the repetition times of the candidate synchronous signal block group in the transmission window according to the duration of the transmission window.

9. The method of claim 8, wherein determining the number of repetitions of the candidate set of synchronization signal blocks within the transmission window based on a duration of the transmission window comprises:

determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the duration of the transmission window;

and determining the repetition times of the candidate synchronous signal block group in the transmission window according to the number of the candidate synchronous signal blocks included in the candidate synchronous signal block group and the number of the candidate synchronous signal blocks transmitted in the transmission window.

10. The method of claim 7, wherein the method further comprises:

and receiving a first signaling sent by the network equipment, wherein the first signaling is used for indicating the repetition times of the candidate synchronous signal block group in the transmission window.

11. The method according to claim 1, wherein the method further comprises:

A number of repetitions of a set of a plurality of candidate sync signal block groups is determined within a transmission window, the candidate sync signal block groups including a plurality of candidate sync signal blocks.

12. The method of claim 11, wherein determining the number of repetitions of the set of candidate sync signal chunks within the transmission window comprises:

Determining the repetition number of the set in the transmission window according to the number of candidate synchronous signal blocks included in the set formed by a plurality of candidate synchronous signal block groups and the number of candidate synchronous signal blocks transmitted in the transmission window.

13. The method of claim 1, wherein determining the extension index of the candidate synchronization signal block comprises:

Based on the length of the extended transmission window, the length of the transmission window and the period of the transmission window, determining an extended index of a candidate synchronization signal block as Wherein X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extended transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

14. The method of claim 1, wherein determining the extension index of the candidate synchronization signal block comprises:

based on the duration of the extended transmission window and the half-frame or frame period received by the candidate sync signal block, determining the expansion index of the candidate synchronous signal block as Wherein X2 is the number or maximum number of candidate sync signal blocks within a field or frame, i3 is the index of the period of the field or frame received by the candidate sync signal block within the duration of the extended transmission window, and i4 is the candidate sync signal block index.

15. A candidate synchronization signal block processing apparatus, characterized in that the apparatus comprises means for performing the method according to any one of claims 1-14.

16. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method of any of claims 1-14.

17. A terminal comprising a memory for storing a computer program comprising program instructions and a processor configured to invoke the program instructions to perform the method of any of claims 1-14.