CN114899206A

CN114899206A - Display panel and preparation method thereof

Info

Publication number: CN114899206A
Application number: CN202210427103.0A
Authority: CN
Inventors: 高思明; 颜志敏
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2022-04-21
Filing date: 2022-04-21
Publication date: 2022-08-12

Abstract

The application discloses display panel and preparation method thereof, display panel includes: the array substrate comprises a mask layer, wherein the mask layer comprises a plurality of mask openings; the pixel definition layer is positioned on one side of the array substrate and comprises a plurality of pixel definition blocks, and pixel openings are formed between the adjacent pixel definition blocks; wherein, the orthographic projection of the mask opening on the pixel definition layer is positioned in the pixel definition block; the light-emitting layer is positioned on one side of the array substrate, which is provided with the pixel defining layer, and comprises a plurality of laminated light-emitting units, and one laminated light-emitting unit is arranged at the position of one pixel opening; the laminated light-emitting unit comprises charge generation layers, gaps are formed between the charge generation layers of the adjacent laminated light-emitting units, and the orthographic projection of the gaps on the mask layer covers at least part of the mask opening. Through the mode, the probability of the light-emitting crosstalk phenomenon between the adjacent light-emitting units can be reduced.

Description

Display panel and preparation method thereof

Technical Field

The application belongs to the technical field of display, and particularly relates to a display panel and a preparation method thereof.

Background

In current Tandem Organic light emitting displays (Tandem OLEDs), a metal-doped Charge Generation Layer (CGL) is generally used, and the Charge Generation Layer is generally disposed to cover the whole surface.

The metal-doped charge generation layer tends to improve the lateral conductivity of the thin film, resulting in Cross-talk (crosstalk) between adjacent light emitting units, thereby affecting the display effect of the display panel.

Disclosure of Invention

The application provides a display panel and a preparation method thereof, which can reduce the phenomenon of luminous crosstalk between adjacent luminous units.

In order to solve the technical problem, the application adopts a technical scheme that: provided is a display panel including: the array substrate comprises a mask layer, wherein the mask layer comprises a plurality of mask openings; the pixel definition layer is positioned on one side of the array substrate and comprises a plurality of pixel definition blocks, and pixel openings are formed between the adjacent pixel definition blocks; wherein an orthographic projection of the mask opening on the pixel definition layer is located within the pixel definition block; the light-emitting layer is positioned on one side of the array substrate, which is provided with the pixel defining layer, and comprises a plurality of laminated light-emitting units, and one laminated light-emitting unit is arranged at one pixel opening position; the laminated light-emitting unit comprises charge generation layers, a gap is formed between the charge generation layers of the adjacent laminated light-emitting units, and the orthographic projection of the gap on the mask layer covers at least part of the mask opening.

In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a method for manufacturing a display panel, including: providing an array substrate, wherein the array substrate comprises a mask layer, and a plurality of mask openings are formed in the mask layer; forming a pixel defining layer, at least a part of a light emitting layer and a plurality of sacrificial layers on one side of the array substrate; wherein the pixel definition layer comprises a plurality of pixel definition blocks, a pixel opening is formed between adjacent pixel definition blocks, and the orthographic projection of the mask opening on the pixel definition layer is positioned in the pixel definition block; the sacrificial layer is positioned on one side, away from the array substrate, of the pixel definition block, and the orthographic projection of the sacrificial layer on the mask layer covers at least part of the mask opening; the light-emitting layer comprises a plurality of laminated light-emitting units, one laminated light-emitting unit is arranged at one pixel opening position, the laminated light-emitting unit comprises charge generation layers, and the charge generation layers of the adjacent laminated light-emitting units are mutually connected and cover the sacrificial layer; and taking the mask layer as a mask, and carrying out laser irradiation on one side of the array substrate, which is far away from the pixel defining layer, so as to remove at least part of the sacrificial layer at the position of the mask opening by ashing, wherein the removed charge generation layer at the position of the sacrificial layer is separated from the charge generation layer at the rest positions and falls off.

Being different from the prior art situation, the beneficial effect of this application is: the display panel provided by the application comprises an array substrate, a pixel definition layer and a light emitting layer; the array substrate is provided with a mask layer, the laminated light-emitting units in the light-emitting layer comprise charge generation layers, gaps are arranged between the charge generation layers of the adjacent laminated light-emitting units, the orthographic projection of the gaps on the mask layer covers at least part of mask openings of the mask layer, and the orthographic projection of the mask openings on the pixel definition layer is positioned in pixel definition blocks of the pixel definition layer. In one aspect, the charge generation layers of adjacent stacked light emitting cells in the light emitting layer are disconnected from each other, which reduces the lateral conductivity of the charge generation layers and reduces the probability of crosstalk between adjacent light emitting cells. On the other hand, the array substrate is provided with the mask layer, the design mode can enable the charge generation layer to be formed on the whole surface when the charge generation layer is formed, and the mask layer can enable the charge generation layers of the adjacent laminated light-emitting units to be disconnected at the position of the pixel definition block, so that the light-emitting area is not damaged, and the process difficulty and the cost are reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:

FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of another embodiment of a display panel according to the present application;

FIG. 3a is a schematic top view of one embodiment of the pixel defining layer and the sacrificial layer of FIG. 2;

FIG. 3b is a schematic top view of one embodiment of the pixel definition layer and the sacrificial layer of FIG. 2 prior to laser ashing;

FIG. 4 is a schematic structural diagram of another embodiment of a display panel according to the present application;

FIG. 5 is a schematic flow chart illustrating an embodiment of a method for manufacturing a display panel according to the present disclosure;

FIG. 6 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 5;

FIG. 7a is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 5;

FIG. 7b is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 5;

FIG. 8a is a schematic structural diagram of another embodiment corresponding to step S102 in FIG. 5;

fig. 8b is a schematic structural diagram of another embodiment corresponding to step S103 in fig. 5.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a display panel of the present application, where the display panel may be an OLED display panel, and the display panel includes: an array substrate 10, a pixel defining layer 12 and a light emitting layer 14.

Specifically, the array substrate 10 may include a plurality of film layers stacked; the plurality of film layers may include a lowermost substrate and a plurality of metal layers above the substrate, and adjacent metal layers are separated by an insulating layer. The substrate may be made of a flexible material such as polyimide or a hard material such as glass. The plurality of metal layers may form a plurality of pixel driving circuits for driving the light emitting layer 14 to emit light. In addition, in the present embodiment, the plurality of film layers in the array substrate 10 further include a mask layer 100, and the mask layer 100 includes a plurality of mask openings 102. Optionally, the mask layer 100 is made of metal, for example, the mask layer 100 may be a stack structure formed by ti/al/ti. Alternatively, the mask layer 100 may be a metal layer closest to the light emitting layer 14 in the array substrate 10, and the design manner may be such that when the mask layer 100 is subsequently used as a laser mask to remove a part of the film layer in the light emitting layer 14 at the position of the mask opening 102, the diffraction effect is not obvious, and the size of the removed film layer in the light emitting layer 14 is as same as the size of the mask opening 102 as possible, so as to improve the precision. Further, when the mask layer 100 is used to perform laser irradiation from the substrate side of the array substrate 10, in order to reduce the effect of laser on the performance of some transistors in the pixel driving circuit, a protection layer may be introduced between the transistors to be protected and the substrate in a stacked manner to block the laser; optionally, the material of the protection layer may be metal.

The pixel defining layer 12 is located on one side of the array substrate 10, the pixel defining layer 12 includes a plurality of pixel openings 122, and a pixel defining block 120 is disposed between adjacent pixel openings 122; wherein the orthographic projection of the mask opening 102 on the pixel defining layer 12 is located within the pixel defining block 120, i.e. the area of the mask opening 102 is smaller than the area of the pixel defining block 120 at the corresponding position. Alternatively, the adjacent pixel defining blocks 120 may be connected to each other to form a mesh structure.

The light-emitting layer 14 is located on one side of the array substrate 10 where the pixel defining layer 12 is located, and includes a plurality of stacked light-emitting units 140, and one stacked light-emitting unit 140 is located at one pixel opening 122; the stacked light emitting units 140 include charge generation layers 1400, and a gap (not shown) is formed between the charge generation layers 1400 of adjacent stacked light emitting units 140, and an orthogonal projection of the gap on the mask layer 100 covers at least a portion of the mask opening 102. Optionally, an orthographic projection of the gap on the mask layer 100 coincides with the mask opening 102. Alternatively, the orthographic projection of the gap on the mask layer 100 covers the mask opening 102 and extends beyond the mask opening 102. Alternatively, the orthographic projection of the gap on the mask layer 100 is located within the mask opening 102. Alternatively, the stacked light emitting unit 140 may further include a plurality of sub light emitting units 1402 stacked, and the charge generation layer 1400 is stacked between two adjacent sub light emitting units 1402. For example, only two sub-lighting units, respectively labeled a and b, are schematically depicted in fig. 1; in other embodiments, more sub-light emitting units may be included, in which case, the number of the corresponding charge generation layers 1400 is multiple, and a gap is formed between the adjacent charge generation layers 1400 disposed on any layer in the adjacent stacked light emitting units 140.

In the above design, the charge generation layers 1400 of the adjacent stacked light emitting units 140 in the light emitting layer 14 are disconnected from each other, which can reduce the lateral conductivity of the charge generation layers 1400 and reduce the probability of crosstalk between the adjacent light emitting units 140. In addition, the array substrate 10 is provided with the mask layer 100, the design manner can enable the charge generation layer 1400 to be formed on the whole surface when the charge generation layer 1400 is formed, and subsequently, the mask layer 100 can enable the charge generation layers 1400 of the adjacent stacked light-emitting units 140 to be disconnected at the position of the pixel definition block 120 so as not to damage the light-emitting region; the mask layer 100 is generally formed by a low-cost photolithography process; compared with the method of directly etching the charge generation layer 1400 by using a precision mask except for the display panel, the method can save the cost of the precision mask and a device for aligning the precision mask and the display panel; the mode cost that this application provided is lower, and the precision is higher.

Referring to fig. 2 and fig. 3a, fig. 2 is a schematic structural diagram of another embodiment of a display panel of the present application, and fig. 3a is a schematic top view of one embodiment of a pixel defining layer and a sacrificial layer in fig. 2. The display panel includes a sacrificial layer 16 in addition to the array substrate 10, the pixel defining layer 12, and the light emitting layer 14 in fig. 1. The sacrificial layer 16 is disposed on a side of the pixel definition block 120 away from the array substrate 10; wherein the sacrificial layer 16 at the location of the pixel defining block 120 includes the via 160, the charge generation layer 1400 is located at the periphery of the via 160, and the orthographic projection of the via 160 on the mask layer 100 covers at least a portion of the mask opening 102. For example, the orthographic projection of the via 160 on the mask layer 100 coincides with the mask opening 102. Alternatively, the orthographic projection of the via 160 on the mask layer 100 covers the mask opening 102 and extends beyond the mask opening 102. Alternatively, the orthographic projection of the via 160 on the mask layer 100 is located within the mask opening 102. Optionally, the material of the sacrificial layer 16 is a metal, for example, the material of the sacrificial layer 16 includes silver and/or magnesium. The introduction of the sacrificial layer 16 can better disconnect the charge generation layers 1400 of the adjacent stacked light emitting units 140. For example, as shown in fig. 3b, fig. 3b is a schematic top view of the pixel defining layer and the sacrificial layer of fig. 2 in a previous embodiment of laser ashing. A laser beam with a specific wavelength (for example, an infrared laser beam, etc.) reaches the sacrificial layer 16 after passing through the mask opening 102, and the sacrificial layer 16 absorbs the energy of the laser beam with the specific wavelength and is removed by ashing, i.e., the form in fig. 3a is changed; the charge generation layer 1400 located above the sacrificial layer 16 removed by ashing falls off to separate from the surrounding charge generation layer 1400. It should be noted that, during the laser ashing process, the laser with a specific wavelength can directly pass through the pixel defining block 120 at the position of the mask opening 102 and the rest of the film layers in the array substrate 10, and the laser with the specific wavelength only acts on the sacrificial layer 16 to reduce the influence on the pixel defining block 120 and the rest of the film layers in the array substrate 10.

Alternatively, as shown in fig. 2, the orthographic outer edge of the sacrificial layer 16 on the mask layer 100 is located at the periphery of the mask opening 102. That is, the area of the sacrificial layer 16 before laser irradiation can be considered to be larger than the area of the mask opening 102; when the laser is irradiated, the part of the sacrificial layer 16 at the position of the mask opening 102 is ashed and removed, and the remaining sacrificial layer 16 is warped outwards, so that the charge generation layer 1400 above the ashed and removed sacrificial layer 16 can be better separated from the rest of the surrounding charge generation layer 1400.

Further, as shown in fig. 2, the sacrificial layer 16 includes a bottom 162 and an extension 164 connected to each other; the bottom portion 162 is disposed between the charge generation layer 1400 and the pixel defining block 120 in a stacked manner, the bottom portion 162 is disposed with a hollow area (not labeled), and the extension portion 164 extends from the hollow area to a direction away from the array substrate 10 to form the via 160. Optionally, the base 162 and extension 164 are connected in an arcuate manner; and/or the inner wall of the via 160 is curved. The above-mentioned sacrificial layer 16 has a simple structure design, and the electric charge generation layer 1400 above the sacrificial layer 16 removed by ashing can be better separated from the rest of the electric charge generation layers 1400 around the sacrificial layer.

Referring to fig. 2, the bottom 162 of the sacrificial layer 16 is stacked between the stacked light emitting units 1400 and the pixel defining block 120, and a space (not shown) is provided between adjacent stacked light emitting units 140. The design method can enable all the laminated light-emitting units 140 to be prepared in advance in the process of preparing the display panel, and at the moment, the charge generation layer 1400, the hole transport layer, the electron transport layer and the like of the adjacent laminated light-emitting units 140 are all designed in a whole surface mode; and then, performing a laser ashing operation to space the adjacent stacked light emitting units 140 apart, so as to reduce the difficulty of the process preparation.

Optionally, as shown in fig. 3a, for at least part of the stacked light emitting units 140, the sacrificial layer 16 located at the periphery of the stacked light emitting units 140 is formed in a ring shape, so that the stacked light emitting units 140 can be completely spaced from the surrounding stacked light emitting units 140, and the probability of crosstalk between adjacent stacked light emitting units 140 is reduced.

Alternatively, as shown in fig. 2, in the direction perpendicular to and away from the array substrate 10, the extending portion 164 has a first height H1, the stacked light emitting units 140 on the surface of the pixel defining block 120 have a second height H2, the first height H1 is greater than the second height H2, and the difference between the first height H1 and the second height H2 is less than or equal to 300nm (e.g., the difference between the first height H1 and the second height H2 is 200nm, 100nm, etc.). The design mode can reduce the influence of the warped sacrificial layer 16 on the film layers such as the subsequent packaging layer and the like and reduce the probability of breakage of the film layers such as the subsequent packaging layer and the like at the position while better breaking the film layers above the grayed sacrificial layer 16 and the rest of the surrounding film layers.

With reference to fig. 1 or fig. 2, the light-emitting layer 14 further includes a plurality of first electrodes 142, the first electrodes 142 are stacked on one side of the stacked light-emitting units 140 facing the array substrate 10, one stacked light-emitting unit 140 is correspondingly provided with one first electrode 142, and the first electrodes 142 of the adjacent stacked light-emitting units 140 are disconnected from each other. Optionally, the first electrode 142 may be an anode, and the material thereof may be gold, tungsten, nickel, or the like. The material of the first electrode 142 is the same as the material of the sacrificial layer 16. The design method can enable the first electrode 142 and the sacrificial layer 16 to be simultaneously prepared, so as to reduce the difficulty of process preparation.

Optionally, please refer to fig. 4, where fig. 4 is a schematic structural diagram of another embodiment of the display panel of the present application. The first electrode 142 is interconnected with the adjacent sacrificial layer 16. That is, the first electrode 142 may be formed over the entire surface before laser irradiation, and the first electrode 142 located above the pixel defining block 120 forms the sacrificial layer 16. The design mode can further reduce the difficulty of the preparation process.

In addition, as shown in fig. 1, the light-emitting layer 14 may further include a plurality of second electrodes 144, and the second electrodes 144 are disposed on a side of the stacked light-emitting units 140 away from the array substrate 10. Alternatively, the second electrode 144 may be a cathode. As shown in fig. 1, the second electrodes 144 at the positions of the adjacent stacked light emitting cells 140 may be connected to each other.

As shown in fig. 2, when the display panel includes the sacrificial layer 16 and the material of the sacrificial layer 16 is metal, the display panel further includes a plurality of insulating members 18, one insulating member 18 is disposed at a position of one via hole 160, and the insulating member 18 at least covers the extension portion 164 at the corresponding position; at this time, the second electrode 144 covers a side of the stacked light emitting units 140 facing away from the array substrate 10 and an interval between adjacent stacked light emitting units 140, and an orthogonal projection of the plurality of second electrodes 144 on the array substrate 10 covers the entire array substrate 10. The above design can reduce the difficulty in forming the second electrode 144, so as to reduce the process cost. Of course, in other embodiments, the insulator 18 of FIG. 2 may be removed when there is no contact between the sacrificial layer 16 and the first electrode 142.

Of course, in other embodiments, the sacrificial layer 16 with a smaller size is disposed on the pixel definition block 120 before the laser irradiation, for example, the orthogonal projection of the sacrificial layer 16 on the mask layer 100 is located in the mask opening 102; after the laser irradiation, the sacrificial layer 16 may be entirely removed, and the display panel may be finally formed without the sacrificial layer 16. In addition, as for the position of the sacrificial layer 16, it may also be located inside the light emitting layer 14, for example, between the sub light emitting unit 1402 closest to the array substrate 10 and the charge generation layer 1400.

Referring to fig. 5, fig. 5 is a schematic flow chart of an embodiment of a manufacturing method of a display panel of the present application, the manufacturing method specifically includes:

s101: an array substrate 10 is provided, the array substrate 10 includes a mask layer 100, and a plurality of mask openings 102 are disposed on the mask layer 100.

Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 5. The array substrate 10 may include a plurality of film layers, which may be formed layer by layer through a corresponding process. For the mask layer 100, which is different from the related art, it can be formed by means of photolithography. For example, a whole mask layer 100 may be formed by deposition or the like; then, forming a photoresist layer on the surface of the mask layer 100, and forming a plurality of exposure openings on the photoresist layer after exposing and developing the photoresist layer; etching and removing the mask layer 100 at the position of the exposure opening to form a mask opening 102; and removing the photoresist layer.

S102: forming a pixel defining layer 12, at least a part of a light emitting layer 14 and a sacrificial layer 16 on one side of an array substrate 10; wherein the pixel definition layer 12 includes a plurality of pixel definition blocks 120, a pixel opening 122 is formed between adjacent pixel definition blocks 120, and a forward projection of the mask opening 102 on the pixel definition layer 12 is located in the pixel definition block 120; the sacrificial layer 16 is positioned on one side of the pixel defining block 120, which faces away from the array substrate 10, and the orthographic projection of the sacrificial layer 16 on the mask layer 100 covers at least part of the mask opening 102; the light-emitting layer 14 includes a plurality of stacked light-emitting units 140, one stacked light-emitting unit 140 is disposed at a position of one pixel opening 122, the stacked light-emitting units 140 include charge generation layers 1400, and the charge generation layers 1400 of adjacent stacked light-emitting units 140 are connected to each other and cover the sacrificial layer 16.

Specifically, as shown in fig. 7a, fig. 7a is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 5. Optionally, the specific implementation process of step S102 may be: the pixel defining layer 12, the sacrificial layer 16 and at least a part of the light emitting layer 14 are sequentially formed on one side of the array substrate 10. In addition, some film layers in the adjacent stacked light emitting units 140 of the light emitting layer 14 may be disposed over the entire surface, such as a hole transport layer, an electron transport layer, and the like.

Alternatively, when the light emitting layer 14 includes the second electrode 144 on the side facing the array substrate 10, and the material of the sacrificial layer 16 is the same as that of the first electrode 142 in the light emitting layer 14, the sacrificial layer 16 and the first electrode 142 in the light emitting layer 14 may be prepared and formed at the same time, and the first electrode 142 and the adjacent sacrificial layer 16 may be disconnected or connected. When the first electrode 142 is connected to the adjacent sacrificial layer 16, an orthogonal projection of the whole of the first electrode 142 and the sacrificial layer 16 on the array substrate 10 may cover the entire array substrate 10.

As a further alternative, as shown in fig. 7a, the orthographic projection of the sacrificial layer 16 on the mask layer 100 is located within the mask opening 102, i.e. the area of the sacrificial layer 16 is smaller than or equal to the area of the mask opening 102. Of course, in other embodiments, as shown in fig. 8a, fig. 8a is a schematic structural diagram of another embodiment corresponding to step S102 in fig. 5. An orthographic projection of the sacrificial layer 16 on the mask layer 100 covers the mask opening 102, i.e. the area of the sacrificial layer 16 is larger than the area of the mask opening 102.

S103: using the mask layer 100 as a mask, and performing laser irradiation from a side of the array substrate 10 away from the pixel defining layer 12 to ash and remove at least a part of the sacrificial layer 16 at the position of the mask opening 102, and separating and dropping the charge generation layer 1400 at the position of the removed sacrificial layer 16 from the charge generation layer 1400 at the rest position.

Specifically, please refer to fig. 7b, wherein fig. 7b is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 5. When the area of the sacrificial layer 16 in fig. 7a is smaller than the area of the mask opening 102, the sacrificial layer 16 can be completely removed through the laser ashing operation.

Referring to fig. 8b, fig. 8b is a schematic structural diagram of another embodiment corresponding to step S103 in fig. 5. When the area of the sacrificial layer 16 in fig. 8a is larger than the area of the mask opening 102, a portion of the sacrificial layer 16 is removed by ashing and the remaining portion of the sacrificial layer 16 is warped by the laser ashing operation, so that the film layer above the removed sacrificial layer 16 can be better separated from the surrounding remaining film layers.

In addition, when the light-emitting layer 14 further includes a second electrode, and the second electrode is located on the side of the stacked light-emitting unit 140 facing away from the array substrate, the second electrode may be prepared and formed before step S103, and it should be noted that after laser ashing, it is ensured that the first electrode and the second electrode are not overlapped.

Of course, in other embodiments, the second electrode may also be prepared and formed after step S103; and when the sacrificial layer 16 is warped after being subjected to laser ashing, as shown in fig. 4, the insulating member 18 may be formed on the surface of the sacrificial layer 16, and then the second electrode 144 may be formed on the entire surface, so that there is no contact between the second electrode 144 and the sacrificial layer 16. When the sacrificial layer 16 is not connected to the first electrode 142, the insulating member 18 may not be provided, and the entire surface of the second electrode 144 may be covered; at this time, although the second electrode 144 is electrically connected to the sacrificial layer 16, it will not affect the normal light emitting display of the display panel.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims

1. A display panel, comprising:

the array substrate comprises a mask layer, wherein the mask layer comprises a plurality of mask openings;

the pixel definition layer is positioned on one side of the array substrate and comprises a plurality of pixel definition blocks, and pixel openings are formed between the adjacent pixel definition blocks; wherein an orthographic projection of the mask opening on the pixel definition layer is located within the pixel definition block;

the light-emitting layer is positioned on one side of the array substrate, which is provided with the pixel defining layer, and comprises a plurality of laminated light-emitting units, and one laminated light-emitting unit is arranged at one pixel opening position; the laminated light-emitting unit comprises charge generation layers, a gap is formed between the charge generation layers of the adjacent laminated light-emitting units, and the orthographic projection of the gap on the mask layer covers at least part of the mask opening.

2. The display panel according to claim 1, further comprising:

the sacrificial layer is positioned on one side, away from the array substrate, of the pixel defining block; the sacrificial layer positioned at the position of the pixel definition block comprises a via hole, the charge generation layer is positioned at the periphery of the via hole, and the orthographic projection of the via hole on the mask layer covers at least part of the mask opening;

preferably, the outer edge of the orthographic projection of the sacrificial layer on the mask layer is positioned at the periphery of the mask opening.

3. The display panel according to claim 2,

the sacrificial layer comprises a bottom part and an extension part which are connected with each other; the bottom is arranged between the charge generation layer and the pixel definition block in a stacked mode, a hollow area is arranged at the bottom, and the extension portion extends from the hollow area to the direction far away from the array substrate to form the through hole;

preferably, the bottom and the extension are connected in an arc shape; and/or the inner wall of the via hole is arc-shaped.

4. The display panel according to claim 3,

the bottom part is stacked between the stacked light-emitting units and the pixel defining block, and a space is reserved between every two adjacent stacked light-emitting units;

preferably, in a direction away from the array substrate, the extension portion has a first height, the stacked light emitting units on the surface of the pixel defining block have a second height, the first height is greater than the second height, and a difference between the first height and the second height is less than or equal to 300 nm.

5. The display panel according to claim 2,

the light-emitting layer further comprises a plurality of first electrodes which are arranged on one side, facing the array substrate, of the laminated light-emitting unit in a laminated mode;

the material of the first electrode is the same as that of the sacrificial layer.

6. The display panel according to claim 5,

the first electrode is connected to the adjacent sacrificial layer.

7. The display panel according to claim 4,

the material of the sacrificial layer comprises metal; the display panel further comprises a plurality of insulating pieces, one insulating piece is arranged at one via hole position, and the insulating piece at least covers the extending part at the corresponding position;

the light-emitting layer further comprises a second electrode, and the second electrode covers one side of the laminated light-emitting unit, which is far away from the array substrate, and the interval between the adjacent laminated light-emitting units.

8. The display panel according to claim 1,

the mask layer is made of metal, the array substrate comprises a plurality of metal layers which are arranged in a stacked mode, and the mask layer is the metal layer which is closest to the pixel defining layer in the array substrate.

9. A method of manufacturing a display panel, comprising:

providing an array substrate, wherein the array substrate comprises a mask layer, and a plurality of mask openings are formed in the mask layer;

forming a pixel defining layer, at least a part of a light emitting layer and a plurality of sacrificial layers on one side of the array substrate; wherein the pixel definition layer comprises a plurality of pixel definition blocks, a pixel opening is formed between adjacent pixel definition blocks, and the orthographic projection of the mask opening on the pixel definition layer is positioned in the pixel definition block; the sacrificial layer is positioned on one side, away from the array substrate, of the pixel definition block, and the orthographic projection of the sacrificial layer on the mask layer covers at least part of the mask opening; the light-emitting layer comprises a plurality of laminated light-emitting units, one laminated light-emitting unit is arranged at one pixel opening position, the laminated light-emitting unit comprises charge generation layers, and the charge generation layers of the adjacent laminated light-emitting units are mutually connected and cover the sacrificial layer;

and taking the mask layer as a mask, and carrying out laser irradiation on one side of the array substrate, which is far away from the pixel defining layer, so as to remove at least part of the sacrificial layer at the position of the mask opening by ashing, wherein the removed charge generation layer at the position of the sacrificial layer is separated from the charge generation layer at the rest positions and falls off.

10. The production method according to claim 9,

and the mask layer is used as a mask, and before laser irradiation is carried out on one side of the array substrate, which is far away from the pixel definition layer, the method also comprises the step of setting the orthographic projection of the sacrificial layer on the mask layer to cover the mask opening.