CN114899149B - A semiconductor device manufacturing method and semiconductor structure - Google Patents

Abstract

The present invention relates to the technical field of semiconductors, and provides a method for manufacturing a semiconductor device and a semiconductor structure, including: providing a substrate; forming a semiconductor layer on the substrate; forming a dielectric layer on the semiconductor layer; forming a photoresist layer on the dielectric layer; using the photoresist layer in the second well region as a mask, implanting ions into the first well region to form a first doping region, and etching part of the dielectric layer to expose the first gate electrode, the first doped region and part of the first well region; remove the photoresist layer in the second well region; use the photoresist layer in the first well region as a mask, implant ions into the second well region to form The second doped region, and part of the dielectric layer is etched to expose the second gate, the second doped region and the second well region; the photoresist layer in the first well region is removed; and a capping layer is formed on on exposed areas of the semiconductor layer. The manufacturing method and the semiconductor structure of the semiconductor device provided by the present invention reduce the preparation time of the semiconductor device.

Description

A semiconductor device manufacturing method and semiconductor structure

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor structure.

Background technique

During the fabrication of semiconductor devices, metal silicide regions can reduce circuit series resistance and improve circuit performance. Reference may be made to the utility model patent with publication number CN2731718Y. Forming the metal silicide region often requires depositing a barrier layer, and then exposing the region where the metal silicide needs to be formed by photolithography. However, when the resistance of the resistor is high, the metal silicide of the semiconductor device at this time affects the electrical performance of the device, and the cost is high. Therefore, how to improve the electrical performance of the semiconductor device at high impedance and reduce the manufacturing cost has become an urgent problem to be solved.

SUMMARY OF THE INVENTION

In view of the above-mentioned deficiencies of the prior art, the present application proposes a method for manufacturing a semiconductor device and a semiconductor structure, which can improve the electrical performance of the semiconductor device at high impedance and reduce the manufacturing cost.

In order to achieve the above object and other objects, the present application proposes a method for manufacturing a semiconductor device, including:

providing a substrate;

A semiconductor layer is formed on the substrate, the semiconductor layer includes a first well region and a second well region, and a first gate formed on the first well region and a first gate formed on the second well region the second grid;

forming a dielectric layer on the semiconductor layer;

forming a photoresist layer on the dielectric layer;

Using the photoresist layer on the second well region as a mask, implant ions into the first well region to form a first doped region, and etch the dielectric layer to expose the the first gate, the first doped region and the first well region;

removing the photoresist layer in the second well region;

Using the photoresist layer on the first well region as a mask, implant ions into the second well region to form a second doping region, and etch the dielectric layer to expose the the second gate, the second doped region and the second well region;

removing the photoresist layer on the first well region; and

A capping layer is formed on the exposed regions of the semiconductor layer.

Optionally, the semiconductor layer further includes a first spacer dielectric layer, a second spacer dielectric layer and a gate oxide layer, and the first spacer dielectric layer and the second spacer dielectric layer are located in the on the gate oxide layer.

Optionally, the thickness of the second sidewall dielectric layer is greater than the thickness of the first sidewall dielectric layer.

Optionally, the step of forming the semiconductor layer includes: forming an isolation trench structure on the substrate, and the isolation trench structure is located between the first well region and the second well region.

Optionally, the upper surface of the isolation trench structure is higher than the upper surfaces of the first well region and the second well region.

Optionally, the cover layer is a metal silicide layer.

Optionally, the material of the dielectric layer is silicon dioxide.

Optionally, the step of forming the capping layer further includes: performing multiple annealing treatments on the semiconductor device to retain metal silicide on the active region and the polysilicon gate region.

The present invention also provides a semiconductor structure, comprising:

substrate;

a semiconductor layer on the substrate, and the semiconductor layer includes a first well region and a second well region, and a first gate and a second gate;

Wherein, the first gate is located on the first well region, and the second gate is located on the second well region;

a dielectric layer on the semiconductor layer; and

a capping layer on the exposed area of the semiconductor layer.

Optionally, the cover layer is a metal silicide layer.

In summary, the present application proposes a method for manufacturing a semiconductor device and a semiconductor structure, wherein the metal reacts with the polysilicon and the active region and does not react with the oxide or nitride of the dielectric layer. Design and fabricate salicide barrier layers for semiconductor devices to meet electrical performance requirements. The electrical performance of the semiconductor device at high impedance can be improved, and the manufacturing cost can be reduced.

Description of drawings

FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application.

FIG. 2 is a schematic diagram of an oxide layer in an embodiment of the present application.

FIG. 3 is a schematic diagram of a patterned photoresist layer in an embodiment of the present application.

FIG. 4 is a schematic diagram of an isolation trench in an embodiment of the present application.

FIG. 5 is a schematic diagram of an insulating medium in an embodiment of the present application.

FIG. 6 is a schematic diagram of an isolation trench structure in an embodiment of the present application.

FIG. 7 is a schematic diagram of a structure of a well region in an embodiment of the present application.

FIG. 8 is a schematic diagram of a gate oxide layer in an embodiment of the present application.

FIG. 9 is a schematic diagram of a polysilicon layer in an embodiment of the present application.

FIG. 10 is a schematic diagram 1 of a sidewall dielectric layer in an embodiment of the present application.

FIG. 11 is a second schematic diagram of a sidewall dielectric layer in an embodiment of the present application.

FIG. 12 is a schematic diagram of a gate in an embodiment of the present application.

FIG. 13 is a schematic diagram of a dielectric layer in an embodiment of the present application.

FIG. 14 is a schematic diagram of a photoresist layer in an embodiment of the present application.

FIG. 15 is a schematic diagram 1 of etching in an embodiment of the present application.

FIG. 16 is a schematic diagram of a first doped region in an embodiment of the present application.

FIG. 17 is a second schematic diagram of etching in an embodiment of the present application.

FIG. 18 is a schematic diagram 3 of etching in an embodiment of the present application.

FIG. 19 is a schematic diagram of a second doped region in an embodiment of the present application.

FIG. 20 is a schematic diagram of a doped region in an embodiment of the present application.

FIG. 21 is a schematic diagram 1 of a cover layer in an embodiment of the present application.

FIG. 22 is a second schematic diagram of a cover layer in an embodiment of the present application.

Description of reference numbers:

100 substrates;

101 oxide layer;

102 nitride layer;

103 patterned photoresist layer;

110 first isolation trench;

111 second isolation trench;

112 the third isolation trench;

113 insulating medium;

120 a first isolation trench structure;

121 second isolation trench structure;

122 the third isolation trench structure;

130 first well region;

131 second well region;

141 first grid;

142 second grid;

210 gate oxide layer;

220 polysilicon layer;

230 first sidewall dielectric layer;

240 The second sidewall dielectric layer;

310 dielectric layer;

320 photoresist layer;

410 the first doped region;

420 second doped regions;

500 overlays.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

The present application proposes a manufacturing method and a semiconductor structure of a semiconductor device, and designs and manufactures a self-aligned silicide barrier layer of the semiconductor device to meet electrical performance requirements. The electrical performance of the semiconductor device at high impedance can be improved, and the manufacturing cost can be reduced.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application. The present application provides a method for manufacturing a semiconductor device. In this embodiment, the method for manufacturing a semiconductor device may include the following steps:

S1. Provide a substrate.

S2, forming a semiconductor layer on the substrate, the semiconductor layer including a first well region and a second well region, and a first gate formed on the first well region, and in the second well region the second gate formed thereon.

S3, forming a dielectric layer on the semiconductor layer.

S4, forming a photoresist layer on the dielectric layer.

S5. Using the photoresist layer on the second well region as a mask, implant ions into the first well region to form a first doped region, and etch part of the dielectric layer to expose The first gate electrode, the first doped region and part of the first well region are extracted.

S6, removing the photoresist layer in the second well region.

S7. Using the photoresist layer on the first well region as a mask, implant ions into the second well region to form a second doped region, and etch part of the dielectric layer to expose all the the second gate, the second doped region and the second well region.

S8, removing the photoresist layer in the first well region.

S9, forming a capping layer on the exposed region of the semiconductor layer.

Please refer to FIG. 2 , which is a schematic diagram of an oxide layer in an embodiment of the present application. In an embodiment of the present application, the substrate 100 is, for example, a silicon substrate for forming a semiconductor structure. The substrate 100 may include a substrate such as silicon (Si), silicon carbide (SiC), sapphire ((Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2) and a silicon layer disposed over the substrate. ) and other semiconductor substrate materials, a silicon layer is formed on the substrate. In this embodiment, phosphorus ions or arsenic ions can be implanted in the silicon layer to form a doped region to form a source or drain region of the semiconductor structure. In some embodiments of the present application, the present application does not limit the material and thickness of the substrate 100 .

Referring to FIG. 2 , in an embodiment of the present application, an oxide layer 101 is formed on the substrate 100 . The oxide layer 101 is, for example, a material such as dense silicon oxide, and the oxide layer 101 can be formed on the substrate 100 by, for example, thermal oxidation, in-situ vapor growth, or chemical vapor deposition. In this embodiment, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900° C. to 1150° C., oxygen is introduced, and the substrate 100 reacts with oxygen at a high temperature to form a dense oxide layer 101 . The thickness of the oxide layer 101 is, for example, 10 to 50 nm, and specifically, for example, 30 nm, 40 nm, 45 nm, or 50 nm.

Referring to FIG. 2 , in an embodiment of the present application, a nitride layer 102 may be formed on the oxide layer 101 . The nitride layer 102 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. Wherein, the oxide layer 101 as a buffer layer can improve the stress between the substrate 100 and the nitride layer 102 . In the present application, the nitride layer 102 can be formed on the oxide layer 101 by, for example, a low pressure chemical vapor deposition (LPCVD) method. In some embodiments of the present application, the substrate 100 with the oxide layer 101 can be placed in a furnace tube filled with dichlorosilane and ammonia, and the pressure range is, for example, 2~10T, and the temperature range is, for example, 700~800 The reaction is carried out at ℃ to deposit the nitride layer 102 . In addition, the thickness of the nitride layer 102 can also be adjusted by controlling the heating time. In some embodiments, the thickness of the nitride layer 102 is, for example, 50 nm˜200 nm, and specifically, for example, 60 nm, 75 nm, 80 nm, 100 nm, 150 nm, 180 nm, or 200 nm. The nitride layer 102 can protect the substrate 100 from the influence of a chemical mechanical polishing (CMP) process involved in the fabrication of the shallow trench isolation structure. In the process of forming the shallow trench, the nitride layer 102 can be used as a mask to protect other parts of the substrate 10 from being damaged when the substrate 10 is etched.

Please refer to FIGS. 3-5 . FIG. 3 is a schematic diagram of a patterned photoresist layer in an embodiment of the present application. FIG. 4 is a schematic diagram of an isolation trench in an embodiment of the present application. FIG. 5 is a schematic diagram of an insulating medium in an embodiment of the present application. In an embodiment of the present application, a photoresist layer can be formed on the nitride layer 102 by, for example, a spin coating method, and after exposure and development processes, a photolithography pattern is formed on the photoresist layer. groove location. Quantitative etching is performed on the substrate 100 , and after the etching is completed, the photoresist layer is removed to form the first isolation trench 110 , the second isolation trench 111 and the third isolation trench 112 .

Referring to FIGS. 3 to 4 , in an embodiment of the present application, the first isolation trench 110 , the second isolation trench 111 , and the third isolation trench 112 are disposed on the substrate 100 side by side in sequence. A first patterned photoresist layer 103 is obtained on the nitride layer 102, and the first patterned photoresist layer 103 may be used to define the location of the trench region. After the first patterned photoresist layer 103 is formed, using the first patterned photoresist layer 103 as a mask, for example, dry etching is used to quantitatively remove the nitride layer 102 , the oxide layer 101 and parts under the photoresist pattern. Substrate 100 . After the etching is completed, the first patterned photoresist layer 103 is removed to form the first isolation trench 110 , the second isolation trench 111 and the third isolation trench 112 .

Referring to FIGS. 3-5 , in an embodiment of the present application, an insulating medium 113 is deposited in the first isolation trench 110 , the second isolation trench 111 and the third isolation trench 112 . The present application does not limit the deposition method of the insulating medium 113, for example, high density plasma chemical vapor deposition (High Density Plasma CVD, HDP-CVD) or high aspect ratio chemical vapor deposition (High Aspect Ratio Process CVD, HARP- CVD) and other deposition methods to form the corresponding insulating medium 113 . After the insulating medium 113 is deposited, a high temperature (eg, 800-1200° C.) tempering process may be performed to increase the density and stress of the insulating medium 113 . The insulating medium 113 is, for example, silicon oxide with high adaptability to grinding. In other embodiments, the insulating medium 113 may also be an insulating material such as fluorosilicate glass.

Please refer to FIG. 5 and FIG. 6 . FIG. 6 is a schematic diagram of an isolation trench structure according to an embodiment of the present application. In an embodiment of the present application, after the insulating medium 113 is prepared, a planarization process is performed on the insulating medium 113 . For example, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process is used to planarize the insulating medium 113 and part of the nitride layer 102 , so that the heights of the insulating medium 113 and the nitride layer 102 are the same. The polished nitride layer 102 is then etched and removed. The present application does not limit the removal method of the nitride layer 102 , such as dry etching or wet etching. The nitride layer 102 is removed by selecting a relatively large thermal phosphoric acid for etching the nitride layer 102 and the oxide layer 101 to form the first isolation trench structure 120, the second isolation trench structure 121 and the third isolation trench structure 120. The isolation trench structure 122 is provided. After the nitride layer 102 is removed, an isolation trench step height is formed between the first isolation trench structure 120 , the second isolation trench structure 121 and the third isolation trench structure 122 and the oxide layer 101 . In different embodiments, the step height requirements are different, and the step height can be adjusted by etching.

Please refer to FIG. 6 and FIG. 7 . FIG. 7 is a schematic diagram of a structure of a well region in an embodiment of the present application. In an embodiment of the present application, after the isolation trench structure is fabricated, ion implantation is performed on the substrate 100 to form different well regions. That is, an active region is formed by isolating the trench structure, and then different types of ions are doped on the active region to form the first well region 130 and the second well region 131 . In this embodiment, the first well region 130 can be formed by doping the active region with, for example, P-type ions, the first well region 130 is, for example, a P-type well region, and the doping ions are boron (B) or gallium (Ga), etc. . For example, the second well region 131 can be formed by doping the active region with N-type ions. The second well region 131 is, for example, an N-type well region, and the doping ions are phosphorus (P) or arsenic (As).

Please refer to FIG. 7 and FIG. 8 . FIG. 8 is a schematic diagram of a gate oxide layer in an embodiment of the present application. In an embodiment of the present application, after the first well region 130 and the second well region 131 are formed, the oxide layer 101 on the surface of the well region is removed, for example, by dry or wet etching. The gate oxide layer 210 is then formed on the surface of the well region, that is, the shallow trench structure. The present application does not limit the formation method of the gate oxide layer 210, such as chemical vapor deposition or physical vapor deposition. In this embodiment, the gate oxide layer 210 is formed by, for example, an in-situ stream generation (ISSG) method, wherein the material of the gate oxide layer 210 is, for example, silicon oxide or the like. In other embodiments of the present application, the thickness of the gate oxide layer 210 may be set according to actual needs. During the formation of the shallow trench, the gate oxide layer 210 will inevitably be scratched. By re-arranging the gate oxide layer 210, the flatness and defect rate of the gate oxide layer 210 can be ensured, and the lateral insulation gate double layer can be improved. Breakdown and leakage of polar transistors.

Please refer to FIG. 8 and FIG. 9 . FIG. 9 is a schematic diagram of a polysilicon layer in an embodiment of the present application. In an embodiment of the present application, a photoresist is formed on the gate oxide layer 210, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown in the figure). The gate oxide layer 210 is then etched through, for example, a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process. In this embodiment, the gate oxide layer 210 is sequentially anisotropically etched by, for example, a dry etching process, and the substrate 100 can serve as an etch stop layer for the gate oxide layer 210 .

Referring to FIG. 9 , in an embodiment of the present application, a polysilicon layer 220 is deposited on the gate oxide layer 210 . The polysilicon layer 220 may be P-type or N-type, and the doping type of the polysilicon layer 220 is different from that of the substrate 100 . In some embodiments of the present application, the thickness of the polysilicon layer 220 may be set according to actual needs. A photoresist is formed on the polysilicon layer 220, and then the photoresist is exposed and developed to form a patterned photoresist layer (not shown in the figure). The polysilicon layer 220 is then etched through, for example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process. In this embodiment, the polysilicon layer 220 is sequentially anisotropically etched by, for example, a dry etching process, and the gate oxide layer 210 can be used as an etch stop layer for the polysilicon layer 220 .

Please refer to FIGS. 10-12 . FIG. 10 is a schematic diagram 1 of a sidewall dielectric layer in an embodiment of the present application. FIG. 11 is a second schematic diagram of a sidewall dielectric layer in an embodiment of the present application. FIG. 12 is a schematic diagram of a gate in an embodiment of the present application. In an embodiment of the present application, after the polysilicon layer 220 and the gate oxide layer 210 are formed, a first spacer dielectric layer 230 is formed on the polysilicon layer 220, the gate oxide layer 210, each well region and the isolation trench structure, In addition, the material of the first spacer dielectric layer 230 is, for example, silicon oxide, silicon nitride, or a stack of silicon oxide and silicon nitride. After the first spacer dielectric layer 230 is formed, the polysilicon layer 220, the gate oxide layer 210, the isolation trench structure, and the first spacer dielectric on each well region may be removed by an etching process such as a photolithography-etching process. The layer 230 retains the first spacer dielectric layer 230 on both sides of the polysilicon layer 210 and on the gate oxide layer 210 . The height of the first spacer dielectric layer 230 may be the same as the height of the polysilicon layer 220 , and the width of the first spacer dielectric layer 230 gradually increases from the top to the bottom of the polysilicon layer 220 . By arranging the first spacer dielectric layer 230 , the leakage phenomenon of the prepared lateral insulated gate bipolar transistor can be prevented. In this embodiment, the shape of the first spacer dielectric layer 230 is, for example, an arc shape. In other embodiments, the shape of the first spacer dielectric layer 230 may also be a triangle shape or an L shape. After the first spacer dielectric layer 230 is formed, a second spacer dielectric layer 240 may also be formed on the upper surface of the semiconductor. After the second spacer dielectric layer 240 is formed, an etching process such as a photolithography-etching process may be used to remove the polysilicon layer 220, the gate oxide layer 210, the isolation trench structure, and the second spacer dielectric on each well region The layer 240 retains the second spacer dielectric layer 240 on both sides of the polysilicon layer 210 and on the gate oxide layer 210 . Thus, the first gate electrode 141 and the second gate electrode 142 are formed.

Please refer to FIG. 13 . FIG. 13 is a schematic diagram of a dielectric layer according to an embodiment of the present application. In an embodiment of the present application, the dielectric layer 310 may be formed on the semiconductor layer. Before ion implantation, an oxide layer is deposited. In this embodiment, an oxide can be formed by CVD (Chemical Vapor Deposition, vapor deposition method) as a dielectric material of the dielectric layer 310 , and the dielectric material is silicon dioxide, for example.

Please refer to FIG. 14 , which is a schematic diagram of a photoresist layer in an embodiment of the present application. In an embodiment of the present application, a photoresist layer 320 may be formed on the dielectric layer 310 . In this embodiment, the photoresist layer 320 may be formed by spin-coating a layer of photoresist on the upper surface of the semiconductor device. The photoresist layer 320 can be cleaned by developing and exposing, so as to be etched in a subsequent process. A cleaning agent may be used when cleaning the photoresist in the photoresist layer 320. In some embodiments of the present application, the cleaning agent may be, for example, a mixed solution including alcohol amine, boric acid and derivatives thereof.

Please refer to FIG. 8 and FIGS. 15-17 . FIG. 15 is a schematic diagram 1 of etching in an embodiment of the present application. FIG. 16 is a schematic diagram of a first doped region in an embodiment of the present application. In an embodiment of the present application, FIG. 17 is a second schematic diagram of etching in an embodiment of the present application. In an embodiment of the present application, the photoresist layer 320 on the second well region 131 is used as a mask to implant ions into the first well region 130 . A first doped region 410 is formed, and a part of the dielectric layer 310 is etched to expose the first gate 141 , the first doped region 410 and a part of the first well region 130 , and the second well region 131 is removed Photoresist layer 320 . In this embodiment, under the condition that the photoresist implanted with N-type ions is not removed, the previously deposited oxide layer is continuously etched by etching. N-type ion implantation and photoresist removal after etching. In some embodiments of the present application, the ions doped in the first doping region 410 may also be ions of phosphorus element, boron element or other elements.

Please refer to FIG. 8 and FIGS. 18-20 . FIG. 18 is a schematic diagram 3 of etching in an embodiment of the present application. FIG. 19 is a schematic diagram of a second doped region in an embodiment of the present application. In an embodiment of the present application. FIG. 20 is a schematic diagram of a doped region in an embodiment of the present application. In an embodiment of the present application, using the photoresist layer 320 on the first well region 130 as a mask, ions are implanted into the second well region 131 to form the second doping region 420 , and part of the dielectric layer 310 is etched , to expose the second gate electrode 142 , the second doped region 420 and the second well region 131 , and to remove the photoresist layer 320 in the first well region 130 . Annealing treatment repairs the crystal damage on the silicon surface caused by N+ ion implantation, restores the lattice structure, and activates arsenic ions. The photomask is exposed and developed before the P-type ion implantation to form a photoresist, and the P-type boron dioxide ion is implanted. Under the condition that the P-type ion implanted photoresist is not removed, the oxide layer deposited before is etched under the P-type mask layer, and the P-type photoresist is removed after the etching is completed.

Please refer to FIG. 21 and FIG. 22. FIG. 21 is a schematic diagram 1 of a cover layer according to an embodiment of the present application. FIG. 22 is a second schematic diagram of a cover layer in an embodiment of the present application. In an embodiment of the present application, the capping layer 500 may be formed on the exposed region of the semiconductor layer. The material of the capping layer 500 may be, for example, metal cobalt, and the thickness of the capping layer 500 may be, for example, 10-20 nm. After the first rapid thermal annealing under nitrogen atmosphere, the metal in contact with the substrate silicon and the polysilicon reacts to form metal silicide, and the generated silicide can be, for example, Co ₂ Si. In this embodiment, the annealing temperature range of the first rapid thermal annealing may be 400-550°C. A second rapid thermal annealing is performed in a high temperature nitrogen atmosphere, leaving metal silicide on the active and polysilicon gate regions. In this embodiment, the annealing temperature range of the second rapid thermal annealing may be, for example, 650-750°C. At this time, Co ₂ Si in a high resistance state is converted into CoSi ₂ in a low resistance state.

Referring to FIGS. 8-22 , the present application further provides a semiconductor structure. In an embodiment of the present application, the semiconductor structure may include a substrate, a semiconductor layer, a dielectric layer and a capping layer. In an embodiment of the present application, the semiconductor layer is located on the substrate 100 , and the semiconductor layer may include a first well region 130 and a second well region 131 and a first gate electrode 141 and a second gate electrode 142 . In an embodiment of the present application, the first gate 141 is located on the first well region 130 , and the second gate 142 is located on the second well region 131 . The dielectric layer 310 may be on the semiconductor layer, and the capping layer 500 may be on the exposed area of the semiconductor layer.

In summary, the present application proposes a method for manufacturing a semiconductor device and a semiconductor structure, wherein the metal reacts with the polysilicon and the active region and does not react with the oxide or nitride of the dielectric layer. Design and fabricate salicide barrier layers for semiconductor devices to meet electrical performance requirements. The electrical performance of the semiconductor device at high impedance can be improved, and the manufacturing cost can be reduced.

The above description of illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise form disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as those skilled in the art will recognize and appreciate of. As indicated, these modifications may be made to the present invention in light of the foregoing description of the described embodiments of the present invention and are intended to be within the spirit and scope of the present invention.

The systems and methods have generally been described herein with details that are helpful in understanding the invention. Furthermore, various specific details have been set forth in order to provide a general understanding of embodiments of the present invention. One skilled in the relevant art will recognize, however, that embodiments of the invention may be practiced without one or more of the specific details, or with other devices, systems, accessories, methods, components, materials, parts, etc. practice. In other instances, well-known structures, materials and/or operations have not been specifically shown or described in detail to avoid obscuring aspects of the embodiments of the invention.

Thus, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are intended to be within the above disclosure, and it should be understood that, in certain circumstances, without departing from the scope and scope of the proposed invention, Some features of the present invention will be employed without the corresponding use of other features in the spirit of the present invention. Therefore, many modifications may be made to adapt a particular environment or material to the essential scope and spirit of the invention. It is not intended that the invention be limited to the specific terms used in the following claims and/or the specific embodiments disclosed as the best modes contemplated for carrying out the invention, but the invention is to be included within the scope of the appended claims any and all embodiments and equivalents within. Accordingly, the scope of the present invention should be determined only by the appended claims.

The above description is only a preferred embodiment of the application and an illustration of the applied technical principle. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above technical features , and shall also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the above features are similar to those disclosed in this application (but not limited to) A technical solution formed by replacing the technical features of the functions with each other. Except for the technical features described in the specification, the other technical features are known technologies by those skilled in the art, and in order to highlight the innovative features of the present invention, the remaining technical features are not repeated here.

Claims (7)

1. A method of manufacturing a semiconductor device, comprising:

providing a substrate;

forming a semiconductor layer on the substrate, wherein the semiconductor layer comprises a first well region, a second well region, a first grid electrode formed on the first well region and a second grid electrode formed on the second well region;

forming a dielectric layer on the semiconductor layer;

forming a photoresist layer on the dielectric layer;

implanting ions into the first well region by taking the photoresist layer on the second well region as a mask to form a first doped region, and etching the dielectric layer to expose the first gate, the first doped region and the first well region;

removing the photoresist layer in the second well region;

implanting ions into the second well region by taking the photoresist layer on the first well region as a mask to form a second doped region, and etching the dielectric layer to expose the second gate, the second doped region and the second well region;

removing the photoresist layer on the first well region;

annealing the semiconductor device and forming a covering layer on the exposed region of the semiconductor layer, wherein the covering layer is a metal silicide layer; and

and carrying out multiple times of annealing treatment on the semiconductor device, and reserving metal silicide on the active region and the polysilicon gate region.

2. A method for manufacturing a semiconductor device according to claim 1, wherein: the semiconductor layer further comprises a first side wall dielectric layer, a second side wall dielectric layer and a grid oxide layer, and the first side wall dielectric layer and the second side wall dielectric layer are located on the grid oxide layer.

3. A method for manufacturing a semiconductor device according to claim 2, wherein: the thickness of the second side wall dielectric layer is larger than that of the first side wall dielectric layer.

4. A method for manufacturing a semiconductor device according to claim 1, wherein: the step of forming the semiconductor layer includes: and forming an isolation trench structure on the substrate, wherein the isolation trench structure is positioned between the first well region and the second well region.

5. A method for manufacturing a semiconductor device according to claim 4, wherein: the upper surface of the isolation trench structure is higher than the upper surfaces of the first well region and the second well region.

6. A method for manufacturing a semiconductor device according to claim 1, wherein: the dielectric layer is made of silicon dioxide.

7. A semiconductor structure, comprising:

a substrate;

the semiconductor layer is positioned on the substrate and comprises a first well region, a second well region, a first grid electrode and a second grid electrode;

wherein the first gate is located on the first well region, and the second gate is located on the second well region;

a dielectric layer on the semiconductor layer; and

the covering layer is located on the exposed area of the semiconductor layer, the covering layer is a metal silicide layer and comprises metal silicide, and the metal silicide is located on the active area and the polycrystalline silicon gate area.

Images