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CN114899072B - A method and system for controlling etching speed of reactive ion etching - Google Patents

A method and system for controlling etching speed of reactive ion etching Download PDF

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Publication number
CN114899072B
CN114899072B CN202210329752.7A CN202210329752A CN114899072B CN 114899072 B CN114899072 B CN 114899072B CN 202210329752 A CN202210329752 A CN 202210329752A CN 114899072 B CN114899072 B CN 114899072B
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etching
etched
gas
reactive ion
sample
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CN114899072A (en
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尚跃
陈建
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Shanghai Ju Yue Electronics Co ltd
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Shanghai Ju Yue Electronics Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/3244Gas supply means
    • H01J37/32449Gas control, e.g. control of the gas flow
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04Cleaning involving contact with liquid
    • B08B3/08Cleaning involving contact with liquid the liquid having chemical or dissolving effect
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2898Sample preparation, e.g. removing encapsulation, etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32715Workpiece holder
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • H01J2237/3341Reactive etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32Processing objects by plasma generation
    • H01J2237/33Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334Etching
    • H01J2237/3343Problems associated with etching
    • H01J2237/3346Selectivity

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明公开了一种反应离子蚀刻(RIE)工艺,目的是确保钨柱完整及表面洁净无杂质(如图1),利于扫描电子显微镜观察,分析失效原因。根据芯片样本表面的欲蚀刻材料选择相应的蚀刻气体,并在蚀刻气体中加入惰性气体;蚀刻过程中主要通过调整样品的倾斜角度、过程清洗及产生高速撞击离子的设备的功率、蚀刻气体和惰性气体的配比来控制欲蚀刻样本的表面欲蚀刻材料和非欲蚀刻材料的蚀刻速度比。通过本发明提供的控制方法能够使反应离子蚀刻保留具有各向异性特点,同时又能获得高刻蚀选择比。本发明还提供了一种控制反应离子蚀刻的蚀刻速度的系统。

The present invention discloses a reactive ion etching (RIE) process, the purpose of which is to ensure that the tungsten column is intact and the surface is clean and free of impurities (as shown in FIG1), which is conducive to observation under a scanning electron microscope and analysis of the failure cause. According to the material to be etched on the surface of the chip sample, the corresponding etching gas is selected, and an inert gas is added to the etching gas; during the etching process, the etching rate ratio of the material to be etched and the non-material to be etched on the surface of the sample to be etched is mainly controlled by adjusting the inclination angle of the sample, the power of the equipment for process cleaning and generating high-speed impact ions, and the ratio of the etching gas and the inert gas. The control method provided by the present invention can make the reactive ion etching retain the anisotropic characteristics while obtaining a high etching selectivity. The present invention also provides a system for controlling the etching rate of reactive ion etching.

Description

Etching speed control method and system for reactive ion etching
Technical Field
Failure analysis of chips is an emerging discipline, beginning to spread from the military industry to the general enterprises in recent years. The method has important practical significance in the aspects of improving the quality of semiconductor chip products, developing and improving technologies, repairing products, arbitrating failure accidents and the like. The failure analysis of the chip is to analyze and verify the failed chip according to the failure mode or phenomenon of the chip, simulate and reproduce the failure phenomenon of the chip to find out the failure reason and mine the failure mechanism. The method is divided into lossy analysis, nondestructive analysis, physical analysis, chemical analysis and the like. The invention relates to the field of failure analysis processing of chips, in particular to an etching speed control method of reactive ion etching (RIE, reactiveion etching) in damage analysis.
Background
The etching techniques commonly used in failure analysis are classified into wet etching and dry etching.
1. Wet etching: wet etching is a method of removing a material to be etched by chemically reacting a chemical solution with the material to be etched. Wet etching is characterized by isotropic etching, but is often caused by undercut due to lateral etching, and especially is more serious due to etching of micro lines in a chip.
2. Dry etching: dry etching is the exposure of the material to be etched on the chip surface to a plasma which reacts physically or chemically with the material to be etched through a window made in the photoresist, thereby removing the exposed portion of the material. Dry etching can be further classified into physical etching and chemical etching.
Physical etching is to dissociate a gas such as argon (Ar) into positively charged ions by glow discharge, and then accelerate the ions by electric field voltage to bombard the surface material of the chip, thereby knocking out atoms of the surface material. This process is entirely physical energy transfer and is therefore referred to as physical etching. The physical etching has good directivity, and can obtain an etching profile close to vertical. However, as the ions are comprehensively and uniformly sputtered on the chip, both the photoresist and the material to be etched can be etched at the same time, and the etching selectivity is low; and the knocked-out substances are not volatile substances (such as gas) and are easy to deposit on the surface and the side wall of the etched film. Physical etching is therefore rarely fully employed in the fabrication of semiconductor devices.
The chemical etching is to dissociate etching gas by using plasma to generate charged ions, molecules, electrons and atomic groups with strong reactivity; the atomic groups diffuse to the surface of the etched film and react with atoms on the surface of the etched film to form volatile products, and the volatile products are pumped out of the reaction cavity by vacuum equipment. This etching is similar to the wet etching described above, except that the state of the reactants is changed from liquid to gaseous and the reaction rate is promoted by plasma. Therefore, the chemical etching has similar advantages and disadvantages as wet etching, has higher selectivity to masks and substrates, and also has isotropic etching phenomenon. Full chemical etching is commonly used in situations where no pattern conversion is required, such as in photoresist removal processes, during semiconductor device fabrication.
Currently, the most widely used etching methods are combinations of physical etching and chemical etching, such as Reactive Ion Etching (RIE). Reactive ion etching is mainly accomplished by chemical reactions, so that a high selectivity can be obtained. The effect of adding ion bombardment in the etching process is to destroy atomic bonds on the surface of the etched material, so as to accelerate the reaction speed, and bombard destroy the product or polymer deposited on the etched surface so as to enable the etched surface to be contacted with etching gas again, thus the etching can be continued. In addition, the sediment on the side wall can not be bombarded by ions, so that the contact between the etching material surface of the side wall part and etching gas is blocked, the lateral corrosion is inhibited, and the anisotropic etching is realized. However, when ion bombardment is used in this method, both the material to be removed and the material not to be removed will be knocked off, and the etching selectivity will be affected. The etching selectivity ratio refers to the ratio of the etching rate of the material to be etched to the etching rate of other materials without etching under the same etching condition.
Disclosure of Invention
In view of the above-described problems with the current Reactive Ion Etching (RIE), the present invention provides a method for controlling the etching rate of Reactive Ion Etching (RIE). The method comprises the following steps: selecting corresponding etching gas according to the material to be etched on the surface of the chip sample, and adding inert gas into the etching gas; in the etching process, the etching speed ratio of the material to be etched on the surface of the sample to be etched to the material not to be etched is controlled mainly by adjusting the inclination angle of the chip sample, the power of equipment for generating high-speed impact ions and the ratio of etching gas to inert gas; meanwhile, the tungsten column on the chip sample is complete, and the surface is clean and free of impurities by combining process cleaning in the etching process. According to experience, the etching rate is high when the horizontal inclination angle of the sample is about 30 degrees under the condition of the same other conditions. The purpose of adding inert gas to the etching gas is to reduce the vacuum in the reaction chamber and slow down the etching rate. The process cleaning reagent is a hydrazine hydrate solution, the purpose is to activate the chip sample surface and remove the residue on the chip sample surface.
Further, the selected etching gas does not erode the non-material to be etched during the reactive ion etching; this may be accomplished by increasing the inert gas or decreasing the power of the apparatus that generates the high velocity impinging ions when it is desired to slow the etch rate ratio of the material to be etched to the material not to be etched.
Preferably, when the material to be etched on the surface of the chip sample is silicon dioxide, the etching gas is CHF 3. The inert gas is preferably argon (Ar). Argon is an inert gas that does not participate in chemical reactions in the etching therein.
The invention also provides a system for controlling the etching speed of the Reactive Ion Etching (RIE) which is convenient to use the method, and the system for controlling the etching speed of the Reactive Ion Etching (RIE) comprises a focusing ion beam microscope and is characterized by further comprising a gas injection module and a sample stage which can incline and rotate along all directions; the gas injection module can adjust the ratio of the injected etching gas to the inert gas.
Drawings
FIG. 1 is a scanning electron microscope image of an etching effect of etching a chip sample surface by using the control method provided by the invention;
FIG. 2 is a scanning electron microscope image of the etching effect of etching the surface of a chip sample using conventional ion reactive etching techniques.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects solved by the invention more clear, the invention is further described in detail below. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The present invention provides an etching rate control method of Reactive Ion Etching (RIE), the method comprising: selecting corresponding etching gas according to the material to be etched on the surface of the chip sample, and adding inert gas into the etching gas; in the etching process, the etching speed ratio of the material to be etched on the surface of the sample to be etched to the material not to be etched is controlled by controlling the inclination angle of the chip sample and the horizontal, the power of equipment for generating high-speed impact ions and the ratio of etching gas to inert gas, and meanwhile, the tungsten column on the chip sample is ensured to be complete by cleaning in the combination process in the etching process, and the surface is clean and free of impurities.
The purpose of tilting the chip sample horizontally is to increase the etching rate. According to experience, under the condition of the same conditions, the horizontal inclination angle of the sample is about 30 degrees, and the etching rate is larger. The purpose of adding inert gas to the etching gas is to reduce the vacuum in the reaction chamber and slow down the etching rate. The process cleaning reagent is a hydrazine hydrate solution, the purpose is to activate the chip sample surface and remove the residue on the chip sample surface.
In one embodiment, it is desirable to etch silicon-based materials on the chip, wherein the chip sample surface material has silicon dioxide, tungsten pores. When etching silicon-based materials (typically silicon dioxide), a large number of etching gases, such as CF 4、CHF3、O2, may be selected. CHF 3 gas is selected here as the etching gas for silicon dioxide, which does not etch tungsten holes. The process cleans, the purpose is to activate the surface and remove residues. The inert gas is selected to be argon, which does not participate in the chemical reaction in the reactive ion etching. The inert gas is added to reduce the vacuum degree in the reaction chamber and slow down the etching speed.
A high-frequency voltage with a certain voltage magnitude and a frequency of 10-100 MHz is applied between the plate electrodes of the device for generating high-speed impact ions to generate high-speed ions, and the high-speed ions impact a chip sample which is placed between the plate electrodes in advance to physically etch silicon dioxide which needs to be removed on the chip. Simultaneously, the etching gas CHF 3 (trifluoromethane) and the inert gas argon are added to perform chemical etching. When the chemical etching speed needs to be reduced, the proportion of inert gas can be increased; or reducing the power of the device that produces high velocity impinging ions; when it is desired to reduce the speed of the physical etching, this can be achieved by reducing the power of the equipment that produces the high-speed impinging ions.
In the embodiment of the invention, the sample is inclined at 30 degrees and automatically rotated, and the rotation aims to increase the uniformity of etching, and the rotation speed is 100r/min. The process cleaning and selecting reagents are as follows: hydrazine hydrate solution for the purpose of activating the surface and removing residues. The selected gas and the corresponding adjustment ratio are CHF 3: ar=100:50 (ratio of chemical parts), the radio frequency power of the device is selected to be 50-100W (the power is mainly consumed by the movement of charged ions between the flat electrodes), the silicon dioxide etching rate under the condition is about 40nm/min, and the tungsten holes are not basically etched but can be physically bombarded. At this time, the silicon dioxide etching speed is high, and the tungsten hole etching speed is low, so that the high selectivity of etching two materials can be realized.
The main chemical reaction process of the chemical etching to remove silicon dioxide can be represented by the following chemical formula:
CHF 3+e=CHF2 + (difluoromethyl) +f (radical) +2e;
SiO 2+4F=SiF4 (gas) +o 2 (gas);
Wherein e is an electron that impinges on the ion band; in addition, oxygen ions decomposed from SiO2 react with CHF 2 + groups under high pressure to generate various volatile gases such as CO +.CO 2↑、H2 O +.and OF +.. The generated gas is vacuumized by adopting equipment.
FIG. 1 is a scanning electron microscope image of the etching effect of etching the surface of a chip sample using the control method provided by the present invention. FIG. 2 is a scanning electron microscope image of the etching effect of etching the surface of a chip sample using conventional ion reactive etching techniques. The comparison of the two can prove that the technical scheme provided by the invention can well control the etching speed ratio of the material to be etched on the surface of the sample to be etched and the material not to be etched, and simultaneously ensure that the tungsten column on the chip sample is complete, and the surface is clean and free of impurities.
The invention also provides a system for controlling the etching speed of the Reactive Ion Etching (RIE) which is convenient to use the method, and the system for controlling the etching speed of the Reactive Ion Etching (RIE) comprises a focusing ion beam microscope and is characterized by further comprising a gas injection module and a sample stage which can incline and rotate along all directions; the gas injection module can adjust the ratio of the injected etching gas to the inert gas.

Claims (7)

1. A method of controlling an etching rate of Reactive Ion Etching (RIE), the method comprising: selecting corresponding etching gas according to the material to be etched on the surface of the chip sample, and adding inert gas into the etching gas; in the etching process, the etching speed ratio of the material to be etched on the surface of the sample to be etched to the material not to be etched is controlled by controlling the inclination angle of the chip sample and the horizontal, the power of equipment for generating high-speed impact ions and the ratio of etching gas to inert gas, and meanwhile, the tungsten column on the chip sample is ensured to be complete by cleaning in the combination process in the etching process, and the surface is clean and free of impurities.
2. The control method of claim 1, wherein the chip sample is adjusted to a horizontal tilt angle of 30 ° during etching, and the chip sample is rotated.
3. The control method of claim 1, wherein the reagent used in the process cleaning is a hydrazine hydrate solution; which is used to activate the chip sample surface and to clean the chip sample surface of residues.
4. A control method according to claim 1, characterized in that the method comprises: the selected etching gas does not corrode the non-material to be etched during the reactive ion etching; this may be accomplished by increasing the inert gas or decreasing the power of the apparatus that generates the high velocity impinging ions when it is desired to slow the etch rate ratio of the material to be etched to the material not to be etched.
5. The control method of claim 1, wherein the inert gas is selected to be argon.
6. A control method according to any one of claims 1 to 3, wherein the etching gas is selected to be CHF 3 when the material to be etched on the surface of the chip sample is silicon dioxide.
7. A system for etch rate control for Reactive Ion Etching (RIE) comprising a focused ion beam microscope, further comprising a gas injection module and a sample stage tiltable and rotatable in all directions; the gas injection module can adjust the ratio of the injected etching gas to the inert gas; the system for controlling the etching rate of Reactive Ion Etching (RIE) adjusts the etching rate of reactive ion etching using the control method according to any one of claims 1 to 5.
CN202210329752.7A 2022-03-28 2022-03-28 A method and system for controlling etching speed of reactive ion etching Active CN114899072B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9613789D0 (en) * 1995-06-30 1996-09-04 Hyundai Electronics Ind Method for analyzing failure in semiconductor device
CN109643664A (en) * 2016-07-20 2019-04-16 佳科仪器控股有限责任公司 The decapsulation of electronic equipment

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Publication number Priority date Publication date Assignee Title
JP2001338961A (en) * 2000-05-30 2001-12-07 Sanyo Electric Co Ltd Failure analysis method of semiconductor device
WO2004013661A2 (en) * 2002-08-02 2004-02-12 E.A. Fischione Instruments, Inc. Methods and apparatus for preparing specimens for microscopy
US8715515B2 (en) * 2009-03-23 2014-05-06 Intevac, Inc. Process for optimization of island to trench ratio in patterned media
CN104658879B (en) * 2013-11-22 2018-06-08 中芯国际集成电路制造(上海)有限公司 The opening method of chip packing-body
CN105699149A (en) * 2016-04-05 2016-06-22 工业和信息化部电子第五研究所 Layer stripping method in chip failure analysis process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9613789D0 (en) * 1995-06-30 1996-09-04 Hyundai Electronics Ind Method for analyzing failure in semiconductor device
CN109643664A (en) * 2016-07-20 2019-04-16 佳科仪器控股有限责任公司 The decapsulation of electronic equipment

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