CN114895401B - Silicon photon chip optical coupling structure and manufacturing method thereof - Google Patents
Silicon photon chip optical coupling structure and manufacturing method thereof Download PDFInfo
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- 230000003287 optical effect Effects 0.000 title claims abstract description 177
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 122
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 122
- 239000010703 silicon Substances 0.000 title claims abstract description 122
- 238000010168 coupling process Methods 0.000 title claims abstract description 84
- 230000008878 coupling Effects 0.000 title claims abstract description 83
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000013307 optical fiber Substances 0.000 claims abstract description 21
- 210000001503 joint Anatomy 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 73
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 73
- 230000008569 process Effects 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- 238000005253 cladding Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000000835 fiber Substances 0.000 abstract description 3
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- 238000010586 diagram Methods 0.000 description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/12002—Three-dimensional structures
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4287—Optical modules with tapping or launching means through the surface of the waveguide
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4296—Coupling light guides with opto-electronic elements coupling with sources of high radiant energy, e.g. high power lasers, high temperature light sources
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B2006/12133—Functions
- G02B2006/12147—Coupler
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- Optics & Photonics (AREA)
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Abstract
The invention discloses a silicon photon chip optical coupling structure and a manufacturing method thereof, wherein the silicon photon chip optical coupling structure comprises a silicon substrate; a silicon photon chip functional structure area is arranged on the device layer of the silicon substrate, and an optical waveguide area and an optical coupling area are arranged on the silicon photon chip functional structure area; the optical coupling region is provided with an inverted ridge groove, and extends from the end face of the silicon substrate to the optical waveguide region; an isolation layer is arranged along the inner wall of the inverted-ridge-shaped groove, an inverted-ridge-shaped optical waveguide is arranged in the inverted-ridge-shaped groove and above the isolation layer, the end face of the inverted-ridge-shaped optical waveguide layer is in butt joint with the optical fiber, and the other end of the inverted-ridge-shaped optical waveguide layer is in butt joint with the device layer optical waveguide area. The silicon photon chip optical coupling structure obtained by the structure and the method can realize low-loss, distortion-free and high-efficiency coupling of the silicon photon chip and a single-mode fiber or a laser chip, and has low transmission loss.
Description
Technical Field
The invention relates to the technical field of optical devices, in particular to a silicon photon chip optical coupling structure and a manufacturing method thereof.
Background
The silicon photon technology is a new technology for developing and integrating photon devices based on the same material as the microelectronic integration technology, namely silicon material, by utilizing the existing CMOS compatible technology, and can be integrated with electronic devices at the same time, so that the integration of optoelectronic devices is realized, the advantages of ultra-large scale integration and the like of the microelectronic technology and the advantages of ultra-high speed, ultra-low power consumption and the like of the silicon photon technology are integrated, and the silicon photon technology is one of the hot spots of current research and development. Applications of silicon photonics technologies include biosensing, nonlinear optics, lidar systems, optical gyroscopes, radio frequency integrated optoelectronics, integrated radio transceivers, new light sources, laser noise reduction, gas sensors, high speed microwave signal processing, and the like, in addition to telecommunications and data communications.
The alignment coupling of the silicon photonic chip and the single mode fiber is inevitably realized in the application process of the silicon photonic device. The current commonly used silicon photon chip optical coupling method and structure mainly comprises vertical grating coupling and end surface coupling. The vertical grating coupling is based on Bragg gratings, so that the silicon photonic chip and the optical fiber are coupled at an angle of almost 90 degrees; the end face coupling is to manufacture a mode spot adapter at the coupling position of the silicon photon chip to realize the optical coupling of the two. The optical loss of vertical coupling is at least about 3dB, so that the optical loss is further reduced, the technical difficulty is great, the space structure required by vertical coupling is large, and the optical coupling is polarization-sensitive. The vertical grating coupling is whether the optical fiber is vertically or horizontally placed or the reflection vertical grating coupling, the optical coupling efficiency is difficult to be improved to more than 50%, and the requirements on the lithography precision are high. The end face coupling, the discrete optical lens group coupling, the coupling efficiency is relatively high, but the packaging volume is large, the optical chip integration is inconvenient, and the reliability is reduced; the heterogeneous material is adopted as the mode spot adapter, so that a tip optical waveguide is required to be manufactured, the requirements on the lithography precision are high, and the coupling efficiency is difficult to improve; the multi-layer ridge waveguide or the 3D waveguide can improve the coupling efficiency, but the existing structure is formed by large-area etching, the large area almost occupies 99% of the area of the wafer, the manufacturing time is long, and the roughness of the etched surface and side wall is difficult to control, so that the light transmission loss is large. For example, chinese patent application number 2009801361983, entitled method and apparatus for efficient coupling between silicon photonic chips and optical fibers, namely 3D waveguide structures.
Disclosure of Invention
The invention aims to provide a silicon photon chip optical coupling structure and a manufacturing method thereof, which solve the problems of high manufacturing cost and high optical transmission loss of the existing optical coupling structure.
The technical scheme adopted for solving the technical problems is as follows: the technical scheme adopted for solving the technical problems is as follows: a silicon photonics chip optical coupling structure for transmitting continuous light includes a silicon substrate; a silicon photon chip functional structure area is arranged on the device layer of the silicon substrate, and an optical waveguide area and an optical coupling area are arranged on the silicon photon chip functional structure area; the optical coupling region is provided with an inverted ridge groove, and extends from the end face of the silicon substrate to the optical waveguide region; an isolation layer is arranged along the inner wall of the inverted-ridge groove, an inverted-ridge optical waveguide layer is arranged in the inverted-ridge groove and above the isolation layer, the end face of the inverted-ridge optical waveguide layer is abutted with an optical fiber to be used for receiving an optical waveguide, and the other end of the inverted-ridge optical waveguide layer is abutted with an optical waveguide region of a device layer to be used for transmitting the optical waveguide.
Preferably, the material of the isolation layer is low-stress silicon oxide, and the material of the inverted ridge optical waveguide layer is polysilicon.
Specifically, the inverted ridge groove is provided with at least two layers of grooves downwards from the surface of the silicon substrate, a first groove and a second groove are sequentially arranged from top to bottom, the widths of the end faces of the first groove and the second groove are not smaller than the core diameter of an optical fiber, the other end of the first groove is in butt joint with a device layer optical waveguide area, and the width of the joint part of the first groove and the device layer optical waveguide area is equal to the width of the device layer optical waveguide; the length of the second groove is not greater than that of the first groove, and the width of one end of the second groove, which is close to the optical waveguide area of the device layer, is greater than that of one end of the first groove, which is close to the optical waveguide area.
Preferably, the inverted ridge groove is provided with more than three layers of grooves downwards from the surface of the silicon substrate, and is a first groove and a second groove … … Nth groove from top to bottom in sequence, wherein the length of the next layer of groove is not greater than that of the previous layer of groove, and the width of one end, close to the optical waveguide area of the device layer, from the second groove to the Nth groove increases gradually layer by layer.
Further, the inverted ridge groove is 1-1.5 times of the core diameter of the optical fiber.
And the silicon substrate is also provided with an upper cladding layer which covers the surfaces of the inverted ridge waveguide layer and the functional structure area of the silicon photonic chip, and the upper cladding layer and the lower cladding layer are used for limiting light waves to propagate in the inverted ridge waveguide layer.
Preferably, the material of the upper cladding layer is low-stress silicon oxide.
Preferably, the width of the inverted ridge groove gradually narrows from the end face of the silicon substrate to the optical waveguide region of the device layer.
The invention also discloses a manufacturing method of the silicon photon chip optical coupling structure, which comprises the following steps:
1) Forming a silicon oxide layer on a silicon substrate by dry oxidation;
2) Depositing a low-stress silicon oxide layer on the silicon oxide layer in the step 1) by a plasma chemical vapor deposition method;
3) Defining the shape of an upper layer ridge region of the inverted ridge optical waveguide of the optical coupling region through mask photoetching, and then etching downwards through a dry plasma etching process to form a first groove of the inverted ridge optical waveguide;
4) Defining the shape of a second layer ridge region of the inverted ridge optical waveguide of the optical coupling region through mask photoetching, and then etching downwards through a dry plasma etching process to form a second groove of the inverted ridge optical waveguide; etching the third groove to the N groove in the same method as the second groove;
5) Dry oxidation to planarize and smooth the inverted ridge trench formed by the above process; then depositing a low-stress silicon oxide layer on the surface of the silicon substrate and in the inverted ridge groove by a plasma deposition method;
6) Removing the low-stress silicon oxide layer at the butt joint position of the first groove step and the optical waveguide region of the device layer through mask photoetching;
7) Growing polysilicon on the surface of the silicon substrate by an epitaxial process until the whole inverted ridge-shaped groove is filled;
8) High-temperature annealing, adjusting the property of epitaxial polycrystalline silicon, and reducing defects to achieve low transmission loss;
9) Flattening the silicon substrate by Chemical Mechanical Polishing (CMP), exposing the clean device layer after CMP;
10A silicon optical function structure is manufactured, a multi-layer reverse ridge optical coupling structure is finally formed in the optical coupling area, and a low-stress silicon oxide layer is deposited on the surface of the functional structure area of the silicon photonic chip through a plasma deposition method, so that an upper cladding layer is formed.
In order to improve the smoothness of the side wall of the inverted ridge-shaped groove, the step 5) further comprises the steps of removing the dry oxidation layer of the groove through diluted hydrofluoric acid HF after dry oxidation, and then carrying out dry oxidation until the side wall of the formed inverted ridge-shaped groove is smooth.
In order to improve the surface flatness of the wafer, the step 9) may be to protect the epitaxial polysilicon in the optical coupling region by mask lithography, then to etch the polysilicon by isotropic chemistry to achieve the uniformity of the heights of the regions on the wafer surface, and then to planarize the silicon substrate by CMP.
The invention has the beneficial effects that: the optical coupling structure adopts an inverted ridge structure design, a layer of silicon oxide is deposited through oxidation and plasma to serve as an isolation layer, polysilicon is epitaxially grown in the multi-layer inverted ridge groove to be filled, the multi-layer inverted ridge groove is used as a mode spot adapting structure for aligning and coupling with a silicon photon chip, and low-loss, distortion-free and high-efficiency coupling of the silicon photon chip and a single-mode fiber or a laser chip can be realized, and the transmission loss is low.
The invention will be described in more detail below with reference to the drawings and examples.
Drawings
Fig. 1 is a schematic perspective view of a two-layer trench structure according to the present invention.
Fig. 2 is a schematic perspective view of a three-layer trench structure according to the present invention.
Fig. 3 is a partial longitudinal cross-sectional view of the present invention with three layers of grooves.
Fig. 4 is a cross-sectional view of A-A in fig. 2.
Fig. 5 is a cross-sectional view of B-B of fig. 2.
Fig. 6 is a cross-sectional view of C-C of fig. 2.
Fig. 7 is a cross-sectional view of D-D in fig. 2.
Fig. 8 is a schematic view showing a structure of forming a silicon oxide layer on a silicon substrate in the present invention.
FIG. 9 is a schematic diagram of a structure for depositing a low stress silicon oxide layer on an 8-way silicon oxide layer according to the present invention.
Fig. 10 is a schematic diagram of a photoresist coated on a low stress silicon oxide layer.
Fig. 11 is a schematic structural view of a photoresist mask formed on a low stress silicon oxide layer.
Fig. 12 is a schematic diagram of a structure for forming a silicon oxide hard mask by a mask photolithography process.
Fig. 13 is a schematic diagram of the structure after photoresist removal.
Fig. 14 is a schematic structural view of forming a first trench.
Fig. 15 is a schematic structural diagram of a deposition of a low stress silicon oxide layer over a first trench and a silicon photonics chip functional structure region.
Fig. 16 is a schematic diagram of a photoresist coated on a low stress silicon oxide layer.
Fig. 17 is a schematic diagram of a photoresist mask formed over a low stress silicon oxide layer.
Fig. 18 is a schematic structural diagram of forming a silicon oxide hard mask.
Fig. 19 is a schematic diagram of a structure for removing photoresist.
Fig. 20 is a schematic structural view of forming a second trench.
Fig. 21 is a schematic view of a structure in which a silicon oxide layer is formed on the surface of a silicon substrate and in an inverted ridge trench.
Fig. 22 is a schematic structural view of a low stress silicon oxide layer formed on a silicon oxide layer.
Fig. 23 is a schematic structural view of removing the silicon oxide layer at the junction of the first trench step and the device layer optical waveguide region.
Fig. 24 is a schematic view of a structure for growing polysilicon on a surface of a silicon substrate.
Fig. 25 is a schematic structural view of an inverted ridge optical waveguide layer forming a two-layer structure in an optical coupling region.
FIG. 26 is a schematic view of a structure for forming an upper cladding layer.
Fig. 27 is a schematic view of a structure for forming the third trench.
Fig. 28 is a schematic structural view of depositing a silicon oxide layer on the surface of a silicon substrate and within an inverted ridge trench.
Fig. 29 is a schematic view of a structure in which the silicon oxide layer is removed at the junction of the first trench step and the optical waveguide region of the device layer.
Fig. 30 is a schematic diagram of a structure for growing polysilicon on a surface of a silicon substrate.
Fig. 31 is a schematic view of a structure in which an inverted ridge optical waveguide layer is formed in an optical coupling region.
Detailed Description
Embodiment 1as shown in fig. 1, a silicon photonic chip optical coupling structure for transmitting continuous light includes a silicon substrate 1, a silicon photonic chip functional structure region 11 is disposed on a device layer of the silicon substrate 1, and an optical waveguide region 13 and an optical coupling region 12 are disposed on the silicon photonic chip functional structure region 11. The optical coupling region 12 is provided with an inverted ridge groove 2, and the optical coupling region 12 extends from the end face of the silicon substrate 1 to the optical waveguide region 13; an isolation layer 3 for isolating epitaxial polysilicon and silicon of a substrate wafer is arranged along the inner wall of the inverted ridge groove 2, an inverted ridge optical waveguide layer 4 is arranged in the inverted ridge groove 2 and above the isolation layer 3, the end face of the inverted ridge optical waveguide layer 4 is in butt joint with an optical fiber for receiving an optical waveguide, and the other end of the inverted ridge optical waveguide layer is in butt joint with a device layer optical waveguide region 13 for transmitting the optical waveguide. The silicon substrate 1 is also provided with an upper cladding layer 5 which covers the surfaces of the inverted ridge optical waveguide layer 4 and the silicon photonic chip functional structure region 11. The material of the upper cladding layer 5 is preferably low-stress silicon oxide, the material of the isolation layer 3 is preferably silicon oxide, the silicon used for isolating epitaxial polysilicon and a substrate wafer is also used as the lower cladding layer of the inverted ridge waveguide layer 4, and the material of the inverted ridge waveguide layer 4 is preferably polysilicon.
In the silicon substrate of this embodiment, silicon On Insulator (SOI) with a certain device layer thickness is taken as an example, and the device layer thickness can be selected from 220nm, 340nm and 3 μm which are commonly used at present. And is coupled with an optical fiber, wherein the optical fibers for coupling are standard single-mode optical fibers, namely optical fibers with the core diameter of 8-9 mu m, and the end faces are processed by flat cutting or inclined 8 degrees.
The inverted ridge groove 2 is provided with two layers of grooves downwards from the surface of the silicon substrate 1, a first groove 21 and a second groove 22 are arranged in sequence from top to bottom, the widths of the end faces of the first groove 21 and the second groove 22 are not smaller than the core diameter of an optical fiber, namely not smaller than 9 mu m, the other end of the first groove 21 is in butt joint with the device layer optical waveguide region 13, and the width of the joint part of the first groove 21 and the device layer optical waveguide region 13 is equal to the width of the device layer optical waveguide; for a 220nm thin device layer, the width of the O band (optical wavelength 1260nm-1360 nm) is 500nm, and the width of the C band (optical wavelength 1530nm-1565 nm) is 450nm; for a thick device layer of 3 μm, the width is 3 μm; the width of the inverted ridge groove 2 gradually narrows from the end face of the silicon substrate 1 toward the device layer optical waveguide region 13. The length of the first trench 21 is not less than 1000 μm, the length of the second trench 22 is not greater than the length of the first trench 21, and the width of the second trench 22 near the device layer optical waveguide region 13 is greater than the width of the first trench 21 near the optical waveguide region 13. The depth of the inverted ridge groove 2 is not less than 9 μm and not more than 15 μm, wherein the depth of the first groove 21 is not less than 3 μm and not more than 6 μm.
The manufacturing method of the silicon photon chip optical coupling structure comprises the following steps:
1) Forming a silicon oxide layer 100 having a thickness of not more than 100nm on the device layer of the silicon substrate 1 by dry oxidation, as shown in fig. 8;
2) Depositing silicon oxide on the silicon oxide layer 100 of step 1) by a plasma chemical vapor deposition method to form a low stress silicon oxide layer 200 having a thickness of not more than 500nm, as shown in fig. 9; the silicon oxide in the low stress silicon oxide layer 200 is prepared by a plasma chemical vapor deposition method, and thus, the stress in the deposited silicon oxide layer is small compared with the silicon oxide obtained by dry oxidation, and thus, it is called a low stress silicon oxide layer. The low stress silicon oxide layer acts as an etching hard mask in the optical coupling region; in other areas, the device layer is protected from the subsequent epitaxial polysilicon.
3) Coating a photoresist 300 on the low stress silicon oxide layer 200 as a mask, wherein the thickness of the photoresist 300 is 1.2um to 1.3um as shown in fig. 10, and then forming a photoresist mask through exposure and development as shown in fig. 11; the photoresist 300 may be a positive photoresist or a negative photoresist, and different masks may be selected according to different photoresists, which is a conventional process and will not be described in detail herein.
Removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask by a mask photolithography process using photoresist as a mask to define an upper ridge region shape 400 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 12; the photoresist 300 on the surface is removed by using SPM (sulfuric acid and hydrogen peroxide), as shown in FIG. 13; then, the first trench 21 of the inverted ridge optical waveguide is formed by dry plasma etching process and etching downwards by using the low stress silicon oxide layer 200 as a mask, as shown in fig. 14;
4) Depositing a low stress silicon oxide layer 200 with a thickness of not more than 500nm on the first trench by a plasma chemical vapor deposition method, as shown in fig. 15; then, a photoresist 300 is coated on the low stress silicon oxide layer 200, as shown in fig. 16, a photoresist mask is formed through an exposure and development process, as shown in fig. 17, and the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask are removed through a mask photolithography process to define the shape of a second layer ridge region 500 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 18; then, SPM (sulfuric acid and hydrogen peroxide) is used for removing photoresist on the surface, as shown in FIG. 19, and then a second groove 22 of the inverted ridge optical waveguide is formed by dry plasma etching process and etching downwards by taking the low-stress silicon oxide layer 200 as a mask, as shown in FIG. 20;
5) If the surface of the inverted ridge groove 2 formed by the process is not smooth enough through one-time dry oxidation, the dry oxidation layer in the inverted ridge groove can be removed through diluted hydrofluoric acid HF, then the dry oxidation is carried out again, the dry oxidation layer in the inverted ridge groove is removed through diluted hydrofluoric acid HF, and the dry oxidation is carried out again until the side wall of the formed ridge groove 1 is smooth, as shown in fig. 21, the concentration of the diluted hydrofluoric acid HF is 30% -50%; then a low stress silicon oxide layer 200 with the thickness not more than 500nm is deposited on the surface of the silicon substrate and in the inverted ridge groove by a plasma deposition method, as shown in fig. 22; the ridge trench formed by the etching serves as a lower cladding layer to isolate the subsequent epitaxial polysilicon from the silicon of the substrate wafer. The other areas are to protect the device layer from the subsequent epitaxial polysilicon and also to act as a removal stop layer for the subsequent epitaxial polysilicon.
6) Removing the silicon oxide layer 100 at the butt joint position of the step of the first groove 21 and the optical waveguide region of the device layer by mask lithography, as shown in fig. 23; the mask lithography can refer to step 3).
7) Growing polysilicon 600 on the surface of the silicon substrate by an epitaxial process until the entire inverted ridge trench is filled, as shown in fig. 24;
8) High-temperature annealing, adjusting the property of epitaxial polycrystalline silicon, and reducing defects to achieve low transmission loss; in particular, reference may be made to chinese patent application No. CN201710254026.2, entitled annealing condition parameters mentioned in an annealing process for increasing the crystallization rate of a polycrystalline silicon ingot.
9) Planarizing the silicon substrate by Chemical Mechanical Polishing (CMP), exposing the clean device layer after CMP, and finally forming an inverted ridge optical waveguide layer 4 in the optical coupling region 12, as shown in fig. 25; or protecting epitaxial polysilicon of the optical coupling region by using a mask through mask photoetching, then etching the polysilicon through isotropy chemistry to realize the consistency of the heights of all regions on the surface of the wafer, and then flattening the silicon substrate through CMP.
10 A silicon photonics structure is fabricated on the device layer and a low stress silicon oxide layer 200 having a thickness of not more than 500nm is deposited by a plasma deposition method on the surface of the silicon photonics chip functional structure region to form the upper cladding layer 5, as shown in fig. 26. If the electrode is led out, an electrode window area needs to be etched, and the specific process is not the core of the patent of the invention and can be referred to as a semiconductor manufacturing process.
Example 2: a silicon photon chip optical coupling structure is used for transmitting continuous light and comprises a silicon substrate 1, wherein a silicon photon chip functional structure area 11 is arranged on a device layer of the silicon substrate 1, and an optical waveguide area 13 and an optical coupling area 12 are arranged on the silicon photon chip functional structure area 11. The optical coupling region 12 is provided with an inverted ridge groove 2, and the optical coupling region 12 extends from the end face of the silicon substrate 1 to the optical waveguide region 13; an isolation layer 3 for isolating epitaxial polysilicon and silicon of a substrate wafer is arranged along the inner wall of the inverted ridge groove 2 and is also used as a lower cladding layer of the inverted ridge waveguide layer 4, an inverted ridge optical waveguide layer 4 is arranged in the inverted ridge groove 2 and above the isolation layer 3, the end face of the inverted ridge optical waveguide layer 4 is in butt joint with an optical fiber, and the other end of the inverted ridge optical waveguide layer 4 is in butt joint with a device layer optical waveguide region 13. The silicon substrate 1 is also provided with an upper cladding layer 5 which covers the surfaces of the inverted ridge optical waveguide layer 4 and the silicon photonic chip functional structure region 11.
The inverted ridge groove 2 is provided with three layers of grooves downwards from the surface of the silicon substrate 1, namely a first groove 21, a second groove 22 and a third groove 23 from top to bottom, the widths of the end faces of the first groove 21, the second groove 22 and the third groove 23 are not smaller than the core diameter of an optical fiber, namely not smaller than 9 mu m, the other end of the first groove 21 is in butt joint with the device layer optical waveguide region 13, and the width of the joint with the device layer optical waveguide region 13 is equal to the width of the device layer optical waveguide region 13; the length of the first groove 21 is not less than 1000 μm, the length of the second groove 22 is not greater than the length of the first groove 21, the length of the third groove 23 is not greater than the length of the second groove 22, and the width of the second groove 22 near one end of the device layer optical waveguide region 13 is greater than the width of the first groove 21 near one end of the optical waveguide region 13; the width of the third trench 23 at the end near the optical waveguide region 13 of the device layer is larger than the width of the second trench 22 at the end near the optical waveguide region 13. The depth of the inverted ridge groove 2 is not less than 9 μm and not more than 15 μm, wherein the depth of the first groove 21 is not less than 3 μm and not more than 5 μm, and the depth of the second groove 22 is not less than 3 μm and not more than 5 μm.
The manufacturing method of the silicon photon chip optical coupling structure comprises the following steps:
1) Forming a silicon oxide layer 100 having a thickness of not more than 100nm on the device layer of the silicon substrate 1 by dry oxidation, as shown in fig. 8;
2) Depositing a low stress silicon oxide layer 200 having a thickness of not more than 500nm on the silicon oxide layer 100 of step 1) by a plasma chemical vapor deposition method, as shown in fig. 9;
3) A photoresist 300 is coated on the low stress silicon oxide layer 200 as a mask as shown in fig. 10, and then a photoresist mask is formed through an exposure and development process as shown in fig. 11;
Removing the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask by a mask photolithography process using photoresist as a mask to define an upper ridge region shape 400 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 12; the photoresist 300 on the surface is removed using SPM (sulfuric acid and hydrogen peroxide), as shown in fig. 13; then, the first trench 21 of the inverted ridge optical waveguide is formed by dry plasma etching process and etching downwards by using the low stress silicon oxide layer 200 as a mask, as shown in fig. 14;
4) Depositing a low stress silicon oxide layer 200 with a thickness of not more than 500nm on the first trench by a plasma chemical vapor deposition method, as shown in fig. 15; then, a photoresist 300 is coated on the low stress silicon oxide layer 200, as shown in fig. 16, a photoresist mask is formed through an exposure and development process, as shown in fig. 17, and the low stress silicon oxide layer 200 and the silicon oxide layer 100 exposed outside the mask are removed through a mask photolithography process to define the shape of a second layer ridge region 500 of the inverted ridge optical waveguide of the optical coupling region, as shown in fig. 18; then, SPM (sulfuric acid and hydrogen peroxide) is used to remove the photoresist on the surface, as shown in FIG. 19, and then a second groove 22 of the inverted ridge optical waveguide is formed by dry plasma etching process and etching downwards by taking the low stress silicon oxide layer 200 as a mask, as shown in FIG. 20; etching is performed in the same process as the second trench 22 to form a third trench 23 under the second trench 22, as shown in fig. 27;
5) The inverted ridge-shaped groove 2 formed by the above process is flattened and smoothed by dry oxidation; then a low stress silicon oxide layer 200 with the thickness not more than 500nm is deposited in the inverted ridge groove by a plasma deposition method, as shown in fig. 28;
6) Removing the silicon oxide layer 100 and the low-stress silicon oxide layer 200 at the junction of the step of the first trench 21 and the optical waveguide region of the device layer by mask lithography, as shown in fig. 29;
7) Growing polysilicon 600 on the surface of the silicon substrate by an epitaxial process until the entire inverted ridge trench is filled, as shown in fig. 30;
8) High-temperature annealing, adjusting the property of epitaxial polycrystalline silicon, and reducing defects to achieve low transmission loss;
9) Flattening the silicon substrate by Chemical Mechanical Polishing (CMP), exposing the clean device layer after CMP, and finally forming an inverted ridge optical waveguide layer 4 in the optical coupling region 12, as shown in fig. 31;
10 A silicon photonics structure is fabricated on the device layer and a low stress silicon oxide layer 200 having a thickness of not more than 500nm is deposited by a plasma deposition method on the surface of the silicon photonics chip functional structure region to form an upper cladding layer 5, as shown in fig. 3. Otherwise, the same as in example 1 was conducted.
The invention is described above by way of example with reference to the accompanying drawings. It will be clear that the invention is not limited to the embodiments described above. As long as various insubstantial improvements are made using the method concepts and technical solutions of the present invention; or the invention is not improved, and the conception and the technical scheme are directly applied to other occasions and are all within the protection scope of the invention.
Claims (8)
1. A silicon photon chip optical coupling structure is used for aligning and coupling a silicon photon chip with a single-mode optical fiber or a laser chip and comprises a silicon substrate (1); a silicon photonic chip functional structure region (11) is arranged on a device layer of the silicon substrate (1), and an optical waveguide region (13) and an optical coupling region (12) are arranged on the silicon photonic chip functional structure region (11); the method is characterized in that: the optical coupling region (12) is provided with an inverted ridge groove (2), and the optical coupling region (12) extends from the end face of the silicon substrate (1) to the optical waveguide region (13); an isolation layer (3) is arranged along the inner wall of the inverted ridge groove (2), an inverted ridge optical waveguide layer (4) is arranged in the inverted ridge groove (2) and above the isolation layer (3), the end face of the inverted ridge optical waveguide layer (4) is in butt joint with an optical fiber or a laser chip, and the other end of the inverted ridge optical waveguide layer is in butt joint with an optical waveguide area (13);
The width of the inverted ridge groove (2) gradually narrows from the end face of the silicon substrate (1) to the optical waveguide region (13); the inverted ridge groove (2) is provided with two layers of grooves downwards from the surface of the silicon substrate (1), a first groove (21) and a second groove (22) are sequentially arranged from top to bottom, the end face widths of the first groove (21) and the second groove (22) are not smaller than the core diameter of an optical fiber or the waveguide width of a laser chip, one end of the first groove (21) is in butt joint with the optical waveguide area (13), the other end of the first groove is in butt joint with the second groove (22), and the width of a joint part with the optical waveguide area (13) is equal to the width of an optical waveguide of a device layer; the length of the second groove (22) is not greater than that of the first groove (21), and the width of the second groove (22) near one end of the optical waveguide area (13) is greater than that of the first groove (21) near one end of the optical waveguide area (13).
2. A silicon photon chip optical coupling structure is used for aligning and coupling a silicon photon chip with a single-mode optical fiber or a laser chip and comprises a silicon substrate (1); a silicon photonic chip functional structure region (11) is arranged on a device layer of the silicon substrate (1), and an optical waveguide region (13) and an optical coupling region (12) are arranged on the silicon photonic chip functional structure region (11); the method is characterized in that: the optical coupling region (12) is provided with an inverted ridge groove (2), and the optical coupling region (12) extends from the end face of the silicon substrate (1) to the optical waveguide region (13); an isolation layer (3) is arranged along the inner wall of the inverted ridge groove (2), an inverted ridge optical waveguide layer (4) is arranged in the inverted ridge groove (2) and above the isolation layer (3), the end face of the inverted ridge optical waveguide layer (4) is in butt joint with an optical fiber or a laser chip, and the other end of the inverted ridge optical waveguide layer is in butt joint with an optical waveguide area (13);
The width of the inverted ridge groove (2) gradually narrows from the end face of the silicon substrate (1) to the optical waveguide region (13); the inverted ridge groove (2) is provided with more than three layers of grooves downwards from the surface of the silicon substrate (1), a first groove (21) and a second groove (22) … … (N) are sequentially arranged from top to bottom, the length of the next layer of groove is not more than that of the previous layer of groove, one end of the next layer of groove, which is close to the optical waveguide area (13), is butted with one end of the previous layer of groove, which is far away from the optical waveguide area (13), one end of the first groove (21), which is close to the optical waveguide area (13), is butted with the optical waveguide area (13), and the width of the joint of the first groove (21) and the optical waveguide area (13) is equal to the width of the optical waveguide area (13); the width of the second groove (22) to the N-th groove (2N) near one end of the optical waveguide region (13) increases gradually layer by layer.
3. The silicon photonics chip light coupling structure of claim 1 or 2 wherein: the isolation layer (3) is made of low-stress silicon oxide, and the inverted ridge optical waveguide layer (4) is made of polysilicon.
4. The silicon photonics chip light coupling structure of claim 1 or 2 wherein: the depth of the inverted ridge groove (2) is 1-1.5 times of the core diameter of the optical fiber.
5. The silicon photonics chip light coupling structure of claim 1 or 2 wherein: the silicon substrate (1) is also provided with an upper cladding layer (5) which covers the surfaces of the inverted ridge optical waveguide layer (4) and the silicon photon chip functional structure area (11);
the material of the upper cladding (5) is low-stress silicon oxide.
6. A method of fabricating a silicon photonics chip optical coupling structure in accordance with any of claims 1 to 5 comprising the steps of:
1) Forming a silicon oxide layer on a silicon substrate by dry oxidation;
2) Depositing a low-stress silicon oxide layer on the silicon oxide layer in the step 1) by a plasma chemical vapor deposition method;
3) Defining the shape of an upper layer ridge region of the inverted ridge optical waveguide of the optical coupling region through mask photoetching, and then etching downwards through a dry plasma etching process to form a first groove of the inverted ridge optical waveguide;
4) Defining the shape of a second layer ridge region of the inverted ridge optical waveguide of the optical coupling region through mask photoetching, and then etching downwards through a dry plasma etching process to form a second groove of the inverted ridge optical waveguide; etching the third groove to the N groove in the same method as the second groove;
5) Dry oxidation to planarize and smooth the inverted ridge trench formed by the above process; then depositing a low-stress silicon oxide layer on the surface of the silicon substrate and in the inverted ridge groove by a plasma deposition method;
6) Removing the low-stress silicon oxide layer at the butt joint position of the first groove step and the optical waveguide region of the device layer through mask photoetching to obtain an isolation layer;
7) Growing polysilicon on the surface of the silicon substrate by an epitaxial process until the whole inverted ridge-shaped groove is filled;
8) High-temperature annealing, adjusting the property of epitaxial polycrystalline silicon, and reducing defects to achieve low transmission loss;
9) Flattening the silicon substrate by Chemical Mechanical Polishing (CMP), exposing the clean device layer after CMP;
10A silicon optical function structure is manufactured, an inverted ridge optical waveguide layer is finally formed in the optical coupling area, and a low-stress silicon oxide layer is deposited on the surface of the functional structure area of the silicon photonic chip through a plasma deposition method, so that an upper cladding layer is formed.
7. The method of fabricating a silicon photonics chip optical coupling structure of claim 6 wherein: step 5) further comprises removing the dry oxide layer of the trench by diluted hydrofluoric acid HF after dry oxidation, and then dry oxidizing until the side wall of the formed inverted ridge trench is smooth.
8. The method of fabricating a silicon photonics chip optical coupling structure of claim 6 wherein: step 9) protecting epitaxial polysilicon of the optical coupling region by mask photoetching, then etching the polysilicon by isotropic chemistry to realize the consistency of the heights of all regions on the surface of the wafer, and then flattening the silicon substrate by CMP.
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| CN103048733A (en) * | 2011-10-14 | 2013-04-17 | 上海圭光科技有限公司 | Conical multilayer ridge waveguide structure and production method thereof |
| CN109358395A (en) * | 2018-12-04 | 2019-02-19 | 苏州易缆微光电技术有限公司 | A kind of novel waveguide face coupling spot-size converter and preparation method thereof |
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| CN109358395A (en) * | 2018-12-04 | 2019-02-19 | 苏州易缆微光电技术有限公司 | A kind of novel waveguide face coupling spot-size converter and preparation method thereof |
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