CN114895094A - Three-stage double isolation voltage sampling method and energy storage BMS device - Google Patents

Abstract

The utility model relates to an energy storage BMS technical field, in particular to a three-section type double-isolation voltage sampling method and an energy storage BMS device, the device comprises a primary voltage division circuit, a secondary voltage division circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip which are connected in sequence, wherein the primary voltage division circuit divides the total voltage of a battery cluster to obtain a first intermediate voltage; the secondary voltage division circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit carries out isolation processing on the second intermediate voltage to obtain a first isolation voltage; the ADC sampling chip obtains a sampling voltage based on the first isolation voltage; the magnetic isolation chip is used for carrying out isolation processing on the sampling voltage to obtain a second isolation voltage; the processing chip calculates and obtains the total voltage of the battery cluster based on the second isolation voltage, and by means of the device, the sampling precision and the safety of the total voltage of the battery cluster can be improved.

Description

Three-stage double isolation voltage sampling method and energy storage BMS device

technical field

The present disclosure relates to the technical field of energy storage BMS, and in particular, to a three-stage double isolation voltage sampling method and an energy storage BMS device.

Background technique

The current energy storage system consists of multiple battery clusters. A single battery cluster consists of multiple batteries connected in series. The battery cluster is equipped with an energy storage BMS (BATTERY MANAGEMENT SYSTEM) device. The energy storage BMS device is used to detect the single cell and the whole cluster. The total voltage, current, temperature and other data of the battery, and the calculation of key parameters such as SOC (State Of Charge, percentage of remaining battery power), SOH (State Of Health, battery health), charge and discharge capacity, etc., and based on detection and calculation As a result, the charge and discharge control, protection and alarm of the battery cluster are carried out. With the development of the energy storage system, in order to further improve the conversion efficiency of the energy storage system, the number of batteries connected in series in the battery cluster is increasing, and the total voltage level of the entire battery cluster is also getting higher and higher, which has been raised from 1000V to 1500V at present.

The current energy storage BMS device is equipped with a battery cluster total voltage detection circuit. After the energy storage BMS device detects the total voltage, it is used to estimate the battery cluster SOC, SOH, charge and discharge capacity, and perform charge and discharge management, protection, and alarm according to the detection and calculation results. Wait. At present, the total voltage detection circuit of the battery cluster in the energy storage BMS device mainly adopts the form of a first-level resistor divider, and the DC high voltage of the battery cluster is converted into the processing chip in the energy storage BMS device through the voltage dividing resistor, such as MCU (Microcontroller Unit, micro control unit) Acceptable DC low voltage analog signal is connected to the ADC pin of the processing chip, and the processing chip performs digital signal conversion on the DC voltage analog through the internal ADC.

However, as the total voltage of the battery cluster increases from 1000V to 1500V, the ADC of the MCU increases the sampling range of 500V, and the sampling accuracy of the total voltage of the battery cluster decreases correspondingly. The estimation of key parameters such as the discharge volume has caused a large error, so that problems such as inaccurate operation of the charge and discharge management strategy, fault protection and alarm malfunction or no action occur.

At the same time, in the current energy storage BMS device's detection circuit for the total voltage of the battery cluster, the total voltage of the battery cluster is divided by a resistor, and the divided low-voltage signal is directly connected to the pins of the processing chip of the energy storage BMS device. , when the battery cluster is interfered by other devices or a shock signal is generated, the interference signal and shock signal will be directly applied to the pins of the processing chip, so as to cause damage to the processing chip.

SUMMARY OF THE INVENTION

The present disclosure aims to solve one of the technical problems in the related art at least to a certain extent. Therefore, the first purpose of the present disclosure is to propose a three-stage double-isolated voltage sampling energy storage BMS device to solve the problems of low sampling accuracy of the total voltage of the battery cluster and low device safety in the prior art.

The second objective of the present disclosure is to propose a three-stage dual isolation voltage sampling method.

In order to achieve the above purpose, the embodiment of the first aspect of the present disclosure provides a three-stage dual-isolation voltage sampling energy storage BMS device, including: a first-stage voltage divider circuit, a second-stage voltage divider circuit, an analog signal isolation circuit, ADC sampling chip, magnetic isolation chip and processing chip, among which,

The first-level voltage divider circuit is connected to the battery cluster, and the first-level voltage divider circuit is used to divide the total voltage of the battery cluster to obtain a first intermediate voltage;

the two-stage voltage divider circuit, configured to divide the first intermediate voltage to obtain a second intermediate voltage;

The analog signal isolation circuit is used for isolating the second intermediate voltage to obtain a first isolation voltage;

the ADC sampling chip for obtaining a sampling voltage based on the first isolation voltage;

The magnetic isolation chip is used for isolating the sampling voltage to obtain a second isolation voltage;

The processing chip is configured to calculate and obtain the total voltage of the battery cluster based on the second isolation voltage.

In an embodiment of the present disclosure, the first-stage voltage divider circuit is connected in parallel with the battery cluster, and the first-stage voltage divider is formed by connecting a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor in series .

In an embodiment of the present disclosure, the two-stage voltage dividing circuit includes a fourth voltage dividing resistor, a fifth voltage dividing resistor, a sixth voltage dividing resistor, a seventh voltage dividing resistor, an eighth voltage dividing resistor and The ninth voltage dividing resistor, the fourth voltage dividing resistor and the fifth voltage dividing resistor are connected in parallel with the first voltage dividing resistor, and the sixth voltage dividing resistor and the seventh voltage dividing resistor are connected with the first voltage dividing resistor. Two voltage dividing resistors are connected in parallel, and the eighth voltage dividing resistor and the ninth voltage dividing resistor are connected in parallel with the third voltage dividing resistor.

In an embodiment of the present disclosure, the analog signal isolation circuit includes a first analog isolator, a second analog isolator, and a third analog isolator, and both ends of the fourth voltage dividing resistor are connected to the first analog isolator Two ends of the sixth voltage dividing resistor are connected to the second analog isolator, and both ends of the eighth voltage dividing resistor are connected to the third analog isolator.

In an embodiment of the present disclosure, the processing chip is configured to: calculate and obtain the second intermediate voltage based on the second isolation voltage, calculate and obtain the first intermediate voltage based on the second intermediate voltage, and calculate the first intermediate voltage based on the second isolation voltage. The first intermediate voltage is calculated to obtain the total voltage of the battery cluster.

In an embodiment of the present disclosure, the models of the first analog isolator, the second analog isolator, and the third analog isolator are all TE6664N.

In an embodiment of the present disclosure, the model of the ADC sampling chip is ADCS8162, and the model of the magnetic isolation chip is BLD7741.

In an embodiment of the present disclosure, the processing chip adopts an MCU chip whose model is GD32F407.

In order to achieve the above purpose, a second aspect of the present disclosure provides a three-stage double-isolation voltage sampling method, which utilizes the three-stage double-isolation voltage sampling energy storage BMS in any of the above embodiments Device implementation, including:

Divide the total voltage of the battery cluster to obtain a first intermediate voltage;

Dividing the first intermediate voltage to obtain a second intermediate voltage;

inputting the second intermediate voltage into an analog signal isolation circuit for isolation to obtain a first isolation voltage;

performing ADC sampling on the first isolation voltage to obtain a sampling voltage;

inputting the sampling voltage into the magnetic isolation chip for isolation to obtain a second isolation voltage;

The total voltage of the battery cluster is calculated based on the second isolation voltage.

In an embodiment of the present disclosure, the calculating and obtaining the total voltage of the battery cluster based on the second isolation voltage includes: calculating and obtaining the second intermediate voltage based on the second isolation voltage, based on the second intermediate voltage The first intermediate voltage is obtained by calculation, and the total voltage of the battery cluster is calculated and obtained based on the first intermediate voltage.

In one or more embodiments of the present disclosure, using a first-stage voltage divider circuit, a second-stage voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip, and a processing chip, which are connected in sequence, the first-stage voltage divider circuit is used for the battery. The total cluster voltage is divided to obtain a first intermediate voltage; the secondary voltage divider circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit performs isolation processing on the second intermediate voltage to obtain a first isolation voltage; ADC The sampling chip obtains the sampling voltage based on the first isolation voltage; the magnetic isolation chip performs isolation processing on the sampling voltage to obtain the second isolation voltage; and the processing chip calculates the total voltage of the battery cluster based on the second isolation voltage. The total voltage of the battery cluster is sampled by the voltage circuit and the two-stage voltage divider circuit, which improves the sampling accuracy of the total voltage of the battery cluster. In addition, the analog signal isolation circuit and the magnetic isolation chip are used for two-stage isolation processing, which improves the performance of the energy storage BMS device. safety.

Additional aspects and advantages of the present disclosure will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the present disclosure.

Description of drawings

The above and/or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is a schematic circuit diagram of the prior art;

FIG. 2 is a block diagram of a three-stage dual-isolation voltage sampling energy storage BMS device according to an embodiment of the present disclosure;

3 is a circuit diagram of a three-stage dual-isolation voltage sampling energy storage BMS device according to an embodiment of the present disclosure;

FIG. 4 is a schematic flowchart of a three-stage dual isolation voltage sampling method according to an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments are not intended to represent all implementations consistent with embodiments of the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of embodiments of the present disclosure, as recited in the appended claims.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structures, materials, or features are included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless expressly and specifically defined otherwise. It will also be understood that, as used in this disclosure, the term "and/or" refers to and includes any and all possible combinations of one or more of the associated listed items.

Embodiments of the present disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present disclosure and should not be construed as a limitation of the present disclosure.

FIG. 1 is a schematic circuit diagram of the prior art. The current energy storage system consists of multiple battery clusters, and a single battery cluster consists of multiple batteries connected in series (see Figure 1). The battery cluster is also equipped with an energy storage BMS device. The total voltage, current, temperature and other data of the cluster battery are calculated, and key parameters such as SOC, SOH, and charge and discharge capacity are calculated at the same time, and the charge and discharge control, protection, and alarm of the battery cluster are performed according to the detection and calculation results. As shown in Fig. 1, the existing energy storage BMS device includes a first-stage resistance voltage dividing structure composed of a voltage dividing resistor Ra and a voltage dividing resistor Rb, and the voltage dividing resistor Ra and the voltage dividing resistor Rb are used to convert the DC high voltage of the battery cluster. The DC low voltage analog signal acceptable to the processing chip in the energy storage BMS device is connected to the ADC pin of the processing chip, and the processing chip performs digital signal conversion on the DC voltage analog through the internal ADC. However, with the development of the energy storage system, in order to further improve the conversion efficiency of the energy storage system, the number of batteries connected in series in the battery cluster is increasing, and the total voltage level of the entire battery cluster is also getting higher and higher. 1500V class. As the total voltage of the battery cluster increases from 1000V to 1500V, the ADC of the processing chip increases the sampling range of 500V, and the sampling accuracy of the total voltage of the battery cluster decreases correspondingly. The estimation of key parameters has resulted in large errors, so that problems such as inaccurate operation of charge and discharge management strategies, fault protection and alarm malfunction or non-action occur. In addition, because the prior art directly connects the divided low-voltage signal to the pins of the processing chip of the energy storage BMS device, when the battery cluster is interfered by other devices or an impulse signal is generated, the interfering signal and impulse signal will It is directly applied to the pins of the processing chip, so that the processing chip is damaged, so that the safety of the energy storage BMS device is not high enough. Therefore, it is very important to improve the sampling accuracy of the total voltage of the battery cluster and the safety of the device.

In the first embodiment, FIG. 2 is a block diagram of a three-stage dual-isolation voltage sampling energy storage BMS device provided by an embodiment of the present disclosure; Circuit diagram of the isolated voltage sampling energy storage BMS device. The three-stage dual-isolation voltage sampling energy storage BMS device involved in the present disclosure may be referred to as an energy storage BMS device for short. The energy storage BMS (BATTERY MANAGEMENT SYSTEM) device is the energy storage battery management device. The three-stage double-isolated voltage sampling energy storage BMS device solves the problems of low sampling accuracy of the total voltage of the battery cluster and low device safety in the prior art.

As shown in FIG. 2 , the three-stage dual isolation voltage sampling energy storage BMS device 10 includes a first-stage voltage divider circuit 11 , a second-stage voltage divider circuit 12 , an analog signal isolation circuit 13 , an ADC sampling chip 14 , a magnetic isolation chip 15 and a processing chip 16. The primary voltage dividing circuit 11 , the secondary voltage dividing circuit 12 , the analog signal isolation circuit 13 , the ADC sampling chip 14 , the magnetic isolation chip 15 and the processing chip 16 are connected in sequence.

In this embodiment, the first-stage voltage divider circuit 11 is connected to the battery cluster. The first-stage voltage dividing circuit 11 is used for dividing the total voltage of the battery cluster to obtain a first intermediate voltage. Specifically, the battery cluster is composed of a plurality of batteries in series, wherein the batteries at both ends are the positive and negative electrodes of the battery cluster respectively, the voltage formed by the positive and negative electrodes of the battery cluster is the total voltage of the battery cluster, and the first-stage voltage divider circuit 11 is connected in parallel with the battery cluster. , and divide the total voltage of the battery cluster. The total voltage of the battery cluster may range from 0 to 1500V. In some embodiments, battery clusters may be included in a three-stage dual-isolated voltage sampling energy storage BMS device 10 .

In this embodiment, the first-stage voltage divider circuit 11 is composed of a plurality of voltage-dividing resistors. At this time, the first-stage voltage-dividing circuit 11 divides the total voltage of the battery cluster into multiple sections, and each voltage-dividing resistor corresponds to a section, that is, each voltage-dividing circuit 11 corresponds to a section. The resistors correspond to a first intermediate voltage, so the number of the first intermediate voltages is the same as the number of voltage dividing resistors in the first-stage voltage dividing circuit 11 .

In some embodiments, the first-stage voltage divider circuit 11 includes three voltage-dividing resistors. At this time, the first-stage voltage divider circuit 11 divides the total voltage of the battery cluster into three sections, and the number of the first intermediate voltages is three. That is, the first intermediate voltage includes the first divided voltage, the second divided voltage and the third divided voltage. As shown in FIG. 3 , the first-stage voltage dividing circuit 11 is formed by connecting a first voltage dividing resistor R1 , a second voltage dividing resistor R2 and a third voltage dividing resistor R3 in series. Specifically, the negative terminal of the first voltage dividing resistor R1 is connected to the negative terminal of the battery cluster, the positive terminal of the first voltage dividing resistor R1 is connected to the negative terminal of the second voltage dividing resistor R2, and the positive terminal of the second voltage dividing resistor R2 is connected to the negative terminal of the third voltage dividing resistor R3. terminal, the positive terminal of the third voltage dividing resistor R3 is connected to the positive terminal of the battery cluster. The first divided voltage is the voltage across the first voltage dividing resistor R1, the second divided voltage is the voltage across the second voltage dividing resistor R2, and the third divided voltage is the voltage across the third voltage dividing resistor R3. In this case, each segment of the total voltage of the battery cluster that is divided into three segments is sampled separately, and the range of the sampling channel is reduced to improve the sampling accuracy.

In this embodiment, the resistance values of the voltage dividing resistors may be the same or different.

In some embodiments, the resistance values of the first voltage dividing resistor R1, the second voltage dividing resistor R2 and the third voltage dividing resistor R3 are equal, and at this time the first voltage dividing resistor R1, the second voltage dividing resistor R2 and the third voltage dividing resistor R1 The piezoresistor R3 equally divides the total voltage of the battery cluster, that is, the first divided voltage, the second divided voltage and the third divided voltage are equal. The resistance values of the first voltage dividing resistor R1 , the second voltage dividing resistor R2 and the third voltage dividing resistor R3 are, for example, 10MΩ.

In this embodiment, the two-stage voltage divider circuit 12 is used to divide the first intermediate voltage to obtain the second intermediate voltage.

In this embodiment, the secondary voltage dividing circuit 12 may be composed of a plurality of voltage dividing resistors. The secondary voltage dividing circuit 12 divides the voltage divided by the primary voltage dividing circuit 11 for secondary voltage dividing through a plurality of voltage dividing resistors. Therefore, the voltage signal is reduced to meet the sampling range of the ADC sampling chip by sampling each segment of the voltage by dividing the voltage by the secondary resistor.

In some embodiments, the secondary voltage divider circuit 12 includes six voltage divider resistors. As shown in FIG. 3 , the secondary voltage dividing circuit 12 includes a fourth voltage dividing resistor R4, a fifth voltage dividing resistor R5, a sixth voltage dividing resistor R6, a seventh voltage dividing resistor R7, and an eighth voltage dividing resistor R8 which are connected in series in sequence. and the ninth voltage divider resistor R9. The fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5 are connected in parallel with the first voltage dividing resistor R1, the sixth voltage dividing resistor R6 and the seventh voltage dividing resistor R7 are connected in parallel with the second voltage dividing resistor R2, and the eighth voltage dividing resistor R8 And the ninth voltage dividing resistor R9 is connected in parallel with the third voltage dividing resistor R3.

Specifically, the secondary voltage dividing circuit 12 divides the voltage across the first voltage dividing resistor R1 through the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5, and the negative end of the fourth voltage dividing resistor R4 is connected to the first voltage dividing resistor R1. The negative end of the voltage dividing resistor R1, the positive end of the fourth voltage dividing resistor R4 is connected to the negative end of the fifth voltage dividing resistor R5, and the positive end of the fifth voltage dividing resistor R5 is connected to the positive end of the first voltage dividing resistor R1; through the sixth voltage dividing resistor R6 , The seventh voltage dividing resistor R7 divides the voltage at both ends of the second voltage dividing resistor R2 for two-stage voltage division, the negative end of the sixth voltage dividing resistor R6 is connected to the negative end of the second voltage dividing resistor R2, and the positive end of the sixth voltage dividing resistor R6 is connected The negative terminal of the seventh voltage dividing resistor R7, the positive terminal of the seventh voltage dividing resistor R7 is connected to the positive terminal of the second voltage dividing resistor R2; the two ends of the third voltage dividing resistor R3 are connected by the eighth voltage dividing resistor R8 and the ninth voltage dividing resistor R9. The voltage is divided into two stages, the negative end of the eighth voltage dividing resistor R8 is connected to the negative end of the third voltage dividing resistor R3, the positive end of the eighth voltage dividing resistor R8 is connected to the negative end of the ninth voltage dividing resistor R9, and the positive end of the ninth voltage dividing resistor R9 The terminal is connected to the positive terminal of the third voltage dividing resistor R3.

In this embodiment, each voltage dividing resistor in the secondary voltage dividing circuit 12 performs secondary voltage dividing on the voltage across the voltage dividing resistor in the corresponding primary voltage dividing circuit 11 , and selects the voltage at both ends of the voltage dividing resistor in the corresponding primary voltage dividing circuit 11 Three voltage dividing resistors, the intermediate voltage after the two voltage dividing resistors is divided into two is used as the second intermediate voltage. At this time, the number of the second intermediate voltage is three, and the second intermediate voltage includes the fourth voltage divider, the third voltage Fives and Sixths. If the fourth voltage dividing resistor R4, the sixth voltage dividing resistor R6 and the eighth voltage dividing resistor R8 are selected, the fourth voltage dividing resistor is the voltage across the fourth voltage dividing resistor R4, and the fifth voltage dividing resistor is the sixth voltage dividing resistor R6 The voltage at both ends, the sixth divided voltage is the voltage at both ends of the eighth voltage dividing resistor R8.

In this embodiment, the resistance values of the voltage dividing resistors may be the same or different.

In some embodiments, the resistance values of the fourth voltage dividing resistor R4, the sixth voltage dividing resistor R6 and the eighth voltage dividing resistor R8 are equal, and the fifth voltage dividing resistor R5, the seventh voltage dividing resistor R7 and the ninth voltage dividing resistor The resistance of R9 is equal. The resistance values of the fourth voltage dividing resistor R4, the sixth voltage dividing resistor R6 and the eighth voltage dividing resistor R8 are, for example, 100KΩ, and the resistance values of the fifth voltage dividing resistor R5, the seventh voltage dividing resistor R7 and the ninth voltage dividing resistor R9 For example, 10MΩ. At this time, the fourth partial pressure, the fifth partial pressure and the sixth partial pressure can be controlled at 0-5V, respectively.

In this embodiment, the analog signal isolation circuit 13 is used to perform isolation processing on the second intermediate voltage to obtain the first isolation voltage.

In this embodiment, the analog signal isolation circuit 13 may be composed of analog isolators, and the number of the analog isolators is consistent with the number of the second intermediate voltage.

In some embodiments, the number of the second intermediate voltages is three, and the number of the analog isolators is three, so the number of the first isolation voltages is three.

In some embodiments, as shown in FIG. 3 , the analog signal isolation circuit 13 includes a first analog isolator U1 , a second analog isolator U2 and a third analog isolator U3 . Both ends of the fourth voltage dividing resistor R4 are connected to the first analog isolator U1, both ends of the sixth voltage dividing resistor R6 are connected to the second analog isolator U2, and both ends of the eighth voltage dividing resistor R8 are connected to the third analog isolator U3. In this case, an analog isolator is used between the analog signal of the battery cluster voltage (ie, the second intermediate voltage) and the analog signal input terminal of the ADC sampling chip to effectively isolate the interference and shock signals, while allowing the three-stage voltage divider Each segment of the signal can match the input range of the ADC sampling chip.

In some embodiments, as shown in FIG. 3 , the models of the first analog isolator U1 , the second analog isolator U2 and the third analog isolator U3 are all TE6664N. The function of the analog isolator model TE6664N is to electrically isolate the DC signal from 0 to 5V. The input voltage is 0 to 5V, and the isolated output is 0 to 5V (ie, the output voltage). The input and the isolated output have a linear correspondence.

In some embodiments, as shown in FIG. 3 , pin 8 of the first analog isolator U1 is the pin of the negative input voltage Vi1-, and pin 9 of the first analog isolator U1 is the pin of the positive input voltage Vi1+ pin; pin 8 of the second analog isolator U2 is the pin of the negative input voltage Vi2-, pin 9 of the second analog isolator U2 is the pin of the positive input voltage Vi2+, and the third analog isolator U3 The No. 8 pin is the pin of the negative input voltage Vi3-, and the No. 9 pin of the third analog isolator U3 is the pin of the positive input voltage Vi3+. The positive end of the fourth voltage dividing resistor R4 is connected to the No. 9 pin of the first analog isolator U1, the negative end of the fourth voltage dividing resistor R4 is connected to the No. 8 pin of the first analog isolator U1; the positive end of the sixth voltage dividing resistor R6 Connect the No. 9 pin of the second analog isolator U2, the negative terminal of the sixth voltage dividing resistor R6 is connected to the No. 8 pin of the second analog isolator U2; the positive terminal of the eighth voltage dividing resistor is connected to the No. 9 pin of the third analog isolator U3 pin No. 8, the negative end of the eighth voltage dividing resistor is connected to pin No. 8 of the third analog isolator U3.

In some embodiments, as shown in FIG. 3 , the No. 2 pin of the first analog isolator U1 is the pin of the negative output voltage Vo1-, and the No. 1 pin of the first analog isolator U1 is the pin of the positive output voltage Vo1+ pin; pin 2 of the second analog isolator U2 is the pin of the negative output voltage Vo2-, pin 1 of the second analog isolator U2 is the pin of the positive output voltage Vo2+, and the third analog isolator U3 The No. 2 pin of the third analog isolator U3 is the pin of the negative output voltage Vo3-, and the No. 1 pin of the third analog isolator U3 is the pin of the positive output voltage Vo3+.

The first analog isolator U1 , the second analog isolator U2 and the third analog isolator U3 receive the fourth, fifth and sixth voltage divisions, respectively, and output the corresponding first isolation voltage after primary isolation.

In this embodiment, the ADC sampling chip 14 is connected to the analog signal isolation circuit 13, and the ADC sampling chip 14 is used to obtain the sampling voltage based on the first isolation voltage. If the number of the first isolation voltages is three, the number of sampling voltages is also three.

In some embodiments, as shown in FIG. 3 , the ADC sampling chip 14 may be an ADC sampling chip U4 whose model is ADCS8162. The function of ADC sampling chip U4 with model ADCS8162 is to convert the input 0-5V analog signal into digital signal, and send the sampling signal (ie digital signal) to the processing chip through SPI (Serial Peripheral Interface) communication.

In some embodiments, as shown in FIG. 3 , pin 49 of the ADC sampling chip U4 is the first input voltage V1 pin, pin 50 of the ADC sampling chip U4 is the first ground pin, and the ADC sampling chip U4 The 51st pin is the second input voltage V2 pin, the 52nd pin of the ADC sampling chip U4 is the second ground pin, the 53rd pin of the ADC sampling chip U4 is the third input voltage V3 pin, the ADC sampling Pin 54 of the chip U4 is the third ground pin. The No. 1 pin of the first analog isolator U1 is connected to the No. 49 pin of the ADC sampling chip U4, and the No. 2 pin of the first analog isolator U1 is connected to the No. 50 pin of the ADC sampling chip U4; the second analog isolator U2 The No. 1 pin of the ADC sampling chip U4 is connected to the No. 51 pin, the No. 2 pin of the second analog isolator U2 is connected to the No. 52 pin of the ADC sampling chip U4; the No. 1 pin of the third analog isolator U3 is connected to The No. 53 pin of the ADC sampling chip U4, and the No. 2 pin of the third analog isolator U3 is connected to the No. 54 pin of the ADC sampling chip U4. The first input voltage V1 pin receives the fourth voltage division after primary isolation, the second input voltage V2 pin receives the fifth voltage division after primary isolation, and the third input voltage V3 pin receives the primary isolation voltage The sixth partial pressure.

引脚，ADC采样芯片U4的24号引脚为第一输出数字信号DOUTA引脚，ADC采样芯片U4的25号引脚为第二输出数字信号DOUTB引脚。In some embodiments, as shown in FIG. 3 , pin 9 of the ADC sampling chip U4 is the first analog-to-digital conversion start CONVSTA pin, and pin 10 of the ADC sampling chip U4 is the second analog-to-digital conversion start CONVSTB pin When pin 9 of ADC sampling chip U4 is connected to pin 10 of ADC sampling chip U4, all channels are sampled synchronously. The 12th pin of the ADC sampling chip U4 is the clock signal SCLK pin (such as the SPI communication clock signal pin), and the 13th pin of the ADC sampling chip U4 is the chip select signal

pin, the No. 24 pin of the ADC sampling chip U4 is the first output digital signal DOUTA pin, and the No. 25 pin of the ADC sampling chip U4 is the second output digital signal DOUTB pin.

In this embodiment, the magnetic isolation chip 15 is used for isolating the sampled voltage to obtain the second isolation voltage. If the number of sampling voltages is also three, the number of second isolation voltages is also three.

In some embodiments, as shown in FIG. 3 , the magnetic isolation chip 15 may be a magnetic isolation chip U5 with a model name of BLD7741. The function of the magnetic isolation chip U5, model BLD7741, is to electrically isolate the SPI communication signal and transmit data through magnetic coupling. In this case, the communication between the ADC sampling chip 14 and the processing chip 16 adopts the magnetic isolation chip 15 to further isolate the analog signal and the digital signal. When the ADC sampling chip 14 is damaged, the normal operation of the processing chip 16 is not affected, so as to ensure the processing chip 16 other functions are available.

In some embodiments, as shown in FIG. 3 , the No. 11 pin of the magnetic isolation chip U5 is the primary side input signal VID pin, and the No. 12 pin of the magnetic isolation chip U5 is the primary side third output signal VOC pin, The No. 13 pin of the magnetic isolation chip U5 is the VOB pin of the second output signal of the primary side, the No. 14 pin of the magnetic isolation chip U5 is the VOA pin of the first output signal of the primary side, and the No. 6 pin of the magnetic isolation chip U5 is Secondary side output signal VOD pin, magnetic isolation chip U5 pin 5 is the secondary side third input signal VIC pin, magnetic isolation chip U5 pin 3 is the secondary side second input signal VIB pin, magnetic isolation The No. 2 pin of the chip U5 is the first input signal VIA pin of the secondary side.

In this embodiment, the processing chip 16 is configured to calculate and obtain the total voltage of the battery cluster based on the second isolation voltage.

In some embodiments, as shown in FIG. 3 , the processing chip 16 may be an MCU chip U6 whose model is GD32F407. The 41st pin of the MCU chip U6 is the clock signal SPIO-CLK pin, the 42nd pin of the MCU chip U6 is the signal input SPIO-MISO pin (that is, the data receiving pin of the SPI0 communication), and the 43rd pin of the MCU chip U6 The pin is the AD-CONVST pin of the analog-to-digital conversion control signal, and the 40th pin of the MCU chip U6 is the chip selection signal CS pin.

In this embodiment, the processing chip is used for: calculating the second intermediate voltage based on the second isolation voltage, calculating the first intermediate voltage based on the second intermediate voltage, and calculating the total voltage of the battery cluster based on the first intermediate voltage.

Specifically, if the number of the second isolation voltages is three, for example, the second isolation voltage includes a first magnetic isolation voltage Va, a second magnetic isolation voltage Vb and a third magnetic isolation voltage Vc, and the processing chip is based on the first magnetic isolation voltage Va , the second magnetic isolation voltage Vb and the third magnetic isolation voltage Vc obtain the fourth divided voltage after primary isolation, the fifth divided voltage after primary isolation, and the sixth divided voltage after primary isolation. There is a linear correspondence between the input and the isolated output, and then the fourth, fifth and sixth partial pressures are obtained, and the first, second and third partial pressures are further obtained according to the principle of resistance division. The total voltage of the battery cluster can be obtained by summing up the first partial pressure, the second partial pressure and the third partial pressure.

In some embodiments, as shown in FIG. 3 , the connection mode of the ADC sampling chip U4, the magnetic isolation chip U5, and the MCU chip U6 is as follows: pins 24 and 25 of the ADC sampling chip U4 are connected to the pins of the magnetic isolation chip U5. Pin 11, pin 13 of ADC sampling chip U4 is connected to pin 12 of magnetic isolation chip U5; pin 12 of ADC sampling chip U4 is connected to pin 13 of magnetic isolation chip U5; ADC sampling chip Pins 9 and 10 of U4 are connected to pin 14 of the magnetic isolation chip U4. The No. 6 pin of the magnetic isolation chip U5 is connected to the No. 42 pin of the MCU chip U6; the No. 5 pin of the magnetic isolation chip U5 is connected to the No. 40 pin of the MCU chip U6; the No. 4 pin of the magnetic isolation chip U5 is connected To pin 41 of MCU chip U6; pin 3 of magnetic isolation chip U5 is connected to pin 43 of MCU chip U6.

The process for the MCU chip U6 to obtain the data output by the ADC sampling chip U4 includes: connecting the No. 40 pin of the MCU chip U6 to the No. 5 pin of the magnetic isolation chip U5, after signal isolation, through the 12 pin of the magnetic isolation chip U5 Pin No. 13 is output to pin No. 13 of ADC sampling chip U4, which is the chip selection signal of ADC sampling chip U4, and is controlled by No. 40 pin of MCU chip U6; No. 41 pin of MCU chip U6 is connected to the magnetic The No. 4 pin of the isolation chip U5, after signal isolation, is output to the No. 12 pin of the ADC sampling chip U4 through the No. 13 pin of the magnetic isolation chip U5. This signal is the SPI communication clock signal of the ADC sampling chip U4. Pin 41 of the MCU chip U6 sends a clock signal to synchronize the SPI clock; pin 43 of the MCU chip U6 is connected to the pin 3 of the magnetic isolation chip U5, after signal isolation, it passes through the 14 pin of the magnetic isolation chip U5. The No. 1 pin is output to No. 9 and No. 10 pins of ADC sampling chip U4. These two pins are the control pins for converting the analog signal of ADC sampling chip U4 into digital signal, and are controlled by No. 43 pin of MCU chip U6. Control; when the voltage needs to be read, pin 41 of the MCU chip U6 sends a clock signal to synchronize the SPI communication clock of the ADC sampling chip U4 with the SPI communication clock of the MCU chip U6; the MCU chip U6 controls its pin 40 The level is low, and is applied to pin 13 of the ADC sampling chip U4 through the magnetic isolation chip U5, so that the ADC sampling chip U4 is in an effective working state; the MCU chip U6 controls its pin 43 to be a high level, through the The magnetic isolation chip U5 is applied to the pins 9 and 10 of the ADC sampling chip U4 to convert the analog signal into a digital signal and finally send it out through the pins 24 and 25 of the ADC sampling chip U4. The magnetic isolation chip U5 is isolated and sent to pin 42 of the MCU chip.

Combined with the energy storage BMS device battery cluster total voltage sampling method shown in Figure 3, the sampling method is as follows:

The total voltage of the battery cluster is divided by the first-level voltage divider circuit, wherein the first voltage divider resistor R1, the second voltage divider resistor R2, and the third voltage divider resistor R3 have the same resistance values, and the total voltage of the battery cluster is equally divided; the fourth voltage divider resistor R4 and the fifth voltage dividing resistor R5 perform secondary voltage division on the voltage across the first voltage dividing resistor R1, and the sixth voltage dividing resistor R6 and the seventh voltage dividing resistor R7 perform secondary voltage division on the voltage across the second voltage dividing resistor R2 voltage divider, the eighth voltage divider resistor R8 and the ninth voltage divider resistor R9 perform secondary voltage divider on the voltage across the third voltage divider resistor R3;

After the secondary voltage division, the negative terminal of the fourth voltage dividing resistor R4 is connected to the No. 8 pin of the first analog isolator U1, the positive terminal of the fourth voltage dividing resistor R4 is connected to the No. 9 pin of the first analog isolator U1, and the third voltage dividing resistor R4 is connected to the No. The voltage across the four voltage divider resistor R4 is isolated by the first analog isolator U1 and then output from pins 1 and 2 of the first analog isolator U1 to pins 49 and 50 of the ADC sampling chip U4 ; The negative terminal of the sixth voltage dividing resistor R6 is connected to the No. 8 pin of the second analog isolator U2, the positive terminal of the sixth voltage dividing resistor R6 is connected to the No. 9 pin of the second analog isolator U2, and the sixth voltage dividing resistor R6 is two. After being isolated by the second analog isolator U2, the terminal voltage is output from pins 1 and 2 of the second analog isolator U2 to pins 51 and 52 of the ADC sampling chip U4; the eighth voltage dividing resistor The negative terminal of R8 is connected to the No. 8 pin of the third analog isolator U3, the positive terminal of the eighth voltage dividing resistor R8 is connected to the No. 9 pin of the third analog isolator U3, and the voltage across the eighth voltage dividing resistor R8 is simulated by the third analog isolator. After the isolator U3 is isolated, pins 1 and 2 of the third analog isolator U3 are output to pins 53 and 54 of the ADC sampling chip U4;

The analog signal input range of pins 49 and 50, pins 51 and 52, and pins 53 and 54 of ADC sampling chip U4 is 0~5V, and the fourth, fifth and sixth voltage divisions are corresponding to The analog isolator is isolated and input to the ADC sampling chip U4 for conversion, converted into a digital signal, and sent to the magnetic isolation chip U5 pin 11 through the signal output of pins 24 and 25 of the ADC sampling chip U4, After signal isolation (such as SPI communication signal isolation), it is output to pin 42 of MCU chip U6 through pin 6 of magnetic isolation chip U5;

After the MCU chip U6 receives the data sent by the ADC sampling chip U4, it processes it to determine the fourth, fifth and sixth voltage divisions. Since the ADC sampling chip U4 with the model ADCS8162 is a 16-bit ADC sampling chip, The analog signal input range of pins 49 and 50, pins 51 and 52, and pins 53 and 54 of its analog signal input channels is 0 to 5V, and the corresponding digital signal output is 0 to 65535. Further conversion is performed to determine the fourth partial pressure after primary isolation, the fifth partial pressure after primary isolation, and the sixth partial pressure after primary isolation; the calculation formula is as follows:

The fourth divided voltage after the first-level isolation = the digital signal value of the current channel ÷ 65535 × 5V

The fifth voltage divider after the first-level isolation = the digital signal value of the current channel ÷ 65535 × 5V

The sixth voltage divider after first-level isolation = current channel digital signal value ÷ 65535×5V

The voltages of the fourth divided voltage, the fifth divided voltage and the sixth divided voltage are obtained based on the voltage values of the fourth divided voltage after the primary isolation, the fifth divided voltage after the primary isolation, and the sixth divided voltage after the primary isolation The input and output voltages of the analog isolator model TE6664N are the same, so the fourth partial pressure is equal to the fourth partial pressure after the first-level isolation, the fifth partial pressure is equal to the fifth partial pressure after the first-level isolation, and the sixth partial pressure The voltage is equal to the sixth divided voltage after the first-level isolation, thereby determining the voltage across the fourth voltage dividing resistor R4, the voltage across the sixth voltage dividing resistor R6 and the voltage across the eighth voltage dividing resistor R8;

According to the principle of resistance division, based on the voltage across the fourth voltage dividing resistor R4, the voltage across the sixth voltage dividing resistor R6 and the voltage across the eighth voltage dividing resistor R8, the voltage across the first voltage dividing resistor R1 and the second voltage dividing resistor R1 are obtained. The voltage across the piezoresistor R2 and the voltage across the third voltage dividing resistor R3 are calculated as follows:

The voltage across the first voltage dividing resistor R1=the voltage across the fourth voltage dividing resistor R4÷R4×(R4+R5)

The voltage across the second voltage dividing resistor R2=the voltage across the sixth voltage dividing resistor R6÷R6×(R6+R7)

The voltage across the third voltage dividing resistor R3=the voltage value across the eighth voltage dividing resistor R8÷R8×(R8+R9)

The total voltage of the battery cluster is obtained by summing the voltage across the first voltage dividing resistor R1, the voltage across the second voltage dividing resistor R2, and the voltage across the third voltage dividing resistor R3.

In the three-stage dual-isolation voltage sampling energy storage BMS device of the present disclosure, a first-stage voltage divider circuit, a second-stage voltage divider circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip, and a processing chip are connected in sequence. The secondary voltage divider circuit divides the total voltage of the battery cluster to obtain a first intermediate voltage; the secondary voltage divider circuit divides the first intermediate voltage to obtain a second intermediate voltage; the analog signal isolation circuit isolates the second intermediate voltage to obtain The first isolation voltage; the ADC sampling chip obtains the sampling voltage based on the first isolation voltage; the magnetic isolation chip performs isolation processing on the sampling voltage to obtain the second isolation voltage; the processing chip calculates the total voltage of the battery cluster based on the second isolation voltage, in this case In the next step, the first-stage voltage divider circuit and the second-stage voltage divider circuit are used to sample the total voltage of the battery cluster in segments, which improves the sampling accuracy of the total voltage of the battery cluster. The safety of the energy storage BMS device is improved, and the failure rate is reduced. In addition, the range of the total voltage of the battery cluster of the present disclosure is 0-1500V, and the first-stage voltage divider circuit includes three voltage-dividing resistors with equal resistance values, so the energy storage BMS device of the present disclosure is a kind of high-precision 0-1500V DC capable of supporting The three-stage double-isolated voltage sampling energy storage BMS device adopts a three-stage voltage divider structure, which divides the total voltage of the 0-1500V battery cluster into three sections on average, and then samples the three sections of voltage separately, reducing the number of single sampling channels. Range, by sampling the voltage of each segment by the second-level resistor divider, the voltage signal is reduced to meet the sampling range of the ADC sampling chip. It has the characteristics of simple system and high sampling accuracy. Compared with traditional sampling devices, the accuracy can reach ± within 0.1%. At the same time, the present disclosure adopts two-level isolation technology to perform one-level isolation for analog signals, and performs digital signal isolation for SPI communication signals after the ADC sampling chip, which greatly improves the anti-interference ability and security.

The following is an embodiment of the method of the present disclosure. For details not disclosed in the embodiment of the method of the present disclosure, please refer to the embodiment of the apparatus of the present disclosure. The method embodiment of the present disclosure proposes a three-stage dual isolation voltage sampling method. The three-stage double-isolation voltage sampling method adopts the three-stage double-isolation voltage sampling energy storage BMS device of the above device embodiment to realize voltage sampling.

FIG. 4 is a schematic flowchart of a three-stage dual isolation voltage sampling method according to an embodiment of the present disclosure. The three-stage dual isolation voltage sampling method includes:

S101, divide the total voltage of the battery cluster to obtain a first intermediate voltage.

In step S101, a first intermediate voltage is obtained by dividing the total voltage of the battery cluster by a first-stage voltage dividing circuit. The range (ie range) of the total voltage of the battery cluster is 0 to 1500V. For details, refer to the relevant descriptions in the foregoing apparatus embodiments, which are not repeated here.

S102: Divide the first intermediate voltage to obtain a second intermediate voltage.

In step S102, the second intermediate voltage is obtained by dividing the first intermediate voltage by the secondary voltage dividing circuit. For details, refer to the relevant descriptions in the foregoing apparatus embodiments, which are not repeated here.

S103, the second intermediate voltage is input into the analog signal isolation circuit for isolation to obtain a first isolation voltage.

In step S103, the analog signal isolation circuit may be composed of a plurality of analog isolators. For details, refer to the relevant descriptions in the foregoing apparatus embodiments, which are not repeated here.

S104, ADC sampling is performed on the first isolation voltage to obtain a sampling voltage.

In step S104, ADC sampling is performed on the first isolation voltage by an ADC sampling chip to obtain a sampling voltage. For details, refer to the relevant descriptions in the foregoing apparatus embodiments, which are not repeated here.

S105, the sampling voltage is input into the magnetic isolation chip for isolation to obtain a second isolation voltage.

S106, calculate and obtain the total voltage of the battery cluster based on the second isolation voltage.

In step S106, the total voltage of the battery cluster is obtained through calculation by the processing chip. Wherein, calculating the total voltage of the battery cluster based on the second isolation voltage includes: calculating the second intermediate voltage based on the second isolation voltage, calculating the first intermediate voltage based on the second intermediate voltage, and calculating the total battery cluster based on the first intermediate voltage. Voltage. For details, refer to the relevant descriptions in the foregoing apparatus embodiments, which are not repeated here.

It should be noted that the foregoing explanations on the embodiment of the three-stage double-isolation voltage sampling energy storage BMS device are also applicable to the three-stage double-isolation voltage sampling method in this embodiment, and are not repeated here.

The above-mentioned serial numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

In the three-stage dual isolation voltage sampling method of the present disclosure, the total voltage of the battery cluster is divided to obtain a first intermediate voltage; the first intermediate voltage is divided to obtain a second intermediate voltage; and the second intermediate voltage is isolated Obtain the first isolation voltage; obtain the sampled voltage based on the first isolation voltage; perform isolation processing on the sampled voltage to obtain the second isolation voltage; calculate the total voltage of the battery cluster based on the second isolation voltage. The multi-stage sub-sampling of the voltage improves the sampling accuracy of the total voltage of the battery cluster, and the safety of the energy storage BMS device is improved through two-stage isolation processing. In addition, the range of the total voltage of the battery cluster is 0~1500V. The total voltage of the battery cluster is sampled in sections, which reduces the range of a single sampling channel, and the sampling accuracy is high. Compared with the traditional sampling method, the accuracy can reach within ±0.1%. Meanwhile, the present disclosure adopts the two-stage isolation technology to isolate the analog signal of each voltage detection first, and then isolate the digital signal sampled by the ADC. The system has high security and strong anti-interference ability.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present disclosure can be executed in parallel, sequentially or in different orders, and the present disclosure is not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present disclosure should be included within the protection scope of the present disclosure.

Claims (10)

1. A three-section double-isolation voltage sampling energy storage BMS device is characterized by comprising a primary voltage division circuit, a secondary voltage division circuit, an analog signal isolation circuit, an ADC sampling chip, a magnetic isolation chip and a processing chip which are connected in sequence,

the primary voltage division circuit is connected with the battery cluster and used for dividing the total voltage of the battery cluster to obtain a first intermediate voltage;

the secondary voltage division circuit is used for dividing the first intermediate voltage to obtain a second intermediate voltage;

the analog signal isolation circuit is used for carrying out isolation processing on the second intermediate voltage to obtain a first isolation voltage;

the ADC sampling chip is used for obtaining a sampling voltage based on the first isolation voltage;

the magnetic isolation chip is used for carrying out isolation processing on the sampling voltage to obtain a second isolation voltage;

and the processing chip is used for calculating the total voltage of the battery cluster based on the second isolation voltage.

2. The three-stage, dual-isolation voltage sampling energy storage BMS device of claim 1, wherein said primary voltage dividing circuit is connected in parallel with said battery cluster, said primary voltage dividing circuit being formed by a first voltage dividing resistor, a second voltage dividing resistor and a third voltage dividing resistor in series.

3. The three-stage double-isolation voltage sampling energy storage BMS device of claim 2, wherein the secondary voltage dividing circuit comprises a fourth voltage dividing resistor, a fifth voltage dividing resistor, a sixth voltage dividing resistor, a seventh voltage dividing resistor, an eighth voltage dividing resistor and a ninth voltage dividing resistor which are sequentially connected in series, the fourth voltage dividing resistor and the fifth voltage dividing resistor are connected in parallel with the first voltage dividing resistor, the sixth voltage dividing resistor and the seventh voltage dividing resistor are connected in parallel with the second voltage dividing resistor, and the eighth voltage dividing resistor and the ninth voltage dividing resistor are connected in parallel with the third voltage dividing resistor.

4. The three-stage, dual isolated voltage sampling energy storage BMS device of claim 3, wherein: the analog signal isolation circuit comprises a first analog isolator, a second analog isolator and a third analog isolator,

and two ends of the fourth divider resistor are connected with the first analog isolator, two ends of the sixth divider resistor are connected with the second analog isolator, and two ends of the eighth divider resistor are connected with the third analog isolator.

5. The three-stage, dual isolated voltage sampling energy storage BMS device of claim 1, wherein: the processing chip is used for:

and calculating to obtain the second intermediate voltage based on the second isolation voltage, calculating to obtain the first intermediate voltage based on the second intermediate voltage, and calculating to obtain the total voltage of the battery cluster based on the first intermediate voltage.

6. The three-stage, dual isolated voltage sampling energy storage BMS device of claim 4, wherein: the models of the first analog isolator, the second analog isolator and the third analog isolator are TE 6664N.

7. The three-stage, dual isolated voltage sampling energy storage BMS device of claim 1, wherein: the model of the ADC sampling chip is ADCS8162, and the model of the magnetic isolation chip is BLD 7741.

8. The three-stage, double isolated voltage sampling energy storage BMS device of claim 1 or 7, characterized in that: the processing chip adopts an MCU chip with the model of GD32F 407.

9. A three-stage double-isolated voltage sampling method implemented by the three-stage double-isolated voltage sampling energy storage BMS device according to any one of claims 1 to 8, comprising:

dividing the total voltage of the battery cluster to obtain a first intermediate voltage;

dividing the first intermediate voltage to obtain a second intermediate voltage;

inputting the second intermediate voltage into an analog signal isolation circuit for isolation to obtain a first isolation voltage;

performing ADC (analog-to-digital converter) sampling on the first isolation voltage to obtain a sampling voltage;

inputting the sampling voltage into a magnetic isolation chip for isolation to obtain a second isolation voltage;

and calculating the total voltage of the battery cluster based on the second isolation voltage.

10. The three-stage double-isolation voltage sampling method of claim 9, wherein the calculating the total voltage of the battery cluster based on the second isolation voltage comprises:

and calculating to obtain the second intermediate voltage based on the second isolation voltage, calculating to obtain the first intermediate voltage based on the second intermediate voltage, and calculating to obtain the total voltage of the battery cluster based on the first intermediate voltage.

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