CN114864615A - Method for manufacturing image sensor - Google Patents

Abstract

The invention provides a manufacturing method of an image sensor, which sequentially comprises the following steps: providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic area and reserving the silicon nitride layer covering the pixel area; performing an ion implantation process of the logic region; removing the silicon nitride layer covering the pixel region; and performing an ion implantation process of the pixel region. The method removes the silicon nitride layer covering the logic area, reserves the silicon nitride layer covering the pixel area, removes the silicon nitride layer covering the pixel area after the ion implantation process of the logic area is completed, and utilizes the silicon nitride layer reserved in the pixel area as a protective layer, thereby effectively reducing the pollution and physical damage of the processing procedure of the logic area to the pixel area and improving the quality of the image sensor.

Description

How to make an image sensor

technical field

The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a manufacturing method of an image sensor.

Background technique

A CMOS image sensor is a semiconductor device that converts optical images into electrical signals. CMOS image sensors are integrated on metal oxide semiconductor materials and are widely used in digital cameras, camera phones, digital video cameras, medical imaging devices (eg gastroscopes), and automotive imaging devices.

A CMOS image sensor usually includes a pixel area and a peripheral logic area. For a CMOS image sensor, the characteristics of the pixel area used for light-sensing directly determine the performance of the final image sensor. The performance parameters of image sensors include quantum efficiency, dark current, dynamic range, and signal-to-noise ratio. Therefore, the fabrication of the pixel area is very important. When the logic area is processed in a conventional process, the pixel area will be completely exposed, or only a thin layer of silicon oxide will protect the surface of the pixel area. The contamination and physical damage brought by the logic area process will inevitably affect the pixel area, thereby forming pixel defects (such as dead pixels, noise, etc.).

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a manufacturing method of an image sensor, which can reduce the pollution and physical damage to the pixel area caused by the logic area processing process, and improve the quality of the image sensor.

The present invention provides a method for manufacturing an image sensor, comprising:

a substrate is provided, the substrate includes a pixel area and a logic area; a silicon oxide layer covering the pixel area and the logic area is formed on the surface of the substrate; a silicon nitride layer covering the silicon oxide layer is formed ; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;

removing the silicon nitride layer covering the logic region and retaining the silicon nitride layer covering the pixel region;

performing an ion implantation process for the logic region;

removing the silicon nitride layer covering the pixel area;

An ion implantation process for the pixel region is performed.

Further, after forming the shallow trench isolation, the method further includes:

forming a first protective layer, the first protective layer covering the silicon nitride layer and the surface of the shallow trench isolation;

In the step of removing the silicon nitride layer covering the logic region, the first protection layer covering the logic region is also removed, and the first protection layer covering the pixel region remains.

Further, the first protective layer includes at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer, and a polysilicon layer.

Further, after forming the shallow trench isolation, the method further includes:

forming an isolation layer, the isolation layer covers the surface of the silicon nitride layer and the shallow trench isolation, and the material of the isolation layer includes a silicon oxide layer and/or a silicon oxynitride layer;

In the step of removing the silicon nitride layer covering the logic region, the isolation layer covering the logic region is also removed, and the isolation layer covering the pixel region remains.

Further, removing the silicon nitride layer covering the logic region and retaining the silicon nitride layer covering the pixel region, specifically including:

forming a first photoresist layer, the first photoresist layer covering the pixel region and exposing the logic region;

Using the first photoresist layer as a mask, dry or wet etching is performed to remove the silicon nitride layer covering the logic region.

Further, the logic region includes a first logic region and a second logic region; and performing an ion implantation process for the logic region specifically includes:

forming a second photoresist layer, the second photoresist layer covering the pixel area and the second logic area, exposing the first logic area, using the second photoresist layer as a mask, to performing P-type ion implantation on the first logic region to form a P-type well region in the first logic region; removing the second photoresist layer;

forming a third photoresist layer, the third photoresist layer covering the pixel area and the first logic area, exposing the second logic area, using the third photoresist layer as a mask, to N-type ion implantation is performed on the second logic region to form an N-type well region in the second logic region; and the third photoresist layer is removed.

Further, performing the ion implantation process in the pixel region specifically includes: performing P-type ion implantation on the pixel region to form a P-type well region on one side of the shallow trench isolation;

N-type ion implantation is performed on the pixel region to form an N region of the photodiode on the other side of the shallow trench isolation.

Further, it also includes:

forming gates corresponding to different transistors in the pixel region and the logic region;

Ion implantation is performed into the substrate on both sides of the gate to form the source and drain corresponding to each transistor and the P region on the surface of the photodiode.

The present invention also provides a manufacturing method of an image sensor, which sequentially includes the following steps:

a substrate is provided, the substrate includes a pixel area and a logic area; a silicon oxide layer covering the pixel area and the logic area is formed on the surface of the substrate; a silicon nitride layer covering the silicon oxide layer is formed ; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;

removing the silicon nitride layer covering the logic region and the pixel region;

forming a second protective layer, the second protective layer covering the surface of the silicon oxide layer and the shallow trench isolation;

removing the second protective layer covering the logic region and retaining the second protective layer covering the pixel region;

performing an ion implantation process for the logic region;

removing the second protective layer covering the pixel area;

An ion implantation process for the pixel region is performed.

Further, the second protective layer includes at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer, and a polysilicon layer.

Compared with the prior art, the present invention has the following beneficial effects:

The invention provides a method for fabricating an image sensor, which sequentially includes the following steps: providing a substrate, the substrate including a pixel region and a logic region; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon oxide covering forming a shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic area, leaving the silicon nitride layer covering the pixel area; performing the Ion implantation process; removing the silicon nitride layer covering the pixel area; performing an ion implantation process in the pixel area. In the present invention, the silicon nitride layer covering the logic region is removed, and the silicon nitride layer covering the pixel region is retained. After the ion implantation process in the logic region is completed, the silicon nitride layer covering the pixel region is removed, and the nitrided silicon nitride layer retained in the pixel region is used. The silicon layer is used as a protective layer, thereby effectively reducing the pollution and physical damage to the pixel area caused by the logic area processing process, and improving the quality of the image sensor.

Description of drawings

FIG. 1 is a schematic flowchart of a method for fabricating an image sensor according to an embodiment of the present invention.

2a to FIG. 9 are schematic diagrams of steps of a manufacturing method of an image sensor according to a first embodiment of the present invention.

FIG. 10 is a schematic circuit diagram of an image sensor of the present invention.

11 to 12 are schematic diagrams of a manufacturing method of an image sensor according to a second embodiment of the present invention.

13 to 14 are schematic diagrams of another method for fabricating an image sensor according to the present invention.

Among them, the reference numerals are as follows:

10-substrate; 11-shallow trench isolation; 12-silicon oxide layer; 13-silicon nitride layer; 13a-silicon nitride layer in pixel area; 13b-silicon nitride layer in logic area; 14-first light 15-second photoresist layer; 16-third photoresist layer; 17-fourth photoresist layer; 18-photodiode N region; 19-photodiode surface P region (pinning layer); X-pixel region; L-logic region; I-first logic region; II-second logic region; 21-P-type well region; 22-N-type well region; 23-P-type well region; 24-isolation layer; 31, 32 , 33, 34-gate; 25-first protective layer; 45-second protective layer; 41, 43, 44-source; 42, 51, 53, 54-drain.

Detailed ways

Embodiments of the present invention provide a method for fabricating an image sensor. The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

For the convenience of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc., to describe an element as shown in the drawings of the embodiments or the relationship of a component to another (or other) elements or components. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. The terms "first," "second," etc. hereinafter are used to distinguish between similar elements, and are not necessarily used to describe a particular order or temporal order. It is to be understood that these terms so used may be substituted under appropriate circumstances.

An embodiment of the present invention provides a method for manufacturing an image sensor, as shown in FIG. 1 , which sequentially includes the following steps:

Step S1, providing a substrate including a pixel region and a logic region; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming nitrogen covering the silicon oxide layer a silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;

Step S2, removing the silicon nitride layer covering the logic region, and retaining the silicon nitride layer covering the pixel region;

Step S3, performing the ion implantation process of the logic region;

Step S4, removing the silicon nitride layer covering the pixel area;

Step S5, performing an ion implantation process in the pixel region.

2a to 9 are schematic diagrams of steps of a method for fabricating an image sensor according to a first embodiment of the present invention. FIG. 10 is a schematic circuit diagram of an image sensor according to an embodiment of the present invention. The steps of the wafer processing method according to the embodiment of the present invention will be described in detail below with reference to FIG. 2 to FIG. 10 .

Fig. 2a is a schematic top view of the image sensor according to the first embodiment of the present invention; Fig. 2b is a schematic cross-sectional view corresponding to AA' in Fig. 2a. As shown in FIGS. 2a and 2b, a substrate 10 is provided, the substrate 10 includes a pixel area X and a logic area L, exemplarily, the logic area L surrounds the pixel area X. A silicon oxide layer 12 covering the pixel region X and the logic region L is formed on the surface of the substrate 10 , a silicon nitride layer 13 is formed on the surface of the silicon oxide layer 12 , correspondingly, a silicon nitride layer 13 includes a silicon nitride layer 13a in the pixel region and a silicon nitride layer 13b in the logic region. Etch the silicon nitride layer 13, the silicon oxide layer 12 and the substrate 10 with a partial thickness to form trenches, fill the trenches with oxide to form a shallow trench isolation (STI) 11, and perform chemical mechanical polishing (CMP) to make the shallow trenches The upper surfaces of trench isolation (STI) 11 and silicon nitride layer 13 are flush.

As shown in FIG. 3 a , a first photoresist layer 14 is formed, the first photoresist layer 14 covers the pixel region X and exposes the logic region L. Using the first photoresist layer ₁₄ as a mask, dry or wet etching is performed to remove the silicon _nitride layer 13b covering the logic region. The silicon nitride layer 13b of the logic region. In other examples, the silicon nitride layer 13b of the logic region may be removed by dry etching using reactive ion etching with a mixed gas of fluorine gas and oxygen gas. In other examples, before forming the first photoresist layer 14, the overall thickness of the silicon nitride layer 13 can also be thinned according to actual needs. etching process.

As shown in FIG. 3a and FIG. 3b, optionally, after chemical mechanical polishing (CMP) makes the upper surface of the shallow trench isolation (STI) 11 and the silicon nitride layer 13 flush, an isolation layer 24 can also be formed, and the isolation layer 24 covers the upper surface of the silicon nitride layer 13 and the shallow trench isolation (STI) 11, and then a first photoresist layer 14 is formed on the isolation layer 24, and the first photoresist layer 14 is used as a mask to remove the The silicon nitride layer 13b of the logic region. In one example, the isolation layer 24 may be formed by a regrown silicon oxide layer or a silicon oxynitride layer; in another example, the isolation layer 24 may be formed by oxidizing the surface of the silicon nitride layer 13 . The isolation layer 24 plays an isolation role between the silicon nitride layer 13 and the first photoresist layer 14 and an anti-reflection role in the photolithography process. The isolation layer 24 and the silicon nitride layer 13b covering the logic regions are removed by etching.

As shown in FIG. 3 a and FIG. 4 , the first photoresist layer 14 is removed by an ashing process, and wet cleaning is performed to remove particulate impurities or residues formed by the ashing and/or etching processes.

As shown in FIG. 5 , an NMOS transistor and a PMOS transistor can be formed in the logic region L, the NMOS transistor is formed in the P-type well region, and the PMOS transistor is formed in the N-type well region. The logic area L includes a first logic area I and a second logic area II. The first logic region I is used to form a P-type well region, for example, and the second logic region is used to form an N-type well region, for example. In other examples, the first logic region can also be used to form an N-type well region, and the second logic region can be used to form a P-type well region, which can be configured according to actual needs. A second photoresist layer 15 is formed, the second photoresist layer 15 covers the pixel area X and the second logic area II of the logic area, and exposes the first logic area I of the logic area. Using the second photoresist layer 15 as a mask, ion implantation is performed on the first logic region I, such as implanting high-energy boron ions to form a P-type well region 21, which is used to manufacture an NMOS transistor, and then the second photoresist layer 15 is removed by an ashing process. .

As shown in FIG. 6 , a third photoresist layer 16 is formed. The third photoresist layer 16 covers the pixel area X and the first logic area I of the logic area, and exposes the second logic area II of the logic area. Using the third photoresist layer 16 as a mask, ion implantation is performed on the second logic region II, for example, N-type ions are implanted to form an N-type well region 22 for manufacturing a PMOS transistor; the N-type ions can be arsenic ions or phosphorus ions ions, but not limited to this. The third photoresist layer 16 is then removed by an ashing process.

As shown in FIG. 7 , to remove the silicon nitride layer 13a in the pixel area, wet or dry processes can be used to remove, for example, hot phosphoric acid (H ₃ PO ₄ ) wet etching is used to remove the silicon nitride layer 13a in the pixel area. . In other examples, the silicon nitride layer 13a in the pixel region may be removed by dry etching using reactive ion etching containing a mixed gas of fluorine gas and oxygen gas.

As shown in FIG. 8, the ion implantation process of the pixel region is performed. Specifically, a fourth photoresist layer 17 is formed, and the fourth photoresist layer 17 covers parts of the logic region L and the pixel region X. Using the fourth photoresist layer 17 as a mask, ion implantation is performed on the pixel region X, for example, P-type ion implantation is performed on the pixel region to form a P-type well region 23 on one side of the shallow trench isolation 11 . N-type ion implantation is performed on the pixel region to form a photodiode N region 18 on the other side of the shallow trench isolation 11 .

As shown in FIG. 9 , a gate electrode and a source and drain electrode are formed. Specifically, a gate electrode layer on the silicon oxide layer 12 is formed, and the gate electrode layer is, for example, a polysilicon layer. The gate layer is formed into gates of different transistors (eg 31 , 32 , 33 , 34 ) using a photolithography process. Ion implantation is performed on the source and drain regions on both sides of the gate to form the source and drain of the corresponding transistor. For example, N-type ion implantation (doping) is performed on the pixel region X to form a source electrode 41 , a drain electrode 51 , and a drain electrode 42 . P-type ion implantation (doping) is performed on the pixel region X to form a P region (pinning layer) 19 on the surface of the photodiode. The gate electrode 31 , the source electrode 41 and the drain electrode 51 constitute the NMOS transistor of the pixel region X. Exemplarily, N-type ion implantation is performed on the first logic region I of the logic region to form a source electrode 43 and a drain electrode 53; P-type ion implantation is performed on the second logic region II of the logic region to form a source electrode 44 and a drain electrode 54; the gate electrode 34, the source electrode 44 and the drain electrode 54 constitute, for example, a PMOS transistor of the second logic region II. In other examples, PMOS transistors may also be formed in the first logic region I, and NMOS transistors may be formed in the second logic region II, which are configured according to actual needs.

As shown in FIG. 9 and FIG. 10 , the pixel area X includes a plurality of transistors located in the substrate 10 , and FIG. 9 only shows some of the transistors. Wherein, the plurality of transistors in the pixel region include transistors formed by an N-type doped layer in the substrate of the pixel region. The pixel region may include a photodiode PD and various types of transistors such as transfer transistor TX, reset transistor RST, source follower transistor SF, row select transistor RS, conversion gain control transistor, and the like. The photodiode PD may be a buried photodiode.

During operation, the photocharges generated by the photodiode PD are responsive to incident light during exposure. The transfer transistor TX is connected to a transfer signal which controls the transfer transistor TX to transfer the charge accumulated in the photodiode PD to the floating diffusion region (FD), ie the drain 42 . The gate 32 , the drain 42 and the photodiode N region 18 in FIG. 9 constitute the transfer transistor TX in FIG. 10 , and the photodiode N region 18 is the source of the transfer transistor TX. The transfer transistor TX may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A reset transistor RST is connected between VDD and the floating diffusion region (ie, drain 42) and is responsive to a reset signal to reset the pixel circuit, eg, discharge or charge the floating diffusion region and photodiode PD to the current voltage. The floating diffusion region (FD) is connected to the source follower transistor SF. The source follower transistor SF is connected between VDD and the row select transistor RS, amplifying the signal in response to the potential of the floating diffusion region (ie, drain 42). The row select transistor RS connects the pixel circuit output from the source follower transistor SF to the readout column, or bit line BIT, in response to the row select control signal.

Incident light causes charges to be generated in the photodiode PD. As the light-generated electrons in the photodiode PD gradually accumulate, its voltage increases (the electrons are negatively charged). The voltage or charge of the photodiode PD represents the intensity incident on the photodiode PD during exposure. Charge is transferred from photodiode PD to the floating diffusion region (ie, drain 42 ) through transfer transistor TX, so that the voltage of the floating diffusion region decreases proportionally during exposure by photogenerated electrons accumulated on photodiode PD.

11 to 12 are schematic diagrams of a method for fabricating an image sensor according to a second embodiment of the present invention. In the second embodiment, as shown in FIG. 2 b and FIG. 11 , a silicon oxide layer 12 and a silicon nitride layer 13 are sequentially formed on the surface of the substrate 10 ; a shallow trench isolation (STI) 11 is formed on the substrate 10 to perform chemical mechanical After grinding (CMP) to make the upper surfaces of the shallow trench isolation (STI) 11 and the silicon nitride layer 13 flush, a first protective layer 25 can also be formed, and the first protective layer 25 covers the silicon nitride layer 13 and the shallow trenches Surface of isolation (STI) 11. The first protective layer 25 may include a silicon nitride layer (Si ₃ N ₄ ), a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer (Si ₃ N ₄ -SiO ₂ -Si ₃ N ₄ ), and at least one of the polysilicon layers. As shown in FIG. 12 , a fifth photoresist layer 19 is formed. The fifth photoresist layer 19 covers the first protective layer 25 of the pixel region X and exposes the logic region L. As shown in FIG. Using the fifth photoresist layer 19 as a mask, the first protective layer 25 and the silicon nitride layer 13b located in the logic region L are etched and removed, and can be removed by a dry method or a wet method. For example, the first protective layer 25 and the silicon nitride layer 13b located in the logic region are removed by wet etching with hot phosphoric acid (H ₃ PO ₄ ). Next, the pixel region X has the first protective layer 25 and the silicon nitride layer 13a together as a protective layer, and the ion implantation process of the logic region L is performed; the ion implantation of the logic region L includes, for example, IO (input and/or output) devices and multiple cycles of lithography-ion implantation in the N-well, P-well and channel regions of the core device. Next, the first protective layer 25 and the silicon nitride layer 13a covering the pixel region X are removed. The ion implantation process of the pixel region X is performed, and the ion implantation of the pixel region X includes a photolithography-ion implantation cycle of the photosensitive region and the well regions and channel regions of the transistors constituting the pixel unit. Then the gate and source and drain regions of the device are formed. In the second embodiment, the first protective layer 25 and the silicon nitride layer 13a of the pixel region jointly protect the pixel region X, thereby enhancing the protection of the pixel region to further reduce the contamination and damage to the pixel region caused by the logic region processing process, improving the The quality of the image sensor.

The present invention also provides another manufacturing method of an image sensor, which includes the following steps in sequence:

a substrate is provided, the substrate includes a pixel area and a logic area; a silicon oxide layer covering the pixel area and the logic area is formed on the surface of the substrate; a silicon nitride layer covering the silicon oxide layer is formed ; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;

removing the silicon nitride layer covering the logic region and the pixel region;

forming a second protective layer, the second protective layer covering the surface of the silicon oxide layer and the shallow trench isolation;

removing the second protective layer covering the logic region and retaining the second protective layer covering the pixel region;

performing an ion implantation process for the logic region;

removing the second protective layer covering the pixel area;

An ion implantation process for the pixel region is performed.

13 to 14 are schematic diagrams of another method for fabricating an image sensor according to the present invention. 2b and 13, a silicon oxide layer 12 and a silicon nitride layer 13 are sequentially formed on the surface of the substrate 10; the silicon nitride layer 13, the silicon oxide layer 12 and the partially thick substrate 10 are etched to form trenches, Oxide is filled in the trench to form a shallow trench isolation (STI) 11, and chemical mechanical polishing (CMP) is performed to make the upper surface of the shallow trench isolation (STI) 11 and the silicon nitride layer 13 flush, and then the cover is removed. The logic region X and the silicon nitride layer 13 of the pixel region L. As shown in FIG. 14 , the second protective layer 45 is re-formed, and the second protective layer 45 covers the surface of the silicon oxide layer 12 and the shallow trench isolation (STI) 11 . The top surface is flush, and the top surface of the second protective layer 45 after CMP is higher than the top surface of the STI 11 , that is, the second protective layer 45 wraps the top of the STI 11 . The second protective layer 45 may include a silicon nitride layer (Si ₃ N ₄ ), a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer (Si ₃ N ₄ -SiO ₂ -Si ₃ N ₄ ), and at least one of the polysilicon layers.

Through the etching process to form the STI trench and the chemical mechanical polishing (CMP) process, the thickness uniformity and quality of the originally formed silicon nitride layer 13 will decrease. By removing the silicon nitride layer 13, the second protective layer 45 is formed again. , the good quality and uniformity of the second protective layer 45 can be ensured, and the top of the trench isolation (STI) 11 can be wrapped to enhance the anti-pollution capability. In other examples, the silicon oxide layer 12 can also be removed, and a new silicon oxide layer can be grown again. Similarly, in the process of forming the STI trench through the etching process, the silicon oxide layer 12 may suffer certain damage and grow again. A silicon oxide layer is used to ensure the quality of the silicon oxide layer on the surface of the substrate 10 .

Next, the second protective layer 45 covering the logic region L is removed, and the second protective layer 45 covering the pixel region X is retained; the ion implantation process for the logic region L is performed; the second protective layer 45 covering the pixel region is removed protective layer 45 ; perform the ion implantation process of the pixel region X.

In the embodiment of the present invention, by removing the silicon nitride layer covering the logic region and the pixel region, and forming a second protective layer again, the good quality and uniformity of the second protective layer can be ensured; Two protective layers, retaining the second protective layer covering the pixel area; during the ion implantation process of the logic area, the pixel area is protected by the second protective layer, which effectively reduces the pollution and pollution of the logic area processing process to the pixel area. Physical damage to improve the quality of the image sensor.

In summary, the present invention provides a method for fabricating an image sensor, which sequentially includes the following steps: providing a substrate, the substrate including a pixel region and a logic region; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic region and retaining the silicon nitride layer covering the pixel region ; Perform an ion implantation process in the logic region; remove the silicon nitride layer covering the pixel region; perform an ion implantation process in the pixel region. In the present invention, the silicon nitride layer covering the logic region is removed, and the silicon nitride layer covering the pixel region is retained. After the ion implantation process in the logic region is completed, the silicon nitride layer covering the pixel region is removed, and the nitrided silicon nitride layer retained in the pixel region is used. The silicon layer is used as a protective layer, thereby effectively reducing the pollution and physical damage to the pixel area caused by the logic area processing process, and improving the quality of the image sensor.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can use the methods and technical contents disclosed above to improve the present invention without departing from the spirit and scope of the present invention. The technical solutions are subject to possible changes and modifications. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention belong to the technical solutions of the present invention. protected range.

Claims (10)

1. a manufacturing method of an image sensor, is characterized in that, comprises the following steps successively: a substrate is provided, the substrate includes a pixel area and a logic area; a silicon oxide layer covering the pixel area and the logic area is formed on the surface of the substrate; a silicon nitride layer covering the silicon oxide layer is formed ; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic region and retaining the silicon nitride layer covering the pixel region; performing an ion implantation process for the logic region; removing the silicon nitride layer covering the pixel area; An ion implantation process for the pixel region is performed. 2. The method for fabricating an image sensor according to claim 1, wherein after forming the shallow trench isolation, the method further comprises: forming a first protective layer, the first protective layer covering the silicon nitride layer and the surface of the shallow trench isolation; In the step of removing the silicon nitride layer covering the logic region, the first protection layer covering the logic region is also removed, and the first protection layer covering the pixel region remains. 3. The method for fabricating an image sensor according to claim 2, wherein the first protective layer comprises a silicon nitride layer, a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer, and polysilicon at least one of the layers. 4. The method for fabricating an image sensor according to claim 1, wherein after forming the shallow trench isolation, the method further comprises: forming an isolation layer, the isolation layer covers the surface of the silicon nitride layer and the shallow trench isolation, and the material of the isolation layer includes a silicon oxide layer and/or a silicon oxynitride layer; In the step of removing the silicon nitride layer covering the logic region, the isolation layer covering the logic region is also removed, and the isolation layer covering the pixel region remains. 5. The method for fabricating an image sensor according to any one of claims 1 to 4, wherein removing the silicon nitride layer covering the logic region and retaining the silicon nitride layer covering the pixel region, specifically comprising: : forming a first photoresist layer, the first photoresist layer covering the pixel region and exposing the logic region; Using the first photoresist layer as a mask, dry or wet etching is performed to remove the silicon nitride layer covering the logic region. 6. The method for fabricating an image sensor according to any one of claims 1 to 4, wherein the logic region comprises a first logic region and a second logic region; performing an ion implantation process for the logic region, specifically include: forming a second photoresist layer, the second photoresist layer covering the pixel area and the second logic area, exposing the first logic area, using the second photoresist layer as a mask, to performing P-type ion implantation on the first logic region to form a P-type well region in the first logic region; removing the second photoresist layer; forming a third photoresist layer, the third photoresist layer covering the pixel area and the first logic area, exposing the second logic area, using the third photoresist layer as a mask, to N-type ion implantation is performed on the second logic region to form an N-type well region in the second logic region; and the third photoresist layer is removed. 7. The method for fabricating an image sensor according to any one of claims 1 to 4, wherein performing an ion implantation process in the pixel region specifically comprises: performing P-type ion implantation on the pixel region to form a P-type well region on one side of the shallow trench isolation; N-type ion implantation is performed on the pixel region to form a photodiode N region on the other side of the shallow trench isolation. 8. The method for manufacturing an image sensor according to claim 7, further comprising: forming gates corresponding to different transistors in the pixel region and the logic region; Ion implantation is performed into the substrate on both sides of the gate to form source and drain electrodes corresponding to each transistor and a P region on the surface of the photodiode. 9. A method for making an image sensor, comprising the steps of: a substrate is provided, the substrate includes a pixel area and a logic area; a silicon oxide layer covering the pixel area and the logic area is formed on the surface of the substrate; a silicon nitride layer covering the silicon oxide layer is formed ; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic region and the pixel region; forming a second protective layer, the second protective layer covering the surface of the silicon oxide layer and the shallow trench isolation; removing the second protective layer covering the logic region and retaining the second protective layer covering the pixel region; performing an ion implantation process for the logic region; removing the second protective layer covering the pixel area; An ion implantation process for the pixel region is performed. 10. The method for fabricating an image sensor according to claim 9, wherein the second protective layer comprises a silicon nitride layer, a stacked layer of a silicon nitride layer-silicon oxide layer-silicon nitride layer, and polysilicon at least one of the layers.

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