CN114846785A - Image forming apparatus and image forming method - Google Patents

Abstract

An embodiment of the present application may relate to an imaging apparatus including a comparator, a pixel, and a control circuit, wherein the comparator includes a switch, a first transistor, and a first capacitor, wherein the first capacitor is charged when the switch is turned on, and wherein the comparator compares a pixel signal input from the pixel with a ramp signal input from the control circuit using power charged in the first capacitor after the switch is turned off, and outputs an output signal.

Description

Imaging device and imaging method

technical field

The embodiments described below relate to imaging devices/methods, eg, for still images and/or movies.

Background technique

Imaging devices and imaging methods for still images and/or movies are generally widely used. Imaging devices such as digital cameras, cellular phones, terminal equipment, and automobiles (vehicle cameras), but are not limited thereto.

SUMMARY OF THE INVENTION

SUMMARY OF THE INVENTION The present disclosure, including the aspects shown below, may relate to imaging apparatus/methods, eg, for still images and/or movies. It should be understood that the following disclosure does not limit or constrain the pending application/invention.

A first aspect is an imaging device including a comparator, a pixel, and a control circuit, wherein the comparator includes a switch, a first transistor, and a first capacitor, wherein when the switch is turned on, all the first capacitor is charged, and wherein, after the switch is turned off, the comparator compares the pixel signal input from the pixel with that from the control circuit using the power charged in the first capacitor Input the ramp signal, and output the output signal.

A second aspect is the imaging device according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A third aspect is the imaging device according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourth aspect is the imaging device according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifth aspect is the imaging device according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor biases A current is set to flow to drive the comparator.

A sixth aspect is the imaging device according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventh aspect is the imaging device according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighth aspect is the imaging device according to the above aspect, wherein the comparator is disconnected from a common power source of the imaging device when the switch is turned off.

A ninth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A tenth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

An eleventh aspect is an imaging method for an imaging device including a comparator, a pixel, and a control circuit, the imaging method comprising: when a switch of the comparator is turned on, charging a first capacitor of the comparator charging; after the switch is turned off, comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor; and outputting an output signal.

A twelfth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A thirteenth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourteenth aspect is the imaging method according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifteenth aspect is the imaging method according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor makes A bias current flows to drive the comparator.

A sixteenth aspect is the imaging method according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventeenth aspect is the imaging method according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighteenth aspect is the imaging method according to the above aspect, wherein the comparator is disconnected from the common power supply of the imaging device when the switch is turned off.

A nineteenth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A twentieth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

The above disclosure does not limit or constrain this application/invention.

Description of drawings

FIG. 1 is a schematic diagram of an imaging device described in one embodiment.

Figure 2 is a circuit diagram of one embodiment.

Figure 3 is a timing diagram of one embodiment.

Figure 4 is a circuit diagram of one embodiment.

Figure 5 is a timing diagram of one embodiment.

Detailed ways

The following disclosure includes examples only. The scope of the invention and application should not be considered limited by the examples shown below.

FIG. 1 shows a schematic diagram of an imaging device of one embodiment. The imaging apparatus 100 includes a camera module 110 , pixels 120 , an analog to digital (AD) converter 130 and a timing generator (T/G) 140 . Imaging device 100 may include logic circuit 150 in place of T/G 140 . The imaging device 100 may also include a set of lenses, a battery, a memory, and a screen or panel, among others. The imaging device 100 may also include a processor, a hard disk, an optical disk drive, a transceiver, a speaker, a microphone, and the like.

The camera module 110 includes a pixel 120 , an AD converter 130 and a T/G 140 . As described above, the T/G 140 may be replaced with the logic circuit 150 external to the camera module 110 . The camera module 110 may be the image sensor circuit shown in FIG. 2 .

The pixels 120 may be complementary metal oxide semiconductor (CMOS) image sensors, charge coupled device (CCD) image sensors, or other devices. The pixel 120 may be composed of a plurality of pixels. The pixels 120 may also include color filters. The pixel 120 receives light through a lens not shown in the figure, and outputs an analog signal corresponding to the intensity of the received light.

The AD converter 130 is input with an analog signal from the pixel 120 and outputs a digital signal indicating the intensity of light received by the pixel 120 . A processor not shown in the figure may receive the digital signal from the AD converter 130 and generate image data. The processor may store the image data in, for example, a memory. The image data can be a still image or part of a movie.

The T/G 140 (or the logic circuit 150 ) outputs a pulse signal indicating the operation timing based on which the constituent elements of the imaging apparatus 100 operate. For example, when a timing signal is input from the T/G 140 (or the logic circuit 150 ), the AD converter 130 may compare the voltage of the analog signal output from the pixel 120 with a reference voltage not shown in FIG. 1 .

Hereinafter, the details of the AD converter 130 are explained with reference to the accompanying drawings.

The imaging device may include an AD converter, eg, a single slope analog to digital converter (SS ADC). In general, it is desirable to reduce the power consumption of the SS ADC without causing side effects.

For example, the power consumption of the AD converter (other than the SSADC) can be reduced only by reducing the bias current of the comparator included in the AD converter. An example of a bias circuit that reduces power consumption is implemented using a dynamic bias circuit. On the other hand, less bias current may degrade the performance of the comparator (eg analog-to-digital conversion): reduced speed, increased noise, and/or reduced AD accuracy.

As mentioned above, in general, it is desirable to reduce the power consumption of the ADC. It should be noted that it is not an optimal choice to apply the dynamic bias circuit of the comparator, which can reduce the power consumption of the AD converter, to the SS ADC.

Because in general, comparators with dynamic bias circuits can compare input signals corresponding to input digital signals, which in SS ADCs cannot be generated during AD conversion operations.

Typically, dynamically biased comparators can cause large "banding noise". This is because the dynamic bias circuit can cause large changes in the comparator's supply current. This may negatively affect image quality.

Hereinafter, the first embodiment will be explained. Figure 2 shows an image sensor circuit including two input pixel signal lines (Vpixel1 and Vpixel2) and two single slope ADCs. The image sensor circuits shown in Figure 2 show a simplified structure in order to more easily explain their operation. In an actual image sensor, more ADCs need to be placed, and these ADCs are usually columnar to accommodate the number of pixel signal outputs. The image sensor circuit shown in FIG. 2 corresponds to the camera module shown in FIG. 1 .

The input pixel signal lines Vpixel1 and Vpixel2 are included in the pixel 120 shown in FIG. 1 . Each of the input pixel signal lines Vpixel1 and Vpixel2 corresponds to one pixel. I1 and I2 shown in Figure 2 are comparators. The comparator I1 receives signals from pixels not shown in FIG. 2 through an input pixel signal line Vpixel1. The comparator I2 inputs a signal from a pixel not shown in FIG. 2 through an input pixel signal line Vpixel1.

VRAMP1 and VRAMP2 shown in Figure 2 represent the ramp reference voltages provided through the lines. The comparator I1 receives the ramp reference voltage VRAMP1 from terminal 3 . Comparator I1 receives the ramp reference voltage VRAMP2 from terminal 2. The comparator 2 has the same structure as the comparator I1. The ramp reference voltages VRAMP1 and VRAMP2 may be output from a control circuit not shown in FIG. 2 (eg, the logic circuit 150 shown in FIG. 1 ).

VDD_common shown in Figure 2 is a common power supply shared with all or some of the comparators. The comparator I1 receives the common power supply VDD_common through terminal 1 and performs its operation. The comparator I2 has the same structure as the comparator I1. The common power supply VDD_common may be powered from a power supply circuit not shown in the drawings.

The comparator I1 receives the ramp reference voltages VRAMP1/VRAMP2 and an input pixel voltage (hereinafter, Vpixel1 for ease of understanding), and performs a comparison operation. The comparator I1 outputs a signal indicating its comparison result from the terminal Vout1 shown in FIG. 2 . The comparator I2 outputs a signal indicating its comparison result from the terminal Vout2 shown in FIG. 2 .

Comparator I1 includes transistors M1, M2, M3, M4, M6, M7, M8, M9, and M10. Comparator I1 includes capacitors Cp, _CG , and Cs. The comparator I1 includes a switch SW1. Comparator I1 includes terminals 1 to 5 . Terminal 1 is connected to the common power supply VDD_common. Terminal 2 receives the ramp reference voltage VRAMP2. Terminal 3 receives the ramp reference voltage VRAMP1. Terminal 4 is connected to the input pixel signal line Vpixel1. The output signal from the comparator I1 is output from the terminal 5 and supplied to the counter circuit I3.

The comparator I2 has basically the same structure as the comparator I1. There is a small difference between them. The terminal 4 of the comparator I2 is connected to the input pixel signal line Vpixel2, and the output signal of the comparator I2 is supplied to the counter circuit I4 through the terminal 5.

The counter circuit I3 receives the output signal from the terminal Vout1. The counter circuit I3 receives the clock signal (CLK). During a predetermined period of time, the counter circuit I3 counts the clocks included in the clock signal while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) may be output by the control circuit shown in the figures (eg, the logic circuit 150 of FIG. 1 ).

The counter circuit I4 receives the output signal from the terminal Vout2. The counter circuit I4 receives the clock signal (CLK). During a predetermined period of time, the counter circuit 4 counts the clocks included in the clock signal while the counter circuit detects the output signal from the terminal Vout1. The clock signal (CLK) may be provided by the control circuit shown in the figures (eg, logic circuit 150 of FIG. 1 ).

The operation of the image sensor circuit shown in FIG. 2 is described with reference to the timing diagram shown in FIG. 3 . In FIG. 3, it is assumed that the first pixel signal level corresponding to the input pixel signal line Vpixel1 (for ease of understanding, hereinafter Vpixel1) is lower than the second pixel signal level corresponding to the input pixel signal line Vpixel2 (for ease of understanding) , hereinafter Vpixel2). In actual use, the first pixel signal level Vpixel1 may be higher than the second pixel signal level Vpixel2 or the same as the second pixel signal level Vpixel2. The horizontal axis of FIG. 3 is the time axis.

In FIG. 3 , the ramp reference voltage VRAMP2 is higher than the ramp reference voltage VRAMP1 and precisely tracks the ramp reference voltage VRAMP1 with a predetermined offset level (Vth). The ramp reference voltage VRAMP1 is initially at a predetermined initial level (Vinit). At a predetermined timing, the ramp reference voltage VRAMP1 starts to ramp up from Vinit at a constant rate. For example, when the user operates the imaging device to take a photo or to take a movie, the ramp reference voltage starts to ramp up. When the ramp reference voltage VRAMP1 starts to ramp up, the ramp reference voltage VRAMP2 simultaneously starts to ramp up from a predetermined level (Vinit+Vth) higher than VRAMP 1 at the same rate as VRAMP 1 . Both the ramp reference voltages VRAMP1 and VRAMP2 suspend the ramp-up at the same timing and maintain it at a predetermined level.

The offset level Vth is a predetermined voltage, and can be designed to be the voltage used by the transistor M5 shown in FIG. 2 to flow the target bias current. Transistor M5 has a grounded source terminal. When a voltage is applied to the gate terminal of transistor M5, transistor M5 acts as a current source for the comparator.

The transistor M5 shown in FIG. 2 may be a MOS transistor. For example, the drain current (Id) of the transistor M5 is determined as follows.

Id=k*W/L*(Vgs–Vt) ² (1)

In formula (1), k: constant, W: channel width, L: channel length, Vgs: voltage difference between gate terminal and source terminal, Vt: threshold voltage.

If it is assumed that "k", "W", "L" and "Vt" are all known, and the target drain current Id can be determined or predetermined, then "Vgs" can be automatically calculated using equation (1). When the source terminal is grounded and Vth is applied to the gate terminal, Vth is equal to Vgs. Therefore, the predetermined offset level Vth is applied to the gate terminal of the transistor M5.

Here, the target drain current Id may be determined in consideration of, for example, power consumption of the comparators I1 and I2, random noise, voltage gain, transient response, and the like.

In Figure 2, each pixel signal (for ease of understanding, Vpixel1 or Vpixel2) is fed to the negative input (terminal 4) of the comparator I1 (or I2), which converts the pixel signal Vpixel1 (or I2) Vpixel2) is compared with the ramp reference voltage Vramp1. Another ramp reference voltage Vramp2 is used to apply a voltage to the gate terminal of transistor M5. The reference voltage Vramp2 may be provided by a sample/hold circuit not shown in the drawings. Transistor M5 acts as a bias current source for comparator I1 (or I2).

In the following, the basic operation of the comparators I1/I2 is explained. The comparators I1, I2 in this embodiment may be differential amplifiers. The comparators I1 and I2 have the same structure, including transistors M1 to M5. Transistors M1 and M2 may be NMOS differential input transistors driven by current source transistor M5. Transistors M3 and M4 serve as load transistors for input transistors M1 and M2. The transistors M3 and M4 can be understood as a current mirror circuit.

In this embodiment, it is assumed that transistors M1 and M2 are the same size, and transistors M3 and M4 are the same size. When the gate terminal voltage of the transistor M1 is higher than the gate terminal voltage of the transistor M2, the drain current (IdM1) of the transistor M1 is greater than the drain current (IdM2) of the transistor M2. The drain current (IdM1) of transistor M1 is equal to the drain current (IdM3) of transistor M3. Since transistors M3 and M4 act as a current mirror circuit, the drain current of transistor M3 is mirrored to the drain current of transistor M4 (IdM3=IdM4).

The output current of comparator I1 (or I2) is generated by the difference (IdM4-IdM2) between the drain current of transistor M2 and the drain current of transistor M4. Since the drain current from transistor M2 is less than the drain current of transistor M1 , the drain current difference between transistors M1 and M2 (IdM1 - IdM2 ) exceeds the output current of comparator I1 (or I2 ) at terminal 5 . The output terminal impedance can be designed to have a high value, and therefore, the output voltage can be raised accordingly.

In Figure 2, each signal from a pixel (input pixel voltage Vpixel1/Vpixel2) is fed to the negative input (terminal 4) of the comparator I1 (or I2). The comparator I1 (or I2) compares the pixel signal with the ramp reference voltage (Vramp1). The other ramp reference voltage (Vramp2) is used to supply voltage to the gate terminal of transistor M5 (through transistor M7) through the sample/hold circuit. Transistor M5 acts as a bias current source for comparator I1 (or I2).

As described above, the predetermined offset level Vth may be designed to be the voltage level at which the current source transistor M5 is biased to cause the target bias current to flow to the comparator I1 (or I2). When the ramp reference signal Vramp1 reaches the same level as the input pixel signal (Vpixel1/Vpixel2), the comparator I1 (or I2) may have a voltage gain with a level sufficient to compare the input signal. The timing at which this occurs is "T5" shown in FIG. 3 .

As shown in FIG. 2, the output from the comparator I1 (or I2) is provided to the counter circuit I3 (or I4) through the terminal Vout1 (or Vout2). The counter circuit I3 (or I4) counts the number of pulses supplied from the terminal CLK while the output voltage level from the output of the comparator I1 (or I2) is kept at a low level. This case corresponds to "T1" to "T5" shown in FIG. 3 . In a similar manner, when the ramp reference voltage VRAMP1 is lower than the input pixel voltage Vpixel2, the counter circuit I4 counts the number of pulses applied through the terminal CLK. Therefore, the output value from the counter circuit I3 may be different from the output value of the counter circuit I4. For example, the logic circuit 150 shown in Figure 1 may receive the output value from the counter circuit I3 (or I4) and use the output digital value to generate an image.

In FIG. 3, at timing T1, when the pulse ΦPW becomes a high level, the switch SW1 is turned on. The common power supply VDD_common is supplied to the local power supply line Vdd1 (or Vdd2) of the comparator I1 (or I2) through the switch SW1. The capacitor Cp, which is a storage capacitor, is charged so as to have the same voltage as the common power supply VDD_common. Before "T1", the switch SW1 remains open and the capacitor Cp, which has one ground terminal, is not charged. Pulse ΦPW and other pulse signals may be provided from, for example, logic circuit 150 or T/G 140 .

At timing T1, the pulse ΦPW becomes a high level, and the switch SW1 is turned on accordingly. Then, from the timings T1 to T2, the capacitor Cp is charged. At timing T2, the pulse ΦPW becomes low, the switch SW1 is turned off, and the local power supply line Vdd1 (or Vdd2) of the comparator I1 (or I2) is disconnected from the common power supply VDD_common. After T3, the comparator I1 (or I2) uses the power stored in the capacitor Cp for its operation. Thus, for example, when the comparator I1 (or I2) is performing a comparison function, the local power lines of each comparator can be isolated from each other, thus reducing the power supply line related crosstalk between the comparators (I1, I2) caused by negative impact. This may contribute to improving the quality of images obtained by the imaging device 100 due to less crosstalk and more stable power lines. In addition, the comparator I1 (or I2 ) consumes power only when a comparison operation is required, and thus, the power consumption of the imaging device 100 can be reduced. It should be noted that the imaging device 100 may include millions or more of pixels and comparators. The power consumption of these entire circuits can be significantly reduced, which is beneficial for devices that obtain high-resolution images.

At timing T3, the pulse Φ1 supplied from the logic circuit 150 or the T/G 140 becomes a high level, and the transistors M8 and M10 in the comparator I1 (or I2) are turned on. One terminal of the capacitor CG is connected to the terminal 4 through the transistor M8 , and the input pixel voltage _Vpixel1 (or Vpixel2 ) is applied to the terminal 4 . The other terminal of capacitor _CG is connected to the ground terminal of comparator I1 (or I2) through transistor M10.

In FIG. 3, when the pulse Φ1 goes high, the pulse Φ applied to the gate terminal of the transistor M6 goes high at the same time. The transistor M6 having the grounded source terminal is turned on, and then the capacitor Cs connected to the drain terminal and the source terminal of the transistor M6 is discharged. The source terminal of the transistor M5 is connected to the capacitor Cs, and therefore, the voltage level of the source terminal of the transistor M5 becomes the ground level.

At timing T4, pulse Φ1 goes low and pulse Φ2 provided by logic circuit 150 or T/G 140 goes high. Transistors M8 and M10 are turned off due to pulse Φ1 applied to their gate terminals. When transistor M8 is turned off, one terminal of capacitor _CG is disconnected from terminal 4 . When the transistor M10 is turned off, the other terminal of the capacitor _CG is disconnected from the ground terminal of the comparator I1 (or I2).

At timing T4, transistor M7 is turned on due to pulse Φ2 applied to the gate terminal of transistor M7. One terminal of capacitor _CG is connected to terminal 2 through transistor M7. At timing T4, transistor M9 is turned on due to pulse Φ2 applied to the gate terminal of transistor M9. The other terminal of capacitor _CG is connected to the gate terminal of transistor M5 through transistor M9. Transistor M5 acts as a current source in comparator I1. Since the ramp reference voltage _Vramp2 is applied to terminal 2 and the charge in the capacitor _CG is preserved, i.e. the voltage difference between the two terminals of the capacitor CG remains constant, it can be understood that the gate voltage of the transistor M5 (Fig. "VGATE" shown in 2) can be calculated with the following formula "Vinit+Vth-Vpixel1". In the case of comparator I2, the formula is "Vinit+Vth-Vpixel2".

At timing T5 shown in FIG. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel1. Since the voltage increase in the ramp reference voltage Vramp1 applied to the comparator I1 is obtained by "Vpixel1-Vinit", and the voltage difference between the ramp reference voltages Vramp1 and Vramp2 is Vth, the voltage applied to the transistor M5 in the comparator I1 is The voltage of the gate terminal can be obtained according to the formula shown below.

{(Vinit+Vth–Vpixel1)+(Vpixel1–Vinit)}=Vth

This means that transistor M5 can cause a bias current large enough to drive comparator I1 to flow through, and the output of comparator I1 goes high with a certain amount of delay time in response to its input voltage change. These responses are shown in Figure 3 as "Vout1" and "ibias1".

At illustration T6 shown in FIG. 3, the ramp reference voltage Vramp1 reaches the input pixel voltage Vpixel2. Since the voltage increase in the ramp reference voltage Vramp1 of the comparator I2 is (Vpixel2−Vinit), where the voltage difference between the ramp reference voltages Vramp1 and Vramp2 is Vth, it can be understood that the voltage applied to the comparator I2 included in the The voltage (VGATE) of the gate terminal of the transistor M5 is obtained by the formula shown below. This is similar to comparator I1.

{(Vinit+Vth-Vpixel2)+(Vpixel2-Vinit)}=Vth

This means that transistor M5 can flow a bias current large enough to drive comparator I2, whose output goes high with a certain amount of delay in response to its input voltage change. These responses are shown in Figure 3 as "Vout2" and "ibias2".

As mentioned above, since the bias current of each comparator I1/I2 only flows when the level of the ramp reference voltage Vramp1 is close to its input pixel signal level (Vpixel1 or Vpixel2), it is different from the constant current in some conventional SS ADCs. Comparators I1 and I2 consume less power compared to source-driven comparators. Furthermore, the timing of bias current flow in comparators I1/I2 can be automatically controlled by the input signal level and the ramp reference level (Vramp1/Vramp2).

The capacitance of the capacitor Cp shown in FIG. 2 is used to operate the comparators I1/I2 after T2 shown in FIG. 3 . At timing T2, the switch SW1 is turned off, and the comparators I1/I2 are disconnected from the common power supply VDD_common. When implementing a comparison operation with comparators I1/I2, it may be helpful to have information on how the capacitance of capacitor Cp can be estimated, and when the comparators (I1/I2) disclosed above are connected to the common supply line (VDD_common) How to properly handle its local power cord (Vdd1/Vdd2) after disconnection.

Before estimating the capacitance of the capacitor Cp (herein simply referred to as "Cp" for ease of understanding), it is understood that the total charge flowing into the capacitor Cs during the comparison of the comparators I1/I2 is less than Vth*Cs. For ease of understanding, in this formula, "Cs" represents the capacitance of the capacitor Cs. For correct operation of comparators I1/I2, the minimum supply voltage applied to capacitor Cs can be estimated based on various aspects of comparators I1/I2's voltage gain, input-output time delay, input offset voltage, and output dynamic range. In order to achieve these specifications required to achieve ADC specifications, the drain-source voltage of each transistor in comparators I1/I2 needs to remain above the so-called saturation voltage (Vds_min) calculated according to the formula shown below.

Vds_min=Vgs–Vt

Therefore, by adding the saturation voltage Vds_min of each transistor M4, M2 and M5, the minimum supply voltage (Vdd_min) can be estimated as shown below. In this embodiment, these transistors are assumed to be the same size.

Vdd_min=3*Vds_min

The capacitance of the capacitor Cp needs to be larger than "Cs*Vth/(VDD_common-Vdd_min)". From this calculation, the minimum capacitance of the capacitor Cp can be estimated. This minimum capacitance can reduce the power consumption of the imaging device 100 . Furthermore, by using such calculation results, the silicon area shared by the capacitors Cp can be minimized when the comparators I1/I2 are placed in the chip. Minimizing silicon area can help reduce the cost of the imaging device 100 .

Hereinafter, the second embodiment is explained. Figure 4 shows comparators I1 and I2. The reference numbers of FIG. 3 correspond to FIG. 2 . The comparators I1/I2 include transistors M1 to M10, wherein M1, M2, M5, M6, M7, M8, M9, M10 are all PMOS transistors, and M3 and M4 are NMOS transistors, and also include terminals 1 to 5, a capacitor C _G , Cp and Cs and switch SW1. It should be noted that the transistors M1 to M10 are different from those in FIG. 2 . I3 and I4 are counter circuits. CLK provides a clock signal from, for example, T/G 140 or logic circuit 150 shown in FIG. 1 . FIG. 5 is a timing chart when the comparators I1/I2 operate. In FIGS. 4 and 5, it is assumed that the pixel signal level Vpixel1 is higher than the pixel signal level Vpixel2, the ramp reference voltage VRAMP2 is lower than the ramp reference voltage VRAMP1, and the ramp reference voltage VRAMP2 is precisely at a predetermined offset level (Vth) Tracking ramp reference voltage VRAMP1. The ramp reference voltage VRAMP1 ramps down from a predetermined initial level (Vinit) at a constant rate. The operation of transistors M1 to M4 is similar to that of FIG. 2 .

In Figure 4, each pixel signal/voltage (for ease of understanding, Vpixel1 and Vpixel2) is supplied to the negative input (terminal 4) of a comparator I1 (or I2) which converts the pixel signal Vpixel1 (or Vpixel2) is compared to the ramp reference voltage (VRAMP1). Another ramp reference voltage (VRAMP2) can provide a voltage through the sample/hold circuit to the gate terminal of transistor M5, which acts as a bias current source for comparator I1 (or I2).

As mentioned above, "Vth" can be designed to be the voltage level of the bias current source transistor (M5) to cause the bias current to flow to the comparator I1 (or I2). Therefore, the comparator I1 (or I2) may have a voltage gain that is large enough to compare the input signal when the ramp reference voltage Vramp1 reaches the same voltage as the input pixel signal Vpixel1 (or Vpixel2).

As described above, the counter circuit I3 (or I4) inputs the signal output from the comparator I1 (or I2). The counter circuit I3 (or I4) counts the number of pulses supplied through the CLK terminal, while the output signal from the comparator I1 (or I2) is kept at low level.

In FIG. 5, at timing T1, the pulse ΦPW becomes a high level, and the switch SW1 is turned on accordingly. The common power supply VDD_common is supplied to the local power supply line of each comparator (Vdd1, Vdd2) through the switch SW1, and charges the storage capacitor Cp to have the same level as VDD_common. From timing T1 to T2, the capacitor Cp is charged.

At timing T2, the pulse φPW becomes low level, and the switch SW1 is turned off. The local power line (Vdd1/Vdd2, shown as Vdd in Figure 4) of each comparator (I1, I2) is disconnected from the common power line (VDD_common). At timing T3, the pulse Φ1, which has been at a high level and applied to the gate terminals of transistors M8 and M10, becomes a low level. Therefore, transistors M8 and M10 in comparator I1 (or I2) are turned on. One terminal of capacitor _CG is connected to terminal 4 through transistor M10. Terminal 4 receives the input pixel signal Vpixel1 (or _Vpixel2 ), while the other terminal of capacitor CG is connected through transistor M8 to Vdd1 derived from the common power supply VDD_common. After timing T3, the comparator I1 (or I2) uses the power stored in the capacitor Cp for its operation. Thus, for example, when the comparator I1 (or I2) is performing a comparison function, the local power lines of each comparator can be isolated from each other, thus reducing the power supply line related crosstalk between the comparators (I1, I2) caused by negative impact.

When the pulse Φ1, which has been at a high level and applied to the gate terminals of transistors M8 and M10, goes low, while the pulse Φres applied to the gate terminal of transistor M6 goes low, the transistors M8, M10 and M6 is turned on. The capacitor Cs connected to the transistor M6 is discharged, and the voltage applied to the source terminal of the transistor M5 reaches the same level as Vdd1/Vdd2, that is, the same level as the common power supply VDD_common.

At timing T4, the pulse Φ1 becomes a high level, while the pulse Φ2 becomes a low level. The transistors M8 and M10 that receive the pulse Φ1 on the gate node are turned off, and the transistors M7 and M9 that receive the pulse Φ2 on the gate node are turned on. Therefore, the two terminals of capacitor _CG are disconnected from terminal 4 (via transistor M10 ) and the common power supply Vdd (via transistor M8 ) and are connected to terminal 2 (via transistor M9 ) and the gate terminal of transistor M5 (via transistor M8 ) M7). Transistor M5 acts as a current source for comparator I1 (or I2). The ramp reference voltage VRAMP2 is applied to terminal 2, so the charge on the capacitor _CG is preserved. The voltage difference between the two terminals of capacitor CG still exists, and the voltage on the gate terminal of transistor M5 is calculated by "Vinit-Vth+Vdd- _Vpixelx (x=1 or 2)".

At timing T5, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel1. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I1 is reduced by (Vinit – Vpixel1), and the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth, therefore, the gate terminal of the transistor M5 in the comparator I1 reaches as follows. voltage shown.

(Vinit–Vth+Vdd1–Vpixel1)–(Vinit–Vpixel1)=Vdd1–Vth

This formula means that transistor M5 can cause a bias current large enough to drive comparator I1 to flow and the output signal of comparator I1 to go low with a certain amount of delay in response to its input voltage change. In Figure 5, the responses are shown as "Vout1" and "ibias1".

At timing T6, the ramp reference voltage VRAMP1 reaches the same voltage as the input pixel signal Vpixel2. The voltage of the ramp reference voltage VRAMP1 applied to the comparator I2 is reduced to (Vinit−Vpixel2), and the voltage difference between the ramp reference voltages VRAMP1 and VRAMP2 is Vth. The voltage applied to the gate terminal of the transistor M5 in the comparator I2 is calculated by the formula shown below.

(Vinit–Vth+Vdd2–Vpixel2)–(Vinit–Vpixel2)=Vdd2–Vth

This means that if transistor M5 can cause a bias current large enough to drive comparator I2 to flow, the output of comparator I2 goes low with a certain amount of delay time in response to its input voltage change. These responses are shown in Figure 5 as "Vout2" and "ibias2".

It will be appreciated that imaging devices typically have a large number of pixels arranged along multiple columns and rows. The timing diagrams included in FIG. 3 and/or FIG. 5 may be applied to these pixels, and for example, the pixels on each column or row may operate simultaneously according to the same timings described in FIG. 3 or FIG. 5 . Logic circuit 150 or T/G 140 may output signals and/or pulses to control comparators I1/I2.

The above-described embodiments may have various advantages. First, for example, the bias current of each of the aforementioned comparators in an SS ADC depends on the voltage difference between the input signal and the ramp reference voltage applied to the comparator. The comparator's bias current only begins to flow when the ramp reference voltage level is close to the input signal level. Therefore, the dynamic bias circuit is perfectly suitable for the SS ADC, and in addition, the power consumption of the SS ADC is reduced.

Second, for example, the local power line of each of the above-mentioned comparators in the SS ADC is connected to the common power supply (VDD_common) through a switch (SW1). Such separate local power lines each have storage capacitors (Cp).

As described in the above-described embodiment, just before the start of AD conversion, these switches ( SW1 ) are turned off, and at the same time, the local power supply line and the common (sensor) power supply line (VDD_common) of each comparator corresponding to the pixels arranged on a column )Disconnect.

The supply current for each column of comparators is provided by the storage capacitor (Cp) instead of the common (sensor) supply line (VDD_common). Therefore, negative effects such as fluctuations generated in each local power line (Vdd1/Vdd2) do not propagate to other local power lines, so that, for example, "striping noise" can be eliminated.

In addition to the above-described embodiments, the present application may have other aspects. For example, a first aspect is an imaging device comprising a comparator, a pixel and a control circuit, wherein the comparator comprises a switch, a first transistor and a first capacitor, wherein when the switch is turned on , the first capacitor is charged, and wherein, after the switch is turned off, the comparator compares the pixel signal input from the pixel with the pixel signal input from the pixel using the power charged in the first capacitor Control the ramp signal input by the circuit and output the output signal.

A second aspect is the imaging device according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A third aspect is the imaging device according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourth aspect is the imaging device according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifth aspect is the imaging device according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor biases A current is set to flow to drive the comparator.

A sixth aspect is the imaging device according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventh aspect is the imaging device according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighth aspect is the imaging device according to the above aspect, wherein the comparator is disconnected from a common power source of the imaging device when the switch is turned off.

A ninth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A tenth aspect is the imaging device according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

An eleventh aspect is an imaging method for an imaging device including a comparator, a pixel, and a control circuit, the imaging method comprising: when a switch of the comparator is turned on, charging a first capacitor of the comparator charging; after the switch is turned off, comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor; and outputting an output signal.

A twelfth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a first ramp signal and a second ramp signal.

A thirteenth aspect is the imaging method according to the above aspect, wherein the ramp signal includes a predetermined voltage difference between the first ramp signal and the second ramp signal.

A fourteenth aspect is the imaging method according to the above aspect, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal.

A fifteenth aspect is the imaging method according to the above aspect, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor makes A bias current flows to drive the comparator.

A sixteenth aspect is the imaging method according to the above aspect, wherein the capacitance of the first capacitor is large enough to drive the comparator.

A seventeenth aspect is the imaging method according to the above aspect, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal.

An eighteenth aspect is the imaging method according to the above aspect, wherein the comparator is disconnected from the common power supply of the imaging device when the switch is turned off.

A nineteenth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-up signals.

A twentieth aspect is the imaging method according to the above aspect, wherein the first ramp signal and the second ramp signal are ramp-down signals.

The embodiments disclosed above are examples, and it should be understood that the scope of the invention and the application is not limited or restricted by such disclosure.

Claims (20)

1. An imaging device, comprising a comparator, a pixel and a control circuit, wherein, The comparator includes a switch, a first transistor, and a first capacitor, wherein, When the switch is turned on, the first capacitor is charged, and wherein, After the switch is turned off, the comparator compares the pixel signal input from the pixel with the ramp signal input from the control circuit using the power charged in the first capacitor, and outputs an output signal. 2. The imaging device of claim 1, wherein the ramp signal comprises a first ramp signal and a second ramp signal. 3. The imaging device of claim 2, wherein the ramp signal comprises a predetermined voltage difference between the first ramp signal and the second ramp signal. 4. The imaging device of claim 1, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal. 5. The imaging apparatus according to claim 1, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor enables A bias current flows to drive the comparator. 6. The imaging device of claim 1, wherein the capacitance of the first capacitor is large enough to drive the comparator. 7. The imaging device of claim 1, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal. 8. The imaging device of claim 1, wherein the comparator is disconnected from a utility power source for the imaging device when the switch is open. 9. The imaging device of claim 1, wherein the first ramp signal and the second ramp signal are ramp-up signals. 10. The imaging device of claim 1, wherein the first ramp signal and the second ramp signal are ramp-down signals. 11. An imaging method for an imaging device comprising a comparator, a pixel and a control circuit, wherein the imaging method comprises: charging the first capacitor of the comparator when the switch of the comparator is turned on; comparing a pixel signal input from the pixel with a ramp signal input from the control circuit using the power charged in the first capacitor after the switch is turned off; Output the output signal. 12. The imaging method of claim 11, wherein the ramp signal comprises a first ramp signal and a second ramp signal. 13. The imaging method of claim 12, wherein the ramp signal comprises a predetermined voltage difference between the first ramp signal and the second ramp signal. 14. The imaging method of claim 11, wherein the comparator inverts the output signal when the first ramp signal reaches the same level as the pixel signal. 15. The imaging method according to claim 11, wherein when a voltage having the same voltage level as the predetermined voltage difference is applied to the gate terminal of the first transistor, the first transistor causes the A bias current flows to drive the comparator. 16. The imaging method of claim 11, wherein the capacitance of the first capacitor is large enough to drive the comparator. 17. The imaging method of claim 11, wherein the comparator completes its comparison operation when the second ramp signal reaches the same level as the pixel signal. 18. The imaging method of claim 11, wherein the comparator is disconnected from a utility power source of the imaging device when the switch is turned off. 19. The imaging method of claim 11, wherein the first ramp signal and the second ramp signal are ramp-up signals. 20. The imaging method of claim 11, wherein the first ramp signal and the second ramp signal are ramp-down signals.

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