CN114844348B - Power supply circuit, display panel and display device - Google Patents
Power supply circuit, display panel and display device Download PDFInfo
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- CN114844348B CN114844348B CN202110145442.5A CN202110145442A CN114844348B CN 114844348 B CN114844348 B CN 114844348B CN 202110145442 A CN202110145442 A CN 202110145442A CN 114844348 B CN114844348 B CN 114844348B
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- 239000003990 capacitor Substances 0.000 claims description 57
- 229920001621 AMOLED Polymers 0.000 claims description 29
- 230000000087 stabilizing effect Effects 0.000 claims description 8
- 239000003381 stabilizer Substances 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical group 0.000 claims description 4
- 230000001105 regulatory effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 102100024397 Soluble calcium-activated nucleotidase 1 Human genes 0.000 description 1
- 101710143787 Soluble calcium-activated nucleotidase 1 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present disclosure relates to the technical field of power supply circuits, and provides a power supply circuit, a display panel and a display device, wherein the power supply circuit generates a clock signal according to a control signal by using a logic control unit; generating a first driving signal and a second driving signal by using a grid driver; then according to the response of the first charge pump, outputting the voltage to be the node voltage with different multiplication ratios with the input voltage under the first driving signal or the second driving signal; and generating a negative voltage according to the node voltage by using a second charge pump, wherein the first driving signal and/or the second driving signal are/is used for respectively indicating the on/off state of at least one transistor in the first charge pump and the second charge pump, and the second driving signal and the first driving signal are mutually opposite signals. Therefore, the power supply can be flexibly selected according to specific application scenes, the problem of inductance size is solved, the total area of a power supply circuit is effectively reduced, the working efficiency of the power supply can be improved, and the cost of a power supply chip is reduced.
Description
Technical Field
The disclosure relates to the technical field of power supply circuits, and in particular relates to a power supply circuit, a display panel and a display device.
Background
Power supplies are an important component in electronic products. It is a current technical trend to use less power in electronic products to simplify the power requirements. However, in some special electronic applications, it is also necessary to use multiple power supplies for power, especially in some applications it is necessary to use both positive and negative power supplies for power.
The existing electronic applications of the positive and negative power supplies used simultaneously include: the front end of the traditional telephone is connected with the front end of the circuit, the liquid crystal display, the OLED (Organic Light-Emitting Diode) display, the CCD (Charge Coupled Device) bias, the power amplifying circuit and the analog input of the instrument. Except for the front-end analog part of the instrument, other power applications are large-scale, and a large number of special mature commercial products are appeared. Aiming at the special requirement of the front-end simulation part of the instrument and meter, a discrete power circuit combination is generally used for realizing positive and negative power supply.
Compared with the traditional liquid crystal panel, the active matrix organic light emitting Diode panel (Active Matrix Organic LIGHT EMITTING Diode, AMOLED) has the characteristics of high response speed, high contrast, wide viewing angle and the like. Has been used in a large number of smart bracelets, smart watches, smart phones, tablet computers, notebook computers, etc. The existing power supply chip and power supply circuit (such as the power supply of AMOLED) for providing positive and negative power supply almost adopt a DC-DC converter with an inductance architecture.
A DC-DC system using only Buck or LDO as a voltage regulator cannot obtain a stable output voltage when the battery voltage is lower than the system required voltage, and the normal available battery voltage will require a higher voltage in addition to the voltage drop actually existing in the converter. Since most MCU systems use 3.3V as the system power source, the available battery voltage is more than 3.4V, even up to 3.6V is normal, especially in the case of large load current. One solution to this problem is to use a Boost (Boost) device with a shunt (Bypass) function, where the Boost device is configured to maintain continuous operation of the system to a level that depletes the battery power, so that the Boost device only performs voltage boosting when needed, and provides input directly to the load for use when not needed, without any conversion, as shown in fig. 1.
In the existing power supply circuit 100 for an active matrix organic light emitting diode panel based on an inductor architecture, which has a voltage input terminal VIN, a clock signal input terminal CTRL, a positive voltage output terminal ELVDD and a negative voltage output terminal ELVSS, the voltage input terminal VIN of the power supply circuit 100 is directly supplied with power by a connection battery port, which supplies power to other circuits of the chip through a buck converter 102 and an inductor Ls connected in series. Wherein, this power circuit 100 still includes: a logic control unit 110 connected to the voltage input terminal VIN and the clock control signal input terminal CTRL, respectively, a DC-DC converter 120 connected to the voltage input terminal VIN and the logic control unit 110, a negative voltage charge pump (Negative Voltage Charge Pump) 130, and a low dropout linear regulator (LDO) 140 connected between the DC-DC converter 120 and the positive voltage output terminal ELVDD and an LDO 150 connected between the negative voltage charge pump 130 and the negative voltage output terminal ELVSS. The power supply circuit 100 is based on an inductance structure (boost or buck-boost) DC-DC converter 120, and steps up or down the voltage connected to the voltage input terminal VIN to a voltage near the required voltage, and generates an intermediate node voltage VOP with an absolute voltage slightly higher than the output positive voltage and the output negative voltage, and the intermediate node voltage VOP is stepped down by the LDO 140 to generate the output positive voltage, and is provided to the load circuit of the AMOLED through the positive voltage output terminal ELVDD. While a circuit for generating the intermediate node voltage VON by the negative voltage charge pump 130 and generating the output negative voltage through the LDO 150, which is provided to the load circuit of the AMOLED through the negative voltage output terminal ELVSS, has been developed in a large number of mature commercial products.
In the application of extremely focusing on the size of a PCB and the height of a device, such as a smart bracelet and a smart watch, the AMOLED power supply circuit of the current scheme is an inductance-based switching power supply architecture, the inductance area and the thickness have severely restricted the selection of the inductance, the circuit design and the product thickness design are influenced, customers are forced to select the inductance with relatively smaller size but larger direct current impedance DCR, the working efficiency is sacrificed, and the standby time is shortened.
In addition, the output voltage noise of the boost-type or buck-type power converter in the prior art is increased, in electronic products requiring low noise and stable voltage, the application causes serious electromagnetic interference EMI and radiation problems due to the periodic charge-discharge process with inductance, and the application is severely limited for the noise sensitive occasions such as radio frequency, and the use of the converter also requires the additional configuration of a power purifying circuit, so that the complexity and the chip size of the circuit are improved.
Disclosure of Invention
In order to solve the technical problems, the disclosure provides a power supply circuit, a display panel and a display device, which can flexibly select a power supply according to specific application scenes, so that the problem of inductance size is eliminated, the total area of the power supply circuit is effectively reduced, and the cost of a power supply chip and a peripheral circuit can be reduced while the working efficiency of the power supply is improved.
In one aspect the present disclosure provides a power circuit having a voltage input, a control signal input, a positive voltage output, and a negative voltage output, wherein the power circuit further comprises:
The logic control unit is connected with the control signal input end and used for generating a clock signal according to the accessed control signal;
a gate driver connected to an output terminal of the logic control unit, the gate driver configured to generate a first driving signal and a second driving signal according to an input voltage and the clock signal;
A first charge pump having an input connected to the voltage input and the output of the gate driver, respectively, and configured to operate in a plurality of modes in response to the first drive signal or the second drive signal to obtain a voltage at a node of the first charge pump output at a different multiplication ratio to the input voltage;
A second charge pump having an input connected to the output of the gate driver and the output of the first charge pump, respectively, configured to generate a negative voltage in response to the first driving signal or the second driving signal based on the node voltage,
The first driving signal and/or the second driving signal are/is used for respectively indicating the on/off state of a transistor of at least one of the first charge pump and the second charge pump, and the second driving signal and the first driving signal are mutually opposite signals.
Preferably, the aforementioned power supply circuit further includes:
The positive voltage stabilizer is connected with the output end of the first charge pump and used for converting the voltage of the split node into a first output power supply and outputting the first output power supply to the positive voltage output end;
a negative voltage stabilizer connected with the output end of the second charge pump for converting the negative voltage into a second output power and outputting the second output power to the negative voltage output end,
The first output power supply is a positive power supply with a first target voltage, and the second output power supply is a negative power supply with a second target voltage.
Preferably, the multiplication ratio of the divided node voltage of the aforementioned first charge pump output to the input voltage is obtained to be greater than 0 and less than or equal to 1, or greater than 1.
Preferably, the first charge pump has a first input terminal connected to the voltage input terminal, a second input terminal connected to the gate driver, and a third input terminal, a first output terminal supplying the split node voltage, and further includes:
A first transistor, a second transistor, a third transistor, and a fourth transistor connected in series between the first input terminal and ground, wherein the control terminals of the first transistor and the third transistor are commonly connected as the second input terminal, the first driving signal is connected, and the control terminals of the second transistor and the fourth transistor are commonly connected as the third input terminal, the second driving signal is connected;
A first capacitor having a first end connected to a connection node between the first transistor and the second transistor and a second end connected to a connection node between the third transistor and the fourth transistor;
a second capacitor, wherein a connection node of the second transistor and the third transistor is used as the first input end, and the second capacitor is connected between the first input end and the ground;
and a third capacitor connected between the first output terminal and a connection node of the first transistor and ground.
Preferably, the second charge pump has a fourth input terminal connected to the first output terminal, a fifth input terminal and a sixth input terminal connected to the gate driver, a second output terminal supplying the negative voltage, and further includes:
A fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor connected in series between the fourth input terminal and the second output terminal, wherein the control terminals of the fifth transistor and the seventh transistor are commonly connected as the fifth input terminal, the first driving signal is connected, the control terminals of the sixth transistor and the eighth transistor are commonly connected as the sixth input terminal, the second driving signal is connected, and the connection node of the sixth transistor and the seventh transistor is grounded;
A fourth capacitor having a first end connected to a connection node between the fifth transistor and the sixth transistor and a second end connected to a connection node between the seventh transistor and the eighth transistor;
And a fifth capacitor connected between the second output terminal and a connection node of the eighth transistor and ground.
Preferably, any one of the aforementioned first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, and eighth transistor is a metal oxide semiconductor field effect transistor.
Preferably, the aforementioned power supply circuit is integrated on one chip.
Preferably, the power supply circuit is connected with:
And the voltage stabilizing capacitor is positioned outside the chip and is coupled with the first charge pump.
Preferably, a dc regulated power supply is connected to the voltage input terminal of the power supply circuit, and the dc regulated power supply is configured to provide the input voltage.
Preferably, the voltage input terminal of the power supply circuit is externally connected to a battery supply terminal, the inside is connected to ground through a buck converter, an inductor and a capacitor connected in series, and a connection node of the inductor and the capacitor supplies the input voltage to the first charge pump,
The inductor and the capacitor are distributed outside the power circuit integrated chip.
Preferably, the display panel is an active matrix organic light emitting diode panel.
In another aspect, the present disclosure provides a display panel including:
a load circuit for generating a driving current to drive the light emitting element; and
A power supply circuit as hereinbefore described configured to provide positive power and negative power to the load circuit.
Preferably, the load circuit includes:
A first transistor, a first end of which is connected with a data signal, a second end of which is connected with a positive voltage output end of the power circuit through a second transistor, and a control end of which is connected with an (n) -th scanning signal;
A third transistor, a fourth transistor and the light emitting element connected in series between a connection node of the first transistor and the second transistor and a negative voltage output end of the power supply circuit, wherein a control end of the fourth transistor and a control end of the second transistor are commonly connected and connected with an (n) -th level enable signal;
A storage capacitor and a fifth transistor connected in series, wherein the positive electrode of the storage capacitor is connected with the positive voltage output end of the power circuit, the negative electrode of the storage capacitor is connected with the first end of the fifth transistor, the control end of the fifth transistor is connected with the (n-1) -th level scanning signal, and the second end of the fifth transistor receives a low level; and
And a sixth transistor, wherein a first end of the sixth transistor is connected with a control end of the third transistor, a second end of the sixth transistor is connected with a second end of the third transistor, and a control end of the sixth transistor is connected with a control end of the first transistor.
Preferably, the display panel is an active matrix organic light emitting diode panel, and the light emitting element is a light emitting diode.
In another aspect, the present disclosure also provides a display apparatus, including: a display panel as hereinbefore described.
The beneficial effects of the present disclosure are: the present disclosure provides a power supply circuit, a display panel, and a display device, wherein the power supply circuit includes: the logic control unit is used for generating a clock signal according to the accessed control signal; a gate driver configured to generate a first driving signal and a second driving signal according to an input voltage and the aforementioned clock signal; a first charge pump configured to operate in a plurality of modes in response to the aforementioned first drive signal or second drive signal to obtain a different multiplication ratio of the split node voltage output by the first charge pump to the input voltage; the second charge pump is configured to respond to the first drive signal or the second drive signal, generate a negative voltage according to the node voltage, the first drive signal and/or the second drive signal are used for respectively indicating the on/off state of at least one transistor in the first charge pump and the second charge pump, the second drive signal and the first drive signal are mutually opposite signals, and then the node voltage and the negative voltage are respectively processed by the voltage stabilizer to correspondingly generate a positive power supply and a negative power supply required by a subsequent circuit. The power supply circuit adopts an inductance-free scheme of a charge pump structure, can flexibly select a power supply according to specific application scenes, not only eliminates the problem of inductance size and improves the problem of electromagnetic interference (EMI), but also effectively reduces the total area of the power supply circuit, and can reduce the cost of a power supply chip and a peripheral circuit while improving the working efficiency of the power supply.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of an inductor-based power circuit for an active matrix OLED panel as disclosed in the prior art;
fig. 2 is a schematic structural diagram of a capacitor-based power circuit for an active matrix organic light emitting diode panel according to a first embodiment of the present disclosure;
FIGS. 3a and 3b are schematic diagrams of two charge pumps in one embodiment of the power circuit of FIG. 2;
FIG. 3c shows a schematic diagram of a configuration of two charge pumps in the power circuit of FIG. 2 in another embodiment;
fig. 4 is a schematic structural diagram of a power circuit based on a capacitor architecture for an active matrix organic light emitting diode panel according to a second embodiment of the present disclosure;
Fig. 5 is a schematic structural diagram of an active matrix organic light emitting diode panel according to a third embodiment of the present disclosure;
Fig. 6 is a schematic diagram showing a structure of a load circuit in the active matrix organic light emitting diode panel shown in fig. 5.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. The present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
Embodiment one:
Fig. 2 is a schematic structural diagram of a power circuit based on a capacitor architecture for an active matrix organic light emitting diode panel according to an embodiment of the present disclosure, fig. 3a and fig. 3b are schematic structural diagrams of two charge pumps in the power circuit shown in fig. 2 in one implementation mode, and fig. 3c is a schematic structural diagram of two charge pumps in the power circuit shown in fig. 2 in another implementation mode.
Referring to fig. 2 to 3b, a first embodiment of the present disclosure provides a power circuit 200 for an active matrix organic light emitting diode panel based on a capacitor architecture, the power circuit 200 having a voltage input terminal VIN, a control signal input terminal CTRL, a positive voltage output terminal ELVDD and a negative voltage output terminal ELVSS, the power circuit 200 further comprising at least: a logic control unit 201, a gate driver 210, a first charge pump 220 and a second charge pump 230,
The logic control unit 201 is connected to the control signal input end CTRL, and is configured to generate a clock signal Qc according to the accessed control signal CTRL;
The gate driver 210 is connected to an output terminal of the logic control unit 201, and the gate driver 210 is configured to generate a first driving signal Qm and a second driving signal Qn according to an input voltage Vin and the clock signal Qc;
The input terminal of the first charge pump 220 is connected to the voltage input terminal VIN and the output terminal of the gate driver 210, respectively, and is configured to operate in multiple modes in response to the first driving signal Qm or the second driving signal Qn, so as to obtain the voltage VOP of the node output by the first charge pump 220 and the input voltage VIN with different multiplication ratios;
the second charge pump 230 has an input terminal connected to the output terminal of the gate driver 210 and the output terminal of the first charge pump 220, respectively, and is configured to generate a negative voltage VOL according to the node voltage VOP in response to the first driving signal Qm or the second driving signal Qn,
The first driving signal Qm and/or the second driving signal Qn are used for respectively indicating the on/off state of the transistor of at least one of the first charge pump 220 and the second charge pump 230, and the second driving signal Qn and the first driving signal Qm are mutually opposite signals.
Further, the power supply circuit 200 further includes: a positive voltage regulator 240 and a negative voltage regulator 250, wherein the positive voltage regulator 240 is connected to the output terminal of the first charge pump 220, and is configured to convert the voltage VOP of the split node into a first output power supply Vdd and output the first output power supply Vdd to the positive voltage output terminal ELVDD; the negative voltage regulator 250 is connected to the output terminal of the second charge pump 230, and is configured to convert the negative voltage VON into the second output power Vss, output the second output power Vss to the negative voltage output terminal ELVSS,
The first output power supply Vdd is a positive power supply with a first target voltage, and the second output power supply Vss is a negative power supply with a second target voltage.
In particular, in the present embodiment, the positive voltage regulator 240 and the negative voltage regulator 250 are, for example, low dropout linear regulators (LDOs), and it is known that the low dropout linear regulators (LDOs) have low cost, low noise and small quiescent current, which are outstanding advantages, and require few external components and have small loss. LDO (low dropout) regulators with a positive output voltage typically use power transistors (also called pass devices) as PNP, which allow saturation, so the regulator can have a very low drop-off voltage, typically around 200 mV; in contrast, the voltage drop of a conventional linear regulator using NPN composite power transistors is about 2V. The negative output LDO uses NPN as its pass device and its operation mode is similar to PNP device of the positive output LDO. A newer development is the use of CMOS power transistors that can provide the lowest drop out voltage.
Further, the aforementioned first charge pump 220 is a variable-rate charge pump (Ratio Variable Charge Pump), and the multiplication ratio of the voltage VOP at the node output by the first charge pump 220 to the input voltage Vin is greater than 0 and less than or equal to 1, or greater than 1.
Further, referring to fig. 3a and 3b, in one embodiment, the first charge pump 220 has a first input terminal connected to the voltage input terminal VIN, a second input terminal connected to the gate driver 210, and a third input terminal, a first output terminal providing the split node voltage VOP, and further includes: transistor Q1, transistor Q2, transistor Q3, transistor Q4, capacitor C1, capacitor C2 and capacitor C3,
Wherein, the transistors Q1, Q2, Q3 and Q4 are connected in series between the first input terminal and the ground, and the control terminals of the transistors Q1 and Q3 are commonly connected as the second input terminal, to which the first driving signal Qm is connected, and the control terminals of the transistors Q2 and Q4 are commonly connected as the third input terminal, to which the second driving signal Qn is connected;
A capacitor C3 having a first terminal connected to a connection node between the transistor Q1 and the transistor Q2, a second terminal connected to a connection node between the transistor Q3 and the transistor Q4, and a connection node between the transistor Q2 and the transistor Q3 as the first input terminal, the capacitor C1 being connected between the first input terminal and ground; a capacitor C2 is connected between the first output terminal and the connection node of the transistor Q1 and ground.
Further, the second charge pump 230 has a fourth input terminal connected to the first output terminal, a fifth input terminal and a sixth input terminal connected to the gate driver 210, a second output terminal providing the negative voltage VOL, and further includes: transistor Q5, transistor Q6, transistor Q7, transistor Q8, capacitor C4, capacitor C5 and capacitor C6,
Wherein, the transistor Q5, the transistor Q6, the transistor Q7 and the transistor Q8 are connected in series between the fourth input terminal and the second output terminal, the control terminal of the transistor Q5 and the control terminal of the transistor Q7 are commonly connected as the fifth input terminal, the first driving signal Qm is connected, the control terminal of the transistor Q6 and the control terminal of the transistor Q8 are commonly connected as the sixth input terminal, the second driving signal Qn is connected, and the connection node of the transistor Q6 and the transistor Q7 is grounded;
A capacitor C4 is connected between the fourth input terminal and the connection node of the transistor Q5 and ground;
The first end of the capacitor C5 is connected to the connection node of the transistor Q5 and the transistor Q6, and the second end of the capacitor C5 is connected to the connection node of the transistor Q7 and the transistor Q8;
A capacitor C6 is connected between the aforementioned second output terminal and the connection node of the transistor Q8 and ground.
Further, any one of the aforementioned transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 is a metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FILED EFFECT Transistor, abbreviated as MOS Transistor).
Further, the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8 are all N-type MOS transistors. Of course, the disclosure is not limited thereto, and the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8 may be P-type MOS transistors or others, and the corresponding driving signals and circuit connection relations thereof may be adaptively changed, which is not described herein.
Further, referring to fig. 3c, in another embodiment, the first charge pump 220 and the second charge pump 230 can be simplified and integrated into a circuit, by multiplexing the gate driver 210, and reducing part of the voltage stabilizing capacitance, on one hand, the circuit density is improved, and on the other hand, the wafer area required for gate driving is reduced, so that the overall area of the circuit is reduced, and on the other hand, the corresponding power loss is also reduced. It is intended that the control terminals of the transistors Q1, Q3, Q5 and Q7 are commonly connected to the gate driver 210 to access the aforementioned first driving signal Qm, and the control terminals of the transistors Q2, Q4, Q6 and Q8 are commonly connected to the gate driver 210 to access the aforementioned second driving signal Qn, and the divided node voltage VOP is supplied to the subsequent positive voltage regulator 240 and the negative voltage VOL is supplied to the subsequent negative voltage regulator 250, respectively.
Specifically, the first charge pump 220 uses its own input/output pass-through function (1-time mode) to transfer the input voltage Vin to the intermediate node to generate the split node voltage VOP; if the input voltage Vin is insufficient, the variable-rate charge pump (the first charge pump 220) boosts the input voltage Vin to a certain rate (such as 1.33 times, 1.5 times, 2 times, etc.) to generate a node voltage VOP; alternatively, when the input voltage Vin is particularly high, the voltage-reducing function (e.g., 0.33 times, 0.5 times, etc.) of the variable charge pump (the first charge pump 220) may be utilized to output the voltage VOP at the split node. The divided node voltage VOP is then stepped down by an LDO (positive voltage regulator 240) to generate a first output power supply Vdd, which is supplied to a subsequent stage circuit through a positive voltage output terminal ELVDD. The circuit for generating the intermediate node voltage VON by the negative voltage charge pump 130 and generating the output negative voltage via the LDO 150 has a large number of mature commercial products, and will not be described in detail herein.
Further, the logic control unit 210, the first charge pump 220, the second charge pump 230, the positive voltage regulator 240 and the negative voltage regulator 250 of the power circuit 200 are integrated on a chip.
Further, the power supply circuit 200 is connected to: a voltage stabilizing capacitor Cm, which is located outside the chip and is coupled to the first charge pump 220.
Further, the voltage stabilizing capacitor Cm can be designed to be changed into 1 or more partial capacitors according to different multiplying power requirements.
In the first embodiment shown in fig. 2, the voltage input terminal VIN of the power circuit 200 is connected to a dc voltage-stabilizing power supply, which is used to provide the input voltage VIN, and specifically, the dc voltage-stabilizing power supply includes a buck converter 202 and an inductor Ls connected in series between the battery supply terminal VBAT and the voltage input terminal VIN.
Further, the display panel is an Active Matrix Organic Light Emitting Diode (AMOLED) panel (Active Matrix Organic LIGHT EMITTING Diode).
Embodiment two:
Fig. 4 is a schematic structural diagram of a power circuit based on a capacitor architecture for an active matrix organic light emitting diode panel according to a second embodiment of the present disclosure.
In the second embodiment shown in fig. 4, the circuit configuration and principle of the power supply circuit 200 are substantially the same as those of the first embodiment described above, except that: the power supply source of the input voltage Vin is different from the external dc voltage stabilizing source in the first embodiment, in this embodiment, the dc voltage stabilizing source part inside the power supply system (or chip) is integrated on the chip of the power supply circuit 200, wherein the external connection battery supply terminal VBAT of the voltage input terminal Vin is connected to the ground through the buck converter 202, the inductor Ls and the capacitor Ci1 connected in series, and the connection node of the inductor Ls and the capacitor Ci1 provides the input voltage Vin to the first charge pump 220,
The inductor Ls and the capacitor Ci1 are distributed outside the integrated chip of the power circuit 200, the buck converter 202 is integrated inside the power chip, and a grounding capacitor Ci2 is coupled to the connection node of the voltage input terminal VIN and the battery supply terminal VBAT.
In the application occasions with compact sizes such as intelligent bracelets and intelligent watches, the size (area and height) of the inductor is too large, the circuit design and the product thickness design can be influenced, customers are indirectly influenced to be forced to thicken the bracelets and the watches, meanwhile, the inductor with relatively smaller size but larger direct current impedance DCR is forced to be selected, the working efficiency is sacrificed, and the standby time is reduced.
The embodiment of the disclosure adopts an inductance-free scheme of a charge pump structure, so that the influence of the inductance size on the design of a product is directly eliminated, and the total area of a power circuit is effectively reduced;
In the first embodiment, an external direct current stabilized power supply is used as an input power supply, so that the cost and the total area of a circuit can be saved, different customers or application scenes can be conveniently selected, and in the second embodiment, the available power supply in the multiplexing system can be saved, and the cost can be saved and an inductance can be reduced; there are price and efficiency advantages even with external power sources;
While the voltage-doubler charge pump (first charge pump 220) and the negative voltage charge pump (second charge pump) are completely symmetrical in structure and can achieve nearly 100% efficiency conversion without regard to switching losses, driving losses, and the like. Compared with other structural system power supplies, the efficiency loss in LDO is the same, the efficiency of the voltage-stabilized power supply with the Buck circuit is generally much higher than that of Boost or Buck-Boost, so that the overall efficiency of the voltage-stabilized power supply with the Buck circuit is obviously better than that of other structural power supplies, and the efficiency of the power supply circuit 200 can be improved whether the voltage-stabilized power supply with the Buck circuit is external or internal;
in addition, the power circuit 200 can eliminate the problem of electromagnetic interference EMI commonly existing in power circuits of an inductive architecture, and further reduce the cost of power chips and peripheral circuits while improving the working efficiency of the power supply.
Embodiment III:
Fig. 5 is a schematic structural view of an active matrix organic light emitting diode panel according to a third embodiment of the present disclosure, and fig. 6 is a schematic structural view of a load circuit in the active matrix organic light emitting diode panel shown in fig. 5.
Referring to fig. 5 and 6, another aspect of the present disclosure also provides a display panel 10, where the display panel 10 includes, for example:
A load circuit 300 for generating a driving current to drive the light emitting element DLE; and
The power circuit 200 as described above is configured to provide positive power as well as negative power to the load circuit 300 as described above.
Referring to fig. 6, the load circuit 300 is a relatively mature circuit product of the prior art, and as a rational description herein, for example, includes: transistors T1, T2, T3, T4, T5 and T6, as well as a storage capacitor Cst and a light emitting element DLE,
The first end of the transistor T1 is connected to the DATA signal DATA, the second end is connected to the positive voltage output end ELVDD of the power circuit 200 through the transistor T2, the first output power is connected to the second end, and the control end is connected to the (n) -th stage scanning signal SCAN;
the transistor T3, the transistor T4 and the light emitting element DLE are connected in series between the connection node of the transistor T1 and the transistor T2 and the negative voltage output end ELVSS of the power circuit 200, and the control end of the transistor T4 and the control end of the transistor T2 are commonly connected and connected with the (n) -th level enable signal EM [ n ];
The storage capacitor Cst is connected in series with the transistor T5, wherein the positive electrode of the storage capacitor Cst is connected with the positive voltage output end ELVDD of the power circuit 200, the negative electrode is connected with the first end of the transistor T5, the control end of the transistor T5 is connected with the (n-1) -th level scanning signal SCAN-1, and the second end receives the low level Vint;
The first end of the transistor T6 is connected to the control end of the transistor T3, the second end is connected to the second end of the transistor T3, and the control end is connected to the control end of the transistor T1.
Further, the display panel 10 is an Active Matrix Organic Light Emitting Diode (AMOLED) panel, and the light emitting element DLE is a light emitting diode.
Further, the transistors T1, T2, T3, T4, T5 and T6 are all thin film transistors, specifically, the transistor T3 is a driving thin film transistor (DRIVER TFT), and the transistor T1 is a switching thin film transistor (SWITCH TFT). The rest of the transistor groups are used as compensation circuits for matching and compensating the variation of the driving current of the light emitting element DLE caused by the drift of the threshold voltage of the driving thin film transistor T3, and for stabilizing the potential of the gate of the driving thin film transistor T3, so as to stabilize the driving current of the light emitting element DLE generated by the load circuit 300, the stability of the driving current of the light emitting element DLE will not affect the light emitting brightness of the light emitting element DLE, and further the image quality of the display panel applied by the load circuit 300 is improved.
In this embodiment, the first end is a source electrode, and the second end is a drain electrode. In other embodiments, the first end may be a drain, and the corresponding second end may be a source.
Embodiment four:
In another aspect, the disclosed embodiments also provide a display device (not shown) including the display panel 10 as described in the foregoing embodiments, more specifically, the display panel 10 is an active matrix organic light emitting diode panel (AMOLED).
In summary, the power supply circuit 200, the display panel 10 and the display device (not shown) provided in the embodiments of the disclosure, wherein the power supply circuit 200 has a voltage input terminal VIN, a control signal input terminal CTRL, a positive voltage output terminal ELVDD and a negative voltage output terminal ELVSS, and the logic control unit 201 in the power supply circuit 200 is utilized to generate the clock signal Qc according to the accessed control signal CTRL; the gate driver 210 generates a first driving signal Qm and a second driving signal Qn according to the input voltage Vin and the clock signal Qc; the first charge pump 220 is then operated in a plurality of modes in response to the first driving signal Qm or the second driving signal Qn to output the voltage VOP at the node having a different multiplication ratio from the input voltage Vin; then, the second charge pump 230 is used to respond to the first driving signal Qm or the second driving signal Qn, and generate a negative voltage VON according to the aforementioned node voltage VOP, and then the voltage regulator (the positive voltage regulator 240 and the negative voltage regulator 250) is used to process the node voltage VOP and the negative voltage VON respectively, so as to generate the positive power Vdd and the negative power Vss required by the subsequent circuit correspondingly, where the first driving signal Qm and/or the second driving signal Qn are used to indicate the on/off of at least one transistor in the first charge pump 220 and the second charge pump 230 respectively, and the second driving signal Qn and the first driving signal Qm are mutually inverted signals. The power circuit 200 adopts an inductance-free scheme of a charge pump structure, so that the inductance size problem can be eliminated, the electromagnetic interference EMI problem can be improved, and the area of a power chip can be effectively reduced;
In the first embodiment, an external direct current stabilized power supply is used as an input power supply, so that the cost and the total area of a circuit can be saved, different customers or application scenes can be conveniently selected, and in the second embodiment, the available power supply in the multiplexing system can be saved, and the cost can be saved and an inductance can be reduced; there are price and efficiency advantages even with external power sources;
While the voltage-doubler charge pump (first charge pump 220) and the negative voltage charge pump (second charge pump) are completely symmetrical in structure and can achieve nearly 100% efficiency conversion without regard to switching losses, driving losses, and the like. Compared with other structural system power supplies, the efficiency loss in LDO is the same, the efficiency of the voltage-stabilized power supply with the Buck circuit is generally much higher than that of Boost or Buck-Boost, so that the overall efficiency of the voltage-stabilized power supply with the Buck circuit is obviously better than that of other structural power supplies, and the efficiency of the power supply circuit 200 can be improved whether the voltage-stabilized power supply with the Buck circuit is external or internal;
In addition, the power supply circuit 200 can eliminate the problem of electromagnetic interference EMI commonly existing in power supply circuits of an inductive architecture, and reduce the cost of power supply chips and peripheral circuits while further improving the working efficiency of the power supply.
Therefore, the power supply circuit, the display panel and the display device with the power supply circuit have extremely high practicability and compatibility, and are suitable for popularization and application.
It should be noted that in the description of the present disclosure, it should be understood that the terms "upper," "lower," "inner," and the like indicate an orientation or a positional relationship, and are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the components or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.
Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it is apparent that the above examples are merely illustrative of the present disclosure and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present disclosure.
Claims (15)
1. A power supply circuit for a display panel, the power supply circuit having a voltage input, a control signal input, a positive voltage output, and a negative voltage output, wherein the power supply circuit further comprises:
The logic control unit is connected with the control signal input end and used for generating a clock signal according to the accessed control signal;
A gate driver connected to an output terminal of the logic control unit, the gate driver configured to generate a first driving signal and a second driving signal according to an input voltage and the clock signal;
a first charge pump having an input connected to the voltage input and the output of the gate driver, respectively, configured to operate in a plurality of modes in response to the first or second drive signals, to obtain a split node voltage output by the first charge pump at a different multiplication ratio to an input voltage;
A second charge pump having an input connected to the output of the gate driver and the output of the first charge pump, respectively, configured to generate a negative voltage according to the node voltage in response to the first driving signal or the second driving signal,
The first driving signal and/or the second driving signal are/is used for respectively indicating the on/off state of a transistor of at least one of the first charge pump and the second charge pump, and the second driving signal and the first driving signal are mutually opposite signals.
2. The power supply circuit of claim 1, further comprising:
the positive voltage stabilizer is connected with the output end of the first charge pump and used for converting the voltage of the split node into a first output power supply and outputting the first output power supply to the positive voltage output end;
The negative voltage stabilizer is connected with the output end of the second charge pump and used for converting the negative voltage into a second output power supply and outputting the second output power supply to the negative voltage output end,
The first output power supply is a positive power supply with a first target voltage, and the second output power supply is a negative power supply with a second target voltage.
3. The power supply circuit of claim 2, wherein a multiplication ratio of the divided node voltage of the first charge pump output to the input voltage is obtained to be greater than 0 and less than or equal to 1, or greater than 1.
4. The power supply circuit of claim 3, wherein the first charge pump has a first input connected to the voltage input, a second input connected to the gate driver, and a third input, a first output providing the split node voltage, and further comprising:
a first transistor, a second transistor, a third transistor and a fourth transistor connected in series between the first input end and the ground, wherein the control ends of the first transistor and the third transistor are commonly connected to serve as the second input end, connected to the first driving signal, and the control ends of the second transistor and the fourth transistor are commonly connected to serve as the third input end, connected to the second driving signal;
A first capacitor, wherein a first end of the first capacitor is connected with a connection node of the first transistor and the second transistor, and a second end of the first capacitor is connected with a connection node of the third transistor and the fourth transistor;
a second capacitor, wherein a connection node of the second transistor and the third transistor is used as the first input end, and the second capacitor is connected between the first input end and ground;
And the third capacitor is connected between the first output end and the connection node of the first transistor and ground.
5. The power supply circuit of claim 4, wherein the second charge pump has a fourth input terminal connected to the first output terminal, a fifth input terminal and a sixth input terminal connected to the gate driver, a second output terminal providing the negative voltage, and further comprising:
A fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor connected in series between the fourth input terminal and the second output terminal, wherein the control terminals of the fifth transistor and the seventh transistor are commonly connected as the fifth input terminal, the first driving signal is accessed, the control terminals of the sixth transistor and the eighth transistor are commonly connected as the sixth input terminal, the second driving signal is accessed, and the connection node of the sixth transistor and the seventh transistor is grounded;
A fourth capacitor, wherein a first end of the fourth capacitor is connected to a connection node between the fifth transistor and the sixth transistor, and a second end of the fourth capacitor is connected to a connection node between the seventh transistor and the eighth transistor;
and a fifth capacitor connected between the second output terminal and a connection node of the eighth transistor and ground.
6. The power supply circuit according to claim 5, wherein any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a metal oxide semiconductor field effect transistor.
7. The power supply circuit of claim 5, wherein the power supply circuit is integrated on a chip.
8. The power supply circuit according to claim 7, wherein the power supply circuit is connected with:
and the voltage stabilizing capacitor is positioned outside the chip and is coupled with the first charge pump.
9. The power supply circuit of claim 8, wherein a dc regulated power supply is connected to a voltage input of the power supply circuit, the dc regulated power supply being configured to provide the input voltage.
10. The power circuit of claim 8, wherein an external connection of a voltage input of the power circuit is a battery-powered terminal, an internal connection is connected to ground through a series connection of a buck converter, an inductor, and a capacitor, and a connection node of the inductor and the capacitor provides the input voltage to the first charge pump,
The inductor and the capacitor are distributed outside the power circuit integrated chip.
11. The power supply circuit of claim 9 or 10, wherein the display panel is an active matrix organic light emitting diode panel.
12. A display panel, comprising:
a load circuit for generating a driving current to drive the light emitting element; and
The power supply circuit of any one of claims 1-11, configured to provide positive power and negative power to the load circuit.
13. The display panel of claim 12, wherein the load circuit comprises:
the first end of the first transistor is connected with a data signal, the second end of the first transistor is connected with the positive voltage output end of the power circuit through the second transistor, and the control end of the first transistor is connected with an (n) -th scanning signal;
the third transistor, the fourth transistor and the light-emitting element are connected in series between the connection node of the first transistor and the second transistor and the negative voltage output end of the power supply circuit, and the control end of the fourth transistor and the control end of the second transistor are connected in common to be connected with an (n) -th level enabling signal;
The positive electrode of the storage capacitor is connected with the positive voltage output end of the power supply circuit, the negative electrode of the storage capacitor is connected with the first end of the fifth transistor, the control end of the fifth transistor is connected with the (n-1) -th level scanning signal, and the second end of the fifth transistor receives a low level; and
And a sixth transistor, wherein a first end of the sixth transistor is connected with the control end of the third transistor, a second end of the sixth transistor is connected with the second end of the third transistor, and the control end of the sixth transistor is connected with the control end of the first transistor.
14. The display panel of claim 13, wherein the display panel is an active matrix organic light emitting diode panel and the light emitting element is a light emitting diode.
15. A display device, comprising: the display panel according to any one of claims 12 to 14.
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