CN114826503B

CN114826503B - Method and device for calibrating parallel bus data sampling window in FPGA

Info

Publication number: CN114826503B
Application number: CN202210732787.5A
Authority: CN
Inventors: 邬刚; 陈永
Original assignee: Hangzhou Acceleration Technology Co ltd
Current assignee: Hangzhou Acceleration Technology Co ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2022-09-27
Anticipated expiration: 2042-06-27
Also published as: CN114826503A

Abstract

The invention provides a method and a device for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array), wherein the method comprises the following steps: the parallel bus transmits a first clock signal and a calibration signal; the time delay sampling unit is used for sampling the calibration signal and the first clock signal transmitted by each data channel; analyzing the sampling data to obtain the time difference of transmitting the calibration signal to the delay unit through the parallel bus among the channels; and the time calibration delay unit is synthesized so that the data transmitted by each channel can reach the interface sampling unit at the same time, and the sampling node of the sampling clock is always positioned in the stable area of the parallel bus data sampling window. The scheme of the invention can realize the calibration of the parallel bus data sampling window, has high calibration speed, high calibration precision and low calibration cost, and the sampling node of the sampling clock is always positioned in the stable area of the parallel bus data sampling window, so that the calibration can be realized by means of the hardware resources of the FPGA without additional hardware.

Description

Method and device for calibrating parallel bus data sampling window in FPGA

Technical Field

The invention relates to the field of parallel bus communication, in particular to a method and a device for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array).

Background

With the continuous development of semiconductor technology, FPGA (field programmable gate array) chips have been widely used in many fields such as artificial intelligence, big data analysis, cloud computing, network communication, image processing, robots, semiconductor manufacturing equipment, and medical devices. In some fields, FPGA chips are even replacing the position of CPUs, GPUs or DSPs, becoming the dominant chip.

Data transmission between the FPGA chip and an external chip or device has two modes of a serial bus and a parallel bus. With the increasing requirements of service end on data transmission rate, the communication bus is also continuously developed and advanced. At present, the transmission rate of the serial bus is higher and reaches dozens of Gbit/s, however, the channel cost of the high-speed serial bus is higher, the requirement on transmission wires or circuit board plates is also higher, and the rate of the serial bus is more and more difficult to break through on the basis of the dozens of Gbit/s. Compared with a serial bus, the high-speed parallel communication bus can greatly reduce the speed of each data channel on the premise of the same total transmission bandwidth, so that the cost of the bus transmission channel is reduced, and the high-speed parallel communication bus is widely used in many fields such as high-speed digital-to-analog conversion, high-speed analog-to-digital conversion, high-definition image processing and the like.

The parallel bus uses n transmission lines to transmit n bits of binary information simultaneously, and because the parallel data are transmitted together in a group, each bit must be transmitted together. With the increase of transmission frequency, due to the limitation of physical devices or processes, a small difference between the transmission time delay of the data bus and the clock bus on the board PCB or the cable may cause that the receiving end cannot sample the data bus correctly, resulting in communication errors. Meanwhile, the change of external conditions such as the working environment and the working temperature of the electrical equipment can also bring changes to the performance of the electrical equipment, the bus delay and the like, so that sampling deviation is caused, and communication errors are caused. The above is also a difficulty in limiting the frequency of parallel bus transmissions.

The interconnection between the chips transmits data through a parallel interface of system synchronization or source synchronization. Description figure 1 shows a system synchronous parallel bus schematic and description figure 2 shows a source synchronous parallel bus schematic.

During parallel bus communication, there are several factors that affect the efficient sampling of communication data. 1. The propagation delay of the clock to the two chips is not equal (clock skew); 2. the propagation delay of each bit of the parallel data is unequal (data skew); 3. the propagation delay of the clock is not consistent with the propagation delay of the data (skew data and clock).

During transmission, data can only be correctly acquired by performing a sampling action in a data sampling window. The erroneous or metastable sampling state is shown in the figure 4 of the specification, and the setup time and the hold time of the trigger are required to be ensured during the acquisition. Due to the interference limitations of physical layers such as line length and temperature, when the difference between the data channels is large, the sampling time point suitable for a certain channel is probably not suitable for other channels. In fig. 3, the first group shows the relationship between the parallel bus transmission clock and the bus transmission data, taking the rising edge as the sampling time, and the rising edge of each period is always located in the data sampling window. And the second group shows the form of a data sampling window of the source synchronous parallel bus in the transmission process, the width of the data sampling window is small, and the rising edge of the clock cannot be ensured to be positioned in the data sampling window area. And the third group shows the form of a data sampling window of the system synchronous parallel bus in the transmission process, and the data sampling window is close to zero, so that the sampling accuracy cannot be ensured.

In the prior art, there is a scheme that an effective and stable data sampling window of a parallel bus is found in a continuous trial and error manner by continuously calibrating a phase relationship between each data channel and a clock by using a training method. However, this scheme not only requires a lot of time, but also the stable data sampling window obtained by the attempted method may be at the metastable edge, and communication may be in error after slight change of communication environment.

Disclosure of Invention

In view of this, the invention provides a method and a device for calibrating a parallel bus data sampling window in an FPGA, and the specific scheme is as follows:

a method for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array) comprises the following steps:

a preset first clock signal is transmitted to the FPGA through a clock channel of the parallel bus, and a calibration signal is transmitted to the FPGA through n data channels of the parallel bus; n is a natural number greater than 0;

the FPGA is preset with a delay unit, an interface sampling unit and at least n +1 delay sampling units; a sampling node is set in a clock period of the first clock signal;

selecting n delay sampling units to sample calibration signals transmitted by n data channels, and analyzing to obtain channel sampling data of the n data channels; selecting a delay sampling unit to sample the first clock signal, and analyzing to obtain clock sampling data;

analyzing the clock sampling data and the channel sampling data of the n data channels to obtain the time difference between the first clock signal and the time difference between the calibration signal transmitted by the n data channels and the time difference between the first clock signal and the time difference;

the time difference is synthesized to calibrate parts of the delay unit, which are related to the clock channel and the n data channels, so that calibration signals transmitted by the n data channels reach the interface sampling unit at the same time, and the sampling node of the first clock signal is always positioned in a stable area of a parallel bus data sampling window;

based on the calibrated delay unit, the interface sampling unit takes the first clock signal calibrated by the delay unit as a sampling clock, channel data transmitted by n data channels of the parallel bus simultaneously reach the interface sampling unit, and a sampling node of the interface sampling unit is always positioned in a stable area of a data sampling window.

In a specific embodiment, at least one level change pulse is present in the calibration signal, and the duration of the level change pulse is at least one clock cycle of the first clock signal.

In a specific embodiment, the calibration signal is specifically:

before the calibration is started, a sending end continuously sends signals with data of all 0 through n data channels of a parallel bus;

after calibration is started, a sending end continuously sends signals with data all being 1 through n data channels of a parallel bus, and at least continues for one clock cycle of the first clock signal;

and after continuously sending all 1 signals, the sending end continuously sends all 0 data signals through n data channels of the parallel bus.

In a specific embodiment, each delay sampling unit takes a preset second clock signal as a sampling clock to perform synchronous sampling;

the delay sampling unit comprises a trigger and a delay carry chain formed by sequentially connecting a plurality of sub-chains in series, and the output end of each sub-chain is connected with one trigger;

each sub-chain is responsible for executing a section of delay time;

each trigger is responsible for sampling data after the sub-chain connected with the trigger and all the sub-chains before the sub-chain are delayed together to obtain sampling data;

and analyzing the sampling data of each delay sampling unit to obtain channel sampling data and clock sampling data.

In a particular embodiment, the channel sample data includes periodic data and delay data;

the period data is a sampling period where the initial edge of the level change pulse is actually located;

the delay data is the delay time of the start edge of the level change pulse relative to the sampling node of the sampling period in which the start edge is actually located.

In a specific embodiment, the channel sampling data acquisition process for each data channel includes:

numbering each trigger based on the sequence relation of the sub-chains;

in the t +1 th sampling period, when the sampling data obtained by a certain trigger is inconsistent with the sampling data obtained by the previous trigger, namely the initial edge or the termination edge of the level change pulse is obtained, and the trigger is used as an edge trigger; wherein t is a natural number greater than 0;

judging whether the acquired signal is a starting edge or not based on the level change pulse, if so, then:

determining that the initial edge is actually in the t-th sampling period to obtain period data;

integrating delay time lengths of all triggers in front of the edge trigger and corresponding sub chains of all triggers, and calculating delay time of the initial edge relative to a sampling node of the t-th sampling period to obtain delay data;

the periodic data and the delay data constitute channel sampling data of the channel.

In one embodiment, the size of the periodic data in the sampled data of each data channel is compared, and one or more data channel sampled data with the largest sampling period of the initial edge are screened out;

if one data channel sampling data is screened out, taking a channel corresponding to the channel sampling data as a reference channel;

if a plurality of data channel sampling data are screened out, further selecting the channel sampling data with the largest delay data from the data channel sampling data, and taking the channel corresponding to the channel sampling data as a reference channel.

In a specific embodiment, calculating a difference value between the time that the channels except the reference channel transmit the calibration signal to the delay unit through the parallel bus and the time that the reference channel transmits the calibration signal to the delay unit through the parallel bus to obtain a time difference;

and calibrating the delay unit based on the clock sampling data and the time difference so that the calibration signals sent by the data channels simultaneously reach the interface sampling unit, and each sampling node in the first clock signal after delay calibration is positioned in a stable region of a parallel bus data sampling window.

In a specific embodiment, the data sampling window is divided into a first portion, a second portion and a third portion in sequence, the stable region is located in the second portion, and the first portion and the third portion are respectively not less than 20% of the data sampling window.

A calibration device for a parallel bus data sampling window in an FPGA is used for the calibration method of any one of the above items; the calibration device is positioned on the FPGA;

a clock channel of the parallel bus transmits a first clock signal, and n data channels transmit channel data to the FPGA;

the calibration device comprises a calculation unit, a delay control unit and at least n +1 delay sampling units;

the delay sampling unit is used for inputting a first clock signal transmitted by the parallel bus and channel data transmitted by the n data channels into the delay carry chain, and sampling data of the first clock signal and the channel data after delay of each sub-chain of the delay carry chain to obtain sampling data related to a clock and sampling data related to each channel;

the calculating unit is connected with the delay control unit and each delay sampling unit and is used for acquiring sampling data of the delay sampling unit, obtaining clock sampling data and channel sampling data of n data channels, calculating calibration parameters of the delay unit and outputting the calibration parameters to the delay control unit;

and the delay control unit is used for calibrating the delay unit of the FPGA according to the calibration parameters output by the calculation unit so as to synchronously input the channel data transmitted by the n data channels into the interface sampling unit of the FPGA for sampling through the delay of the delay unit, and the sampling node is always positioned in the stable region of the parallel bus data sampling window.

Has the advantages that: the invention provides a method and a device for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array), which can quickly realize the calibration of the parallel bus data sampling window, and have the advantages of high calibration speed, high calibration precision and low calibration cost. By calibrating the time of the sampled clock signal and the data sent by the channels at the same time, the sampling nodes of the sampling clock are ensured to be always positioned in the stable area of the parallel bus data sampling window on the premise that the data sent by each channel is synchronously input into the interface sampling unit. The calibration can be realized by means of hardware resources in the FPGA, and extra hardware cost is not needed.

Drawings

FIG. 1 is a schematic diagram of a system synchronous parallel bus;

FIG. 2 is a schematic diagram of a source synchronous parallel bus;

FIG. 3 is a schematic diagram of a clock and data sampling window;

FIG. 4 is a schematic diagram of the error of the search window by calibrating the clock phase;

FIG. 5 is a flowchart illustrating a calibration method according to an embodiment of the present invention;

FIG. 6 is a block diagram of a calibration device according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating a sampling data principle of a delay sampling unit according to an embodiment of the present invention;

fig. 8 is a schematic flow chart illustrating a sampling effect of the calibration method according to the embodiment of the present invention.

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Reference numerals: 1-FPGA; 2-calibrating the device; 10-a differential buffer; 11-a delay unit; 12-an interface sampling unit; 13-a time-delay sampling unit; 14-a calculation unit; 15-delay control unit.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be described more fully. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather, the present disclosure is to be understood as covering all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the present disclosure.

It should be noted that the sampling node in the present application refers to a specific time of each clock cycle, and when the sampling node reaches each sampling clock cycle, the sampling operation is started. The sampling clock is a clock signal that contains the sampling nodes. Typically, the sampling node is the time of the rising edge of each sampling clock cycle.

In this application, the calibration signal is simply set to a signal in which a level-change pulse is present. The level change pulse refers to a state in which a level inversion occurs and lasts for a certain time, and the level inversion includes changing from 0 to 1 and also includes changing from 1 to 0. For example, the transmitting end continuously transmits all 0 data through the parallel bus in the initial period, continuously transmits all 1 data through the parallel bus in the intermediate stage, and continuously transmits all 0 data through the parallel bus in the end stage, and a state equivalent to a high level pulse is formed in the intermediate stage. Both the high-level pulse and the low-level pulse may be level-change pulses.

It should be noted that the delay-carry chain of the present application needs to maintain high precision, and therefore, the delay time of each sub-chain is calibrated.

It should be noted that, the sampling period in this application is each clock period of the sampling clock. In fig. 8, each clock cycle of the delayed sampling clock is one sampling period.

The terminology used in the various embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the disclosure belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.

Example 1

The embodiment 1 of the invention discloses a method for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array). by calibrating the phase difference between a parallel bus clock and transmission data, data are synchronously input into an interface sampling unit, and a sampling node is always positioned in the parallel bus data sampling window, so that high-speed stable sampling is realized. The flow schematic description of the calibration method is shown in fig. 5, and the specific scheme is as follows:

a calibration method for a parallel bus data sampling window in an FPGA comprises the following steps:

101. a preset first clock signal is transmitted to the FPGA through a clock channel of the parallel bus, and a calibration signal is transmitted to the FPGA through n data channels of the parallel bus; n is a natural number greater than 0;

the FPGA is preset with a delay unit, an interface sampling unit and at least n +1 delay sampling units; a sampling node is set in each clock cycle of the first clock signal;

102. selecting n delay sampling units to sample calibration signals transmitted by n data channels, and analyzing to obtain channel sampling data of the n data channels; selecting a delay sampling unit to sample a first clock signal, and analyzing to obtain clock sampling data;

103. analyzing the clock sampling data and the channel sampling data of the n data channels to obtain the time difference of the first clock signal and the calibration signal transmitted by the n data channels to the time delay unit;

104. integrating the parts of the time difference calibration delay unit, which relate to the clock channel and the n data channels, so that calibration signals transmitted by the n data channels can simultaneously reach the interface sampling unit, and the sampling node of the first clock signal is always positioned in a stable area of a parallel bus data sampling window;

105. based on the calibrated delay unit, the interface sampling unit takes a first clock signal calibrated by the delay unit as a sampling clock, channel data transmitted by n data channels of the parallel bus simultaneously reach the interface sampling unit, and a sampling node clock of the interface sampling unit is positioned in a stable area of a data sampling window of the parallel bus.

Wherein, in step 101-104, the parameters of the delay unit are calibrated mainly by the calibration signal, and step 105 can be executed based on the calibrated delay unit to realize normal channel data transmission. The calibration signal is simple binary data, wherein level change pulses are configured, and the acquisition of the level change pulses determines when data sent by each data channel reaches a delay carry chain in the FPGA, so as to judge the phase error between the data channels. Ideally, each sampling node of the bus transmission clock is located in the middle area of the parallel bus data sampling window, but due to the influence of the length of the parallel bus line, there may be different delays of the data channel and the clock channel, and when the difference of the line length between the clock signal line (i.e. the clock channel) and each data signal line (i.e. the data channel) is large, an effective sampling action cannot be performed basically.

According to the calibration method, the phase errors between the clock signals and the data of the parallel bus are calibrated simultaneously, so that the data transmitted by each channel are synchronously input into the interface sampling unit, the sampling nodes of the sampling clock are always positioned in the stable region of the data sampling window of the parallel bus, the problem of metastable state does not exist, and the interference of external environment factors such as temperature is not easy to occur. And a data sampling window does not need to be searched bit by bit, so that the calibration speed is high, and the test cost is low.

For the calibration method, the present embodiment provides a calibration apparatus for performing the method. The module schematic diagram of the calibration device is shown in the specification and figure 6. And a calibration device, a differential buffer, a delay unit and an interface sampling unit are configured in the FPGA. The differential buffer, the delay unit and the interface sampling unit are all modules configured by the FPGA for matching with the parallel bus interface. The calibration device comprises a delay sampling unit, a calculation unit and a delay control unit. Under the normal condition, an ideal module and a delay carry chain are integrated in the FPGA, the ideal module is used as a delay unit, the hardware of the FPGA is slightly changed, the sampling cost is low, and extra hardware equipment resources are not needed.

Wherein the number of delay sampling unit applications depends on the number of parallel bus channels to be calibrated. And one delay sampling unit is responsible for sampling data transmitted by one data channel. If n data channels of the chip need to be tested, n +1 delay sampling units need to be selected, wherein the n delay sampling units are responsible for delaying and sampling data transmitted by the n data channels, and the other delay sampling unit is responsible for delaying and sampling a first clock signal. And each delay sampling unit takes a preset second clock signal as a sampling clock to perform synchronous sampling.

After the first clock signal is calibrated by the delay unit, the interface sampling unit performs a sampling operation by using the first clock signal as a sampling clock. And after the time delay calibration, each period sampling node of the first clock signal is just in the stable region of the parallel bus data sampling window, so that the interface sampling unit can execute effective sampling action. The first clock signal can be input from outside or provided by the transmitter in a unified way, and the acquisition modes are various. Preferably, the first clock signal is a clock of the parallel bus.

The second clock signal is a sampling clock of each delay sampling unit. Preferably, the second clock signal is an internal clock of the FPGA, and each delay sampling unit synchronously executes a sampling action by using the internal clock of the FPGA as a sampling signal. For example, a specific node such as a rising edge time and a falling edge time of each clock cycle may be set as the sampling node.

Specifically, at least one level change pulse is present in the calibration signal, and the duration of the level change pulse is at least one clock cycle of the first clock signal. In general, only one level change pulse in the calibration signal is needed to implement calibration, and other level change pulses may be set to verify the calibration effect.

Before the calibration is started, a sending end continuously sends signals with data of all 0 through n data channels of a parallel bus; after calibration is started, a sending end continuously sends signals with data of all 1 through n data channels of a parallel bus and at least continues for one clock cycle of a first clock signal; after continuously sending all 1 signals, the sending end continuously sends all 0 data signals through n data channels of the parallel bus until the calibration is finished. Finally, a high-level pulse signal from 0 to 1 to 0 is formed, as shown in the attached fig. 7 and 8 in the specification. After the calibration is completed, the sending end can transmit data through the parallel bus, and the data enters the FPGA, is subjected to time delay calibration by the time delay unit and then synchronously arrives at the interface sampling unit for sampling.

In fig. 8, DATA0 and DATA1 … … DATAn represent DATA transmitted by each DATA channel in the parallel bus. Description figure 8 is the result of a calibration of figure 4. According to the rising edge time of the high-level pulse signal acquired by each delay sampling unit, the phase difference between digital channels of the parallel bus and the phase difference between the first clock signal and the data sampling window of the parallel bus can be judged.

Particularly, the pulse width of the level change pulse of the calibration signal is greater than the clock period of the second clock signal, so that the situation that the trigger cannot acquire data when the level change pulse does not pass through any sampling node and the pulse width of the level change pulse is small and the sampling period occurs is avoided.

As shown in fig. 6, the delay sampling unit includes a flip-flop and a delay carry chain formed by a plurality of sub-chains connected in series in sequence, and an output end of each sub-chain is connected to one flip-flop; each sub-chain is responsible for executing a section of delay time; each trigger is responsible for sampling data after the sub-chain connected with the trigger and all the sub-chains before the sub-chain are delayed together to obtain sampling data.

Since the sub-chains are sequentially connected in series and have the sequence, the number of each trigger is numbered based on the sequence relationship of the sub-chains, and is 1, 2 and 3 … … n, so that the triggers are provided with the sequence, and the number of the triggers is convenient to calculate.

Preferably, each sub-chain can achieve the same time delay. Assuming that the delay time duration corresponding to each sub-chain is D, the channel data output by the first sub-chain is delayed by D, the channel data output by the second sub-chain is delayed by 2D, and the channel data output by the nth sub-chain is delayed by nD. Preferably, the delay time duration corresponding to each sub-chain is 31.25 picoseconds, and the maximum error of the scheme of the embodiment is 31.25 picoseconds.

A clock pulse (CLK) is introduced as control data, and the flip-flops are "triggered" to operate only when CLK arrives, and change output states according to input data. And taking the data output by the trigger as sampling data. When a sampling node arrives, the trigger circuit triggers, and when a signal is at a high level, the trigger outputs 1; when the signal is low, the flip-flop outputs 0. The first acquisition unit acquires input data cycle by taking a clock signal as control data, and finally obtains a series of sampling data consisting of 0 and 1. The sampling data are binary data sampled by the trigger, the delay sampling unit transmits the sampling data to the computing unit, and the computing unit processes the sampling data to compute channel sampling data of the channel.

The channel sampling data represents the sequence of the data sent by each channel reaching the delay sampling unit. Preferably, the channel sample data includes periodic data and delay data; the period data is a sampling period where the initial edge of the level change pulse is actually located; the delay data is the delay time of the start edge of the level change pulse relative to the sampling node of the sampling period in which it is actually located. And the channel sampling data with the minimum period data and delay data represents that the data sent by the channel reaches the delay unit fastest.

Therefore, the present embodiment introduces a delay sampling unit to finally find the actual starting time of the level variation of the calibration signal by delaying one sub-chain by one sub-chain, so as to determine the starting edge of the level variation pulse. Description figure 7 shows a schematic diagram of data collected by the time delay sampling unit. In fig. 7, two DATA channels of DATA0 and DATA1 are listed, DATA transmitted by DATA0 enters a delay sampling unit, and sequentially passes through the delay of n sub-chains, the DATA0 signal input is the situation that the signal transmitted by DATA0 is actually input to the delay sampling unit, and the signal gradually moves backwards after the delay of different sub-chains. In the same clock cycle, the data collected by two adjacent triggers are different, namely representing the edge time of the collected level change pulse.

Specifically, the channel sampling data acquisition process of each data channel includes: in the t +1 th sampling period, when the sampling data obtained by a certain trigger is inconsistent with the sampling data obtained by the previous trigger, namely the initial edge or the ending edge of the level change pulse is obtained, and the trigger is used as an edge trigger. In fig. 7, the delay carry chain n represents the nth sub-chain, the level change pulse is a high level pulse, the rising edge is the starting edge, and the falling edge is the ending edge. In the same sampling period, the output of the delay carry chain 2 is 1, the output of the delay carry chain 3 is 0, and the sampling data of two adjacent sub-chains in the same sampling period are different, which represents that an initial edge or a termination edge exists. Since the level change pulse is a high level pulse, the rising edge of the acquisition can be determined as the start edge.

Whether the acquired edge is the starting edge or not is judged based on the level change pulse, and in practical application, the starting edge and the ending edge can be comprehensively judged according to the sequence of level change in sampled data and the form of the level change pulse.

If the acquired initial edge is the t-th sampling period, determining that the initial edge is actually positioned in the t-th sampling period to acquire period data; integrating the delay time lengths of all triggers before the edge trigger and the corresponding sub-chains of all triggers, and calculating the delay time of the initial edge relative to the sampling node of the t-th sampling period to obtain delay data; the periodic data and the delay data constitute channel sample data of the channel. In fig. 7, assuming that the sampling period is T, the start edge of the signal transmitted by DATA0 is located in the first sampling period, and the delay time of the sampling node relative to the first sampling period is T- (T1 + T2), the delayed DATA is T- (T1 + T2). The beginning edge of the signal transmitted by DATA1 is located in the first sampling period, the delay time of the sampling node relative to the first sampling period is T- (T1 + T2+ T3+ T4), and the delayed DATA is T- (T1 + T2+ T3+ T4). It is apparent that DATA1 reaches the delay cells before DATA0 (t 3+ t 4).

After the sampling data is obtained, the computing unit needs to process the sampling data to obtain channel sampling data, process the sampling data of the design clock to obtain clock sampling data, and compute the time difference of data transmission through the parallel bus among all the data channels according to the channel sampling data.

Specifically, after channel sampling data is acquired, the channel sampling data with the longest delay time is selected, and a channel corresponding to the channel sampling data is a reference channel. The latest received channel sampling data represents that the time required for the corresponding channel to transmit the calibration signal through the parallel bus is longest, and at the moment, the data of each channel can be synchronously input into the interface sampling unit only by delaying and calibrating other channels.

Since the channel sampling data includes period data and delay data, the period data needs to be compared first, and then the delay data needs to be compared. The acquisition of the reference channel comprises: and comparing the size of the periodic data in the sampling data of each data channel, and screening out one or more data channel sampling data with the largest sampling period of the initial edge. If one data channel sampling data is screened out, directly taking a channel corresponding to the channel sampling data as a reference channel; if a plurality of data channel sampling data are screened out, further selecting the channel sampling data with the maximum delay data from the data channel sampling data, and taking the channel corresponding to the channel sampling data as a reference channel.

Calculating the difference between the time of transmitting the calibration signal to the delay unit by the other channels through the parallel bus and the time of transmitting the calibration signal to the delay unit by the reference channel through the parallel bus to obtain the time difference; based on the clock sampling data and the channel sampling data of the reference channel, the delay unit is calibrated so that the sampling node of each clock cycle in the first clock signal is located in the stable region of the parallel bus data sampling window.

In fig. 7, the signal transmitted by DATA0 and the signal transmitted by DATA1 occur in the same sampling period, the time difference between the two DATA channels is (t 3+ t 4), and the signal transmitted by DATA1 arrives at the delay unit before the signal transmitted by DATA0, so DATA1 needs to be delayed (t 3+ t 4) to realize that the signals transmitted by DATA0 and DATA1 are input to the interface sampling unit at the same time.

It should be noted that, the calibration method of this embodiment needs to calibrate the first clock signal and the delay duration of each channel, and may calibrate the first clock signal after the delay duration of each channel is calibrated, or calibrate the delay durations of the reference signal and the first clock signal. The sequencing of the calibration is not affected.

With respect to the relationship between the data sampling window and the sampling nodes of the first clock signal. Preferably, the data sampling window is divided into a first part, a second part and a third part in sequence, the stable region is located in the second part, and the first part and the third part are respectively not less than 20% of the data sampling window. Each sampling node of the first clock signal after delay calibration is located in a stable region and cannot be influenced by interference factors such as temperature and the like. Further preferably, since all channels have implemented synchronous input to the interface sampling unit, the data sampling windows of the parallel bus are also synchronous, and each sampling node may be set at the middle time of the data sampling window, as shown in fig. 8. The parallel bus shown in fig. 4 is calibrated by the calibration method of the present application, and the effect shown in fig. 8 can be obtained.

It should be noted that, the delay unit and the interface sampling unit are strictly calibrated, so that data calibrated by the delay unit can be synchronously input to the interface sampling unit. Preferably, after the delay unit is calibrated, a calibration signal can be sent to perform verification, and it is confirmed that the interface sampling unit can synchronously receive data sent by each channel, so as to further ensure the accuracy of calibration.

Data sent by each channel is synchronously input to the interface sampling unit through calibration of the delay unit, and the interface sampling unit samples according to the first clock signal after delay calibration, so that each sampling action is ensured to be in a data sampling window. The scheme of the embodiment can realize the calibration of the data sampling window at high speed, and the metastable state does not exist, and the result is shown in the attached figure 8 in the specification.

The embodiment provides a calibration method for a parallel bus data sampling window in an FPGA, which can quickly realize the calibration of the parallel bus data sampling window, and has the advantages of high calibration speed, high calibration precision and low calibration cost. By calibrating the time of the sampled clock signal and the data sent by the channels at the same time, the sampling nodes of the sampling clock are ensured to be always positioned in the stable area of the parallel bus data sampling window on the premise that the data sent by each channel is synchronously input into the interface sampling unit. The calibration can be realized by means of hardware resources inside the FPGA, and extra hardware cost is not needed.

Example 2

The embodiment 2 of the invention discloses a calibration device for a parallel bus data sampling window in an FPGA (field programmable gate array), which is used for realizing the calibration method of the embodiment 1. The calibration device is shown in the attached figure 6 of the specification, and the specific scheme is as follows:

a calibration device 2 for a data sampling window of a parallel bus in an FPGA (field programmable gate array) is characterized in that the calibration device 2 is configured in the FPGA1, and n data channels of the parallel bus transmit clock signals and channel signals to the FPGA 1;

the FPGA1 further includes a differential buffer 10, a delay unit 11, and an interface sampling unit 12, and the calibration apparatus 2 includes a calculation unit 14, a delay control unit 15, and at least n +1 delay sampling units 13.

A differential buffer 10 for performing differential processing on the first clock signal transmitted through the parallel bus and the channel data of each data channel;

the delay unit 11 is connected to the differential buffer 10, and is configured to perform delay calibration on the differentially processed first clock signal and the data transmitted by each data channel, respectively, so that the data transmitted by n data channels of the parallel bus can reach the interface sampling unit 12 at the same time after the delay calibration; after the first clock signal is subjected to delay calibration, all sampling nodes are always positioned in a stable area of a parallel bus data sampling window;

the interface sampling unit 12 is connected with the delay unit 11 and is used for sampling data transmitted by each data channel after delay calibration by using the first clock signal after delay calibration as a sampling clock, and a sampling node of the sampling clock is always positioned in a stable region of a parallel bus data sampling window;

the delay sampling unit 13 is configured to sample data transmitted by each data channel after the data is delayed for different time durations, so as to obtain sampled data of the channel; sampling data of the first clock signal after different delay time durations to obtain sampling data about a clock;

the calculating unit 14 is connected with the calculating unit 14 and each delay sampling unit 13, and is configured to obtain sampling data of the delay sampling unit 13, obtain clock sampling data and channel sampling data of each data channel, calculate a calibration parameter of the delay unit 11, and output the calibration parameter to the delay control unit 15;

and a delay control unit 15, configured to calibrate the delay unit 11 according to the calibration parameter output by the calculation unit 14.

The delay sampling unit 13 comprises a trigger and a delay carry chain formed by sequentially connecting a plurality of sub-chains in series, and the output end of each sub-chain is connected with one trigger; each sub-chain is responsible for executing a section of delay time; each trigger is responsible for sampling data after the sub-chain connected with the trigger and all the sub-chains before the sub-chain are delayed together.

The invention provides a method and a device for calibrating a parallel bus data sampling window in an FPGA (field programmable gate array), which can be used for quickly calibrating the parallel bus data sampling window, and have the advantages of high calibration speed, high calibration precision and low calibration cost. By calibrating the time of the sampled clock signal and the data sent by the channels simultaneously, on the premise that the data sent by each channel is synchronously input into the interface sampling unit, the sampling node of the sampling clock is ensured to be always positioned in the stable region of the parallel bus data sampling window, and the calibration can be realized by means of the hardware resources in the FPGA without extra hardware cost.

Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into multiple sub-modules. The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.

Claims

1. A calibration method for a parallel bus data sampling window in an FPGA is characterized by comprising the following steps:

analyzing the clock sampling data and the channel sampling data of the n data channels to obtain a first clock signal and a time difference, wherein the time difference is a difference value of time of a calibration signal transmitted by the n data channels reaching the delay unit;

2. The calibration method according to claim 1, wherein at least one level change pulse is present in the calibration signal, and wherein the duration of the level change pulse is at least one clock cycle of the first clock signal.

3. The calibration method according to claim 2, wherein the calibration signal is specifically:

4. The calibration method according to claim 2, wherein each delayed sampling unit performs synchronous sampling with a preset second clock signal as a sampling clock;

each sub-chain is responsible for executing a section of delay time;

5. The calibration method of claim 4, wherein the channel sample data comprises periodic data and delay data;

6. The calibration method according to claim 5, wherein the channel sampling data acquisition process of each data channel comprises:

numbering each trigger based on the sequential relationship of the child chains;

integrating the delay time lengths of all triggers before the edge trigger and the corresponding sub-chains of all triggers, and calculating the delay time of the initial edge relative to the sampling node of the t-th sampling period to obtain delay data;

7. The calibration method according to claim 5, wherein the size of the period data in the sampling data of each data channel is compared to screen out the sampling data of one or more data channels with the largest sampling period at which the start edge is actually located;

8. The calibration method according to claim 7, wherein a difference between a time when the channels except the reference channel transmit the calibration signal through the parallel bus to the delay unit and a time when the reference channel transmits the calibration signal through the parallel bus to the delay unit is calculated to obtain a time difference;

9. The calibration method according to claim 1, wherein the data sampling window is divided into a first portion, a second portion and a third portion in this order, the stable region is located in the second portion, and the first portion and the third portion are respectively not less than 20% of the data sampling window.

10. A calibration device for a parallel bus data sampling window in an FPGA, for implementing the calibration method of any one of claims 1 to 9; the calibration device is positioned on the FPGA;

the delay sampling unit is used for inputting a first clock signal transmitted by the parallel bus and channel data transmitted by n data channels into the delay carry chain, and sampling data of the first clock signal and the channel data after delay of each sub-chain of the delay carry chain to obtain sampling data related to a clock and sampling data related to each channel;