CN114826281A - Double-layer scheduling decoder and method based on 5G LDPC (Low Density parity check) and intelligent terminal - Google Patents

Abstract

The invention belongs to the technical field of decoders, and discloses a 5G LDPC-based double-layer scheduling decoder, a method and an intelligent terminal. The 5G LDPC-based double-layer scheduling decoder includes: an LLR memory, a control unit, and a shift network , a calculation unit and a check node storage unit; a control unit, used to control the input sequence of the two-layer variable nodes input from the LLR memory to the calculation unit and the output sequence of the updated variable nodes written to the LLR memory, and at the same time from the check The node storage unit reads the relevant check nodes; the shift network is used to shift the two-layer variable nodes; the calculation unit is used to update the variable nodes. The invention utilizes the characteristics of dividing the 5G basic matrix into orthogonal matrices and non-orthogonal matrices, rearranges the input and output order of variable nodes in each layer, and reduces the delay caused by conflicting variable nodes on the premise of ensuring performance. At the same time, the dual-layer scheduling of the decoder is realized, thereby improving the throughput of the decoder and meeting the requirements of 5G high-speed communication.

Description

A 5G LDPC-based dual-layer scheduling decoder, method and intelligent terminal

technical field

The invention belongs to the technical field of decoders, and in particular relates to a 5G LDPC-based dual-layer scheduling decoder, a method and an intelligent terminal.

Background technique

At present, the fifth generation mobile communication (5G) is divided into three application scenarios: Enhanced Mobile Bandwidth (eMBB), Low Latency and High Reliability (URLLC), and Massive Internet of Things (mMTC). Data services are characterized by high speed, and the delay can be between 50 and 100 ms; the delay of interactive services is between 5 and 10 ms; augmented reality and online games require high-definition video and a delay of tens of milliseconds.

Low Density Check Code (LDPC) was first proposed by Robert Gallager in his doctoral dissertation in 1963. The classic LDPC has excellent performance and low decoding complexity in long code blocks, and has repeatedly refreshed the approximation record of the Shannon world. After years of research, LDPC has made great breakthroughs in short code design, supporting flexible code length and code rate, code rate compatibility, and adaptive retransmission. At the same time, the optimization of LDPC decoding algorithm has been in progress. Finally, with its excellent performance, LDPC finally entered the demanding 5G-NR standard in October 2016 (as a coding scheme for eMBB data channels).

5G LDPC is a quasi-cyclic LDPC code. The basic check matrix is divided into BG1 and BG2. It supports 51 boost values, the minimum is 2 and the maximum is 384.

The decoding algorithm of LDPC is a belief propagation (BP) algorithm, which in principle represents the information exchange between the variable node and the check node, and performs multiple iterations to obtain the decoding result. The scheduling methods between nodes are divided into flooding and layered. The characteristic of flooding is that in each decoding iteration, all the soft information from the variable node to the check node is calculated first, and then the soft information from the check node to the variable node is calculated, which is mostly used for computer simulation. The layered feature is that when calculating the soft information of each layer, the relevant node information in this iteration will be updated for the soft information calculation of the next layer, which is suitable for hardware implementation.

The architecture of LDPC decoder is mainly divided into full parallel structure, row parallel structure and block parallel structure. The row-parallel structure and the block-parallel structure adopt the hierarchical decoding scheduling method. The parallelism of the row parallel structure is affected by the number of rows of the basic parity check matrix, with a maximum of 46, and the parallelism of the block parallel structure is affected by the boost value of the 5G LDPC code, with a maximum of 384. At present, most 5G LDPC decoders adopt a hierarchically scheduled row-parallel or block-parallel structure.

In the design of traditional layered LDPC decoders, in order to avoid variable node conflicts between layers, they can only decode in sequence and single-layer decoding. In the case of high code rates, LDPC codes have good throughput. However, for low bit rates, the throughput is often low and cannot meet the basic requirements of 5G communication.

Through the above analysis, the existing problems and defects of the prior art are: the traditional layered 5G LDPC decoder decodes as single-layer scheduling, and the throughput rate is low in the case of low code, which cannot meet the basic requirements of 5G communication.

SUMMARY OF THE INVENTION

Aiming at the problems existing in the prior art, the present invention provides a 5G LDPC-based dual-layer scheduling decoder, method and intelligent terminal. The variable node index of each layer of BG1 and BG2 is a fixed value, that is, the two matrices of BG1 and BG2 are fixed, and the index value of each layer is actually the non-zero element position of each row of the matrix. Since the matrix is fixed, the orthogonal and non-orthogonal regions of BG1 and BG2 are fixed. The size of the basic matrix of BG1 is 46 × 68, and the size of the basic matrix of BG2 is 42 × 52. The orthogonal region of BG1 is from row 21 to row 46. , the orthogonal region is 1 to 20 lines. The orthogonal region of BG2 is 21 to 42 lines, and the non-orthogonal region is 1 to 20 lines. The input and output sequence of nodes is an effective solution designed in this paper to solve the high delay caused by multiple conflicting variable nodes in double-layer scheduling.

The present invention is implemented in this way, a 5G LDPC-based dual-layer scheduling decoder, and the 5G LDPC-based dual-layer scheduling decoder includes:

LLR memory, global control unit, precomputing layer control unit, waiting layer control unit, two sets of shift networks, 768 calculation units and check node storage units;

The global control unit controls the current decoding group and the number of decoding iterations;

The first-level control unit and the waiting-level control unit are used to control the input sequence of the two-layer variable nodes input from the LLR memory to the calculation unit, and the output sequence of the updated variable nodes from the calculation unit written to the LLR memory. The check node storage unit reads the relevant check node;

Two sets of shift networks are used for the shift of two-layer variable nodes;

The computing unit is used for two-layer variable nodes to interact with the corresponding check nodes and obtain the updated variable nodes.

Further, the two-layer variable node includes: a first-layer variable node and a waiting-layer variable node; the first-layer variable node is an odd-layer variable node; the waiting-layer variable node is an even-layer variable node.

Another object of the present invention is to provide a dual-layer scheduling method applied to the 5G LDPC-based dual-layer scheduling decoder, where the 5G LDPC-based dual-layer scheduling decoder includes:

The control unit reads the two-layer variable nodes from the LLR memory and enters the calculation unit through the shift network respectively, interacts with the corresponding check nodes, and obtains the updated variable nodes.

Further, the 5G LDPC-based dual-layer scheduling method for a decoder and decoder includes the following steps:

Step 1: Divide each layer of the basic check matrix of 5G into odd-numbered layers and even-numbered layers, decode each adjacent odd-numbered layer and even-numbered layer at the same time, and divide adjacent odd-numbered layers and even-numbered layers into one group;

In step 2, the first layer computing unit inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes. For non-orthogonal groups, the first layer and the waiting layer are not calculated at the same time due to the existence of conflicting variable nodes. Conflicting variable nodes first enter the calculation unit of the first calculation layer for calculation, and the waiting layer first inputs the non-conflicting variable nodes. After the calculation of the first calculation layer is completed, the updated variable nodes are output, and the waiting layer calculation unit continues to input the conflicting variable nodes. ; For orthogonal groups, there are no conflicting variable nodes in the first layer and the waiting layer, and they are calculated simultaneously;

Step 3: Waiting for the end of the layer calculation and starting to output the updated variable node, the decoding control unit controls the first calculation layer and the waiting layer calculation unit to input the next group of respective variable nodes, and starts the calculation of the next group;

Step 4: After the calculation of all groups is completed, the number of decoding iterations is incremented by 1. If the maximum number of decoding iterations is reached, the decoder ends the calculation and outputs the decoding result; otherwise, steps 2 and 3 are repeated.

Further, each layer of computation of the dual-layer scheduling decoder of the 5G LDPC adopts a block parallel structure.

Further, the grouping of adjacent odd-numbered layers and even-numbered layers into one group includes: the two layers of each group are divided into a pre-calculated layer and a waiting layer; the odd-numbered layer is a pre-calculated layer; the even-numbered layer is a waiting layer .

Further, the second step further includes: rearranging the input and output order of the variable nodes of each layer during the decoding and scheduling.

Further, the rearranging the input and output order of the variable nodes of each layer includes:

In the non-orthogonal group waiting layer, the conflicting variable nodes are input at the end, and the waiting-precompute layer updates the result of conflicting variable nodes.

Further, the rearranging the input and output sequence of the variable nodes of each layer further includes: each layer of the current group first outputs the variable nodes that conflict with the next group.

The input order of the first-computation layer of all groups is adjusted so that the variable nodes that do not conflict with the previous group are input first, and then other variable nodes are input.

The input sequence of the waiting layer of the non-orthogonal group is adjusted as: first input the variable nodes that do not conflict with the first calculation layer of this group, then input the conflict variable nodes between the groups that conflict with the previous group, and wait for the first calculation layer to update the conflict variable nodes. Finally, enter the intragroup conflict variable node.

The input order of the waiting layer of the orthogonal group is adjusted to first input the variable nodes that have no conflict with the previous group, and then input other variable nodes, without waiting in the middle.

The output order of the precomputed layer of the non-orthogonal group is adjusted to output the conflict variable nodes in the group that conflict with the waiting layer of this group first, and then output other variable nodes.

The output order of the precomputed layer of the orthogonal group is adjusted to output the conflicting variable nodes between groups that conflict with the next group first, and then output other variable nodes.

The output order of the waiting layer of all groups is adjusted to output the conflict variable nodes between groups that conflict with the next group first, and then output other variable nodes.

Another object of the present invention is to provide an information data processing terminal configured to execute the 5G LDPC-based dual-layer scheduling method for a decoder.

In combination with the above-mentioned technical solutions and the technical problems solved, please analyze the advantages and positive effects of the technical solutions to be protected by the present invention from the following aspects:

First, in view of the technical problems existing in the above-mentioned prior art and the difficulty of solving the problems, closely combine the technical solutions to be protected of the present invention and the results and data in the research and development process, etc., and analyze in detail and profoundly how to solve the technical solutions of the present invention. Technical problems, some creative technical effects brought about by solving problems. The specific description is as follows:

The invention utilizes the double-layer scheduling of the rearranged decoder, which can greatly reduce the input and output delay of the intermediate variable node, and also has a higher throughput rate in the case of a low code rate.

The present invention proposes a 5G LDPC decoder with a block parallel structure of double-layer scheduling. According to the basic parity check matrix of 5G, every two layers are divided into a group, and each group includes a pre-calculation layer and a waiting layer. Layers are pre-calculated layers, and even-numbered layers are waiting layers. During decoding and scheduling, the input and output order of variable nodes in each layer will be rearranged. The input order that affects the variable nodes at each level comes from conflicting variable nodes between and within groups. In the waiting layer, the conflicting variable nodes are input at the end, and wait for the result of updating the conflicting variable nodes in the first layer. Conflicting variable nodes between groups will affect the update order of variable nodes in each layer. The current group will first output the variable nodes that conflict with the next group, thereby reducing the wait for the next group. The double-layer scheduling of the decoder after the rearrangement can greatly reduce the input and output delay of the intermediate variable node, and also has a high throughput rate in the case of low code rate.

Second, considering the technical solution as a whole or from the product point of view, the technical effects and advantages of the technical solution to be protected by the present invention are specifically described as follows:

The invention utilizes the characteristics of dividing the 5G basic matrix into orthogonal matrices and non-orthogonal matrices, rearranging the input and output order of variable nodes in each layer, and on the premise of ensuring performance, reducing conflicting variable nodes brought about by It realizes the double-layer scheduling of the decoder, thereby improving the throughput rate of the decoder and meeting the requirements of 5G high-speed communication.

Third, as an auxiliary evidence of inventive step for the claims of the present invention, it is also reflected in the following important aspects:

(1) The technical solution of the present invention fills the technical gap in the industry at home and abroad: the present invention fills the problem that the 5G LDPC decoder is difficult to implement in double-layer scheduling and has little meaning. By rearranging the input and output order of the variable nodes of each layer, the decoder avoids the large delay caused by conflicting variable nodes during calculation, and at the same time ensures the performance of the decoder. The data input and output of the calculation are more pipelined and have higher throughput.

(2) Whether the technical solution of the present invention solves the technical problem that people have been eager to solve, but has not been successful: the present invention solves the problem of low throughput of the 5G LDPC decoder under low code rate, and at the lowest code rate When the rate is 1/3 the code rate, the throughput rate can reach 9.6f, and f is the operating frequency, that is, when the frequency is 1Gbps, the decoder throughput rate is 9.6Gbps, and under the single-layer scheduling condition, the 1/3 code rate The decoder throughput rate is only 2.4f.

(3) Whether the technical solution of the present invention overcomes technical prejudice: the present invention overcomes the existence of conflicting variable nodes. Compared with the single-layer scheduling scheme, the resources of the double-layer scheduling scheme are doubled, but the throughput cannot reach the single-layer scheduling throughput. In the case of low bit rate, the throughput of double-layer scheduling designed by the present invention can reach more than three times that of single-layer scheduling.

Description of drawings

FIG. 1 is a schematic diagram of a 5G LDPC-based dual-layer scheduling decoder provided by an embodiment of the present invention.

FIG. 2 is a flowchart of a dual-layer scheduling method for a 5G LDPC-based dual-layer scheduling decoder provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of a conflicting variable node provided by an embodiment of the present invention.

FIG. 4 is a timing diagram of the eighth group and the ninth group provided by an embodiment of the present invention.

FIG. 5 is a schematic diagram of the input-output relationship of the eighteenth group and the nineteenth group provided by an embodiment of the present invention.

FIG. 6 is a graph showing the floating-point simulation performance of the LDPC code and the fixed-point hardware simulation performance of double-layer scheduling provided by the embodiment of the present invention.

FIG. 7 is a schematic diagram of a basic matrix structure of a 5G LDPC provided by an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

1. Explain the embodiment. In order for those skilled in the art to fully understand how the present invention is specifically implemented, this part is an explanatory embodiment for explaining the technical solutions of the claims.

As shown in FIG. 1 , the 5G LDPC-based dual-layer scheduling decoder provided by the embodiment of the present invention includes:

LLR memory, global control control unit, precomputing layer control unit, waiting layer control unit, two groups of shift networks, 768 calculation units and check node storage units;

The global control unit controls the current decoding group and the number of decoding iterations;

The first-level control unit and the waiting-level control unit are used to control the input sequence of the two-layer variable nodes input from the LLR memory to the calculation unit, and the output sequence of the updated variable nodes from the calculation unit written to the LLR memory. The check node storage unit reads the relevant check node;

Two sets of shift networks are used for the shift of two-layer variable nodes;

The computing unit is used to interact the two-layer variable node with the corresponding check node and obtain the updated variable node.

The two-layer variable node provided by the embodiment of the present invention includes: a first-layer variable node and a waiting-layer variable node; the first-layer variable node is an odd-layer variable node; and the waiting-layer variable node is an even-layer variable node.

The dual-layer scheduling method for a 5G LDPC-based dual-layer scheduling decoder provided by the embodiment of the present invention includes:

The control unit reads the two-layer variable nodes from the LLR memory and enters the calculation unit through the shift network respectively, interacts with the corresponding check nodes, and obtains the updated variable nodes.

As shown in FIG. 2 , a 5G LDPC-based dual-layer scheduling method for a decoder provided by an embodiment of the present invention includes the following steps:

Divide each layer of the 5G basic check matrix into odd and even layers, decode each adjacent odd and even layers at the same time, and group adjacent odd and even layers into one group;

The first-layer computing unit inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes. The waiting layer of the non-orthogonal group first inputs the non-conflicting variable nodes and waits. After the calculation of the first layer computing unit is completed, it starts to output the updated variable nodes, and the waiting layer computing unit continues to input the remaining conflicting variable nodes and starts the calculation. The waiting layer and the precomputing layer and the waiting layer of the orthogonal group are calculated at the same time, and there is no need to input waiting in the middle.

Each layer of computation of the 5G LDPC dual-layer scheduling decoder provided by the embodiment of the present invention adopts a block parallel structure.

The method of dividing adjacent odd-numbered layers and even-numbered layers into a group provided by the embodiment of the present invention includes: the two layers of each group are divided into a first-calculated layer and a waiting layer; the odd-numbered layer is a first-calculated layer; the even-numbered layer is a waiting layer Floor.

The step S102 provided by the embodiment of the present invention further includes: during the decoding and scheduling, rearranging the input and output order of the variable nodes of each layer.

The rearrangement of the input and output order of the variable nodes of each layer provided by the embodiment of the present invention includes:

The input order of the first-computation layer of all groups is adjusted so that the variable nodes that do not conflict with the previous group are input first, and then other variable nodes are input.

The input order of the waiting layer of the non-orthogonal group is adjusted to first input the variable nodes that do not conflict with the first calculation layer of this group, and then input the conflict variable nodes between the groups that conflict with the previous group, and wait for the first calculation layer to update the conflict variable nodes. , and finally enter the intragroup conflict variable node.

The input sequence of the waiting layer of the orthogonal group is adjusted so that the variable nodes that do not conflict with the previous group are input first, and then the other variable nodes are input, and there is no need to wait in the middle.

The output order of the precomputed layer of the non-orthogonal group is adjusted to output the conflict variable nodes in the group that conflict with the waiting layer of this group first, and then output other variable nodes.

The output order of the precomputed layer of the orthogonal group is adjusted to output the conflicting variable nodes between groups that conflict with the next group first, and then output other variable nodes.

The output order of the waiting layer of all groups is adjusted to output the conflict variable nodes between groups that conflict with the next group first, and then output other variable nodes.

The rearrangement of the input and output sequence of the variable nodes of each layer provided by the embodiment of the present invention further includes: the current group first outputs the variable nodes that conflict with the next group.

The technical solutions of the present invention will be further described below with reference to specific embodiments.

1. System model

The structure of the LPDC double-layer decoder is shown in Figure 1. The control unit reads the two-layer variable nodes from the LLR memory and enters the calculation unit through two shift networks respectively, interacts with the corresponding check nodes, and finally obtains the updated variables. node.

Divide each layer of the basic matrix into odd-numbered layers and even-numbered layers, decode each adjacent odd-numbered and even-numbered layers at the same time, and group adjacent odd-numbered and even-numbered layers into one group, such as the first layer and The second layer can be decoded at the same time, the third layer and the fourth layer of the second group can be decoded at the same time, and the calculation of each layer adopts a block parallel structure, and the maximum parallelism is 384. At the same time, the two layers of each group are divided into the first layer and the waiting layer for distinguishing.

The idea of double-layer scheduling is that the first-computation layer and the waiting layer input their respective variable nodes at the same time. When encountering conflicting variable nodes, as shown in Figure 2, the conflicting variable nodes first enter the first-computation layer to update, the waiting layer stops input, and waits for After the calculation of the first layer is completed, the updated conflicting variable nodes continue to be input into the waiting layer to update the variable nodes. Table 1 and Table 2 are the variable node indexes of each layer of BG1 and BG2, and Table 3 and Table 4 are the conflicting variable nodes between adjacent layers of BG1 and BG2. Among them, groups 1 to 10 in BG1 are non-orthogonal groups, groups 11 to 23 are orthogonal groups, groups 1 to 10 in BG2 are non-orthogonal groups, and groups 11 to 21 are orthogonal groups. Observing Tables 3 and 4, it can be seen that in the double-layer calculation, under the normal input sequence, the groups in the non-orthogonal region (group 1 to group 10) will bring a large amount of input and output delay due to the influence of conflict variable nodes, and the table It can be seen from Table 5 and Table 6 that there are also a large number of conflicting variable nodes between groups. Under normal output sequence, each group will bring a large amount of input and output delay due to the influence of conflicting variable nodes between groups. Therefore, during design, the input and output order of variable nodes in each group will be rearranged, and there will be different arrangement strategies for groups in orthogonal regions and groups in non-orthogonal regions.

It is observed that only the 5th layer and the 6th layer of BG1 have a large difference in row weight, where the row weight of the 5th layer is 3, the row weight of the 6th layer is 8, and the first two variable nodes of the 5th layer are For conflict variable nodes, if the sixth layer is considered to be the first layer, the fifth layer needs to wait a lot of time to get the updated conflict variable nodes of the sixth layer. If the fifth layer is used as the first calculation layer and the sixth layer is used as the waiting layer, when the fifth layer outputs the updated conflict variable node, due to the large row weight of the sixth layer, only a small amount of waiting clock consumption will be generated. The most efficient use of time.

The line weight difference between adjacent layers in other groups is not large, and the extra clock consumption of the odd-numbered or even-numbered layers as the first-calculated layer is not very different. Therefore, considering the situation of all groups, all odd-numbered layers in BG1 and BG2 As the first layer, all even-numbered layers are used as waiting layers,

Table 1 Variable node index and row weight value of each layer of BG1

Table 2 Variable node index value and row weight value of each layer of BG2

Table 3 Conflict variable nodes between adjacent layers of BG1

Table 4 Conflict variable nodes between adjacent layers of BG2

Table 5. Variable Nodes Conflicting Between BG1 Groups

Table 6 Variable nodes of conflict between BG2 groups

2. Input and output order of non-orthogonal group variable nodes

The following takes the 8th group and the 9th group in BG1 as examples to describe the input and output sequence arrangement strategy of each layer variable node of the non-orthogonal group. The original index order of the variable nodes of each layer in the 8th and 9th groups is as follows,

Group 8:

15 floors: 1, 3, 16, 17, 18, 22, 37

16 floors: 1, 2, 11, 14, 19, 26, 38

Group 9:

17 floors: 2, 4, 12, 21, 23, 39

18 floors: 1, 15, 17, 18, 22, 40

For the order of input and output within the group, it is observed that only the 15th and 16th layers of the 8th group have variable node conflicts with an index value of 1, and the 9th group does not. Therefore, the input order of the variable nodes of the 15th and 16th layers is firstly reset. arranged as follows

15 floors: 1, 3, 16, 17, 18, 22, 37

16 floors: 2, 11, 14, 19, 26, 38, 1

The rearrangement strategy is to put the conflicting nodes in the 16th layer on the last input, so there is no conflict in the first 6 clock inputs of the 8th double-layer calculation. When the 7th clock, only the 15th layer input index value For the variable node value of 37, 16 layers wait. When the calculation of the 15th layer is completed and the updated variable node is output, it follows the rule of outputting the variable node that conflicts with the waiting layer first. Therefore, when outputting, the variable node with an index value of 1 will be output first, and this variable node is sending When entering the variable node storage module, it will also be sent to the waiting layer computing unit to start the 16-layer variable node calculation. This input method can ensure that the delay caused by the input can be reduced without affecting the calculation result.

For the between-group input-output order, the conflicting variable nodes for groups 8 and 9 were observed to be 1, 2, 17, 18, 22. Considering that when the decoder is calculating, the input and output of the variable nodes of each layer have to go through a shifter respectively, each shifter consumes 2 clocks, and the calculation waiting in the middle of the variable nodes of each layer is 3 clocks, that is, waiting The updated variable node result of the layer needs to wait (the number of conflicting variable nodes + 6) clocks more than the normal situation. At the same time, because the non-orthogonal group precomputing layer can get the updated variable node result faster than the waiting layer, so As long as the current group (the number of conflicting variable nodes in the group + 6) is greater than the row weight value of the precomputed layer of this group, it can satisfy the requirement that the precomputed layer computing unit has already calculated the current value when the layer computing unit outputs the updated variable nodes. All the variable nodes after the layer update are output, so in the design, it is only necessary to count the conflicting variable nodes between the waiting layer of the current group and the next group of precomputed layers and waiting layers. As can be seen from Tables 1 to 4, the non-orthogonal groups (group 1 to group 10) in BG1 and BG2 all satisfy this condition. The conflict variable nodes between the waiting layer and the next group in the eighth group are 1 and 2. In order to ensure the highest system throughput and the highest working efficiency of the computing unit, that is, when the computing unit completes the calculation of the current group, it starts to receive the variable nodes of the next group at the same time. . Therefore, the eighth group of waiting layers will first update variable nodes 1 and 2 and then update other variable nodes. The ninth group will first input variable nodes that do not conflict with the eighth group, and finally input variable nodes 1 and 2, thus satisfying the eighth While the group is waiting for the layer to output the updated variable node, it can start to input the variable node of the ninth group, and there is no conflict, that is, the variable node input of the ninth group is the updated variable node. Finally, the variable node input order for groups 8 and 9

15 floors: 1, 3, 16, 17, 18, 22, 37

16 floors: 2, 11, 14, 19, 26, 38, 1

17 floors: 4, 12, 21, 23, 29, 2

18 floors: 15, 17, 18, 22, 40, 1

Variable node output order for groups 8 and 9

15 floors: 1, 3, 16, 17, 18, 22, 37

16 floors: 1, 2, 11, 14, 19, 26, 38

17 floors: 2, 4, 12, 21, 23, 29

18 floors: 1, 15, 17, 18, 22, 40

From this, the input and output order of variable nodes of non-orthogonal groups in BG1 and BG2 can be deduced

Table 7 BG1 rearrangement of non-orthogonal group variable node input and output order

Table 8 Input and output order of non-orthogonal group variable nodes after BG2 rearrangement

3 Orthogonal group variable node input and output order

Take the 18 groups and 19 groups in BG1 as examples to explain the input-output relationship of the quadrature groups. Since there are no conflicting variable nodes in the orthogonal group, the waiting layer and the precomputing layer are calculated at the same time, and there is no additional clock delay. When considering the input-output waiting relationship between groups, it is necessary to consider the conflict relationship between the precomputing layer and the waiting layer of the current group and the next group at the same time. The variable node indices for groups 18 and 19 are as follows, group 18

35 floors: 1, 8, 16, 18, 57

36 floors: 2, 7, 13, 23, 58

Group 19:

37 floors: 1, 15, 16, 19, 59

38 floors: 2, 14, 26, 60

Among them, the variable nodes 1 and 16 in the first calculation layer of the 18 groups conflict with the first calculation layer of the next group, and the variable node 2 of the waiting layer conflicts with the waiting layer of the next group. At the same time, due to the variable node 1 of the first calculation layer The variable node 2 of the waiting layer can be updated at the same time. In order to reduce the clock consumption, each group will input the variable node that conflicts with the previous group at the end when inputting, and will give priority to outputting the conflicting variable node with the next group when outputting. variable node, so the rearranged 18 and 19 groups of output variable node input and output order are as follows,

18 groups of 35 layers,

Input order: 1, 8, 16, 18, 57, Output order: 1, 16, 8, 18, 57

18 groups of 36 layers

Input order: 2, 7, 13, 23, 58, Output order: 2, 7, 13, 23, 58

19 groups of 37 layers

Input order: 15, 19, 59, 1, 16, Output order: 1, 15, 16, 19, 59

19 groups of 38 layers

Input order: 14, 24, 60, 2, Output order: 2, 14, 24, 60

The specific timing relationship between the 18th group and the 19th group is shown in Figure 3.

From this, the input and output order of the variable nodes of each layer of the group of the orthogonal regions after the rearrangement of BG1 and BG2 in Table 9 and Table 10 can be obtained. After the rearrangement, there is no need to wait for an additional clock between the groups in the orthogonal region. As long as the current group gets the calculation result, the variable nodes of the next group can be input, so that the variable nodes of the current group are output and the variable nodes of the next group are input. At the same time, it is more in line with the pipeline design of the hardware, thereby improving the throughput rate of the decoder.

Table 9 Input and output order of group variable nodes in BG1 rearranged orthogonal region

Table 10 Input and output order of group variable nodes in BG2 rearranged orthogonal region

2. Application examples. In order to prove the creativity and technical value of the technical solution of the present invention, this part is an application example of the technical solution in the claims on specific products or related technologies.

The present invention provides an information data processing terminal, which is used for executing the 5G LDPC-based double-layer scheduling method for a decoder.

The present invention provides a 5G LDPC-based double-layer scheduling decoder implementing the 5G LDPC-based double-layer scheduling method, and can be applied to 5G high-rate communication.

The present invention provides a 5G LDPC decoder compatible with multiple code rates, compatible with multiple code rates such as 1/3, 1/2, 2/3, 3/4, 5/6, 8/9, etc. Flexible switching.

The present invention provides a 5G LDPC decoder supporting multiple code lengths, the shortest code length supported is 40, and the longest code length is 25344.

The present invention provides a 5G LDPC decoder that supports all matrices of BG1 and BG2 at the same time, and supports all boost value sizes, with the minimum boost value being 2 and the maximum being 384.

The present invention provides a double-layer scheduling scheme based on 5G LDPC decoding, which effectively reduces the probability of collision of variable nodes of double-layer decoding on the premise of ensuring performance.

The present invention provides a system structure of a 5G LDPC-based double-layer scheduling decoder, which can realize double-layer decoding without occupying too much storage resources.

The present invention provides a decoder pipeline scheme based on 5G LDPC, namely changing the order of input and output variable nodes, so that node input, calculation and output are pipelined, intermediate delay is reduced, and the throughput rate of the decoder is further improved.

The present invention provides a double-layer scheduling decoding scheme based on LDPC, which is suitable for all LDPC codes including 5G LDPC.

The present invention provides a sustainable 5G LDPC decoder, which is not only applicable to the basic matrices BG1 and BG2 in the current 5G standard, but also applicable to the future BG3 and BG4.

3. Evidence of the relevant effects of the embodiment. The embodiments of the present invention have achieved some positive effects in the process of research and development or use, and indeed have great advantages compared with the prior art.

1. Decoder performance analysis

1.1 Throughput

The formula for calculating the throughput rate is as follows

Among them, N _LDPC represents the length of the encoded LDPC code, cycle represents the number of clocks required for each iteration, n _iter represents the number of iterations, and f represents the clock frequency.

Under the same conditions, the throughput performance comparison between the double-layer scheduling LDPC decoder designed by the present invention and the single-layer scheduling LDPC decoder is as follows.

Table 11 8/9 bit rate throughput comparison

Performance Traditional single-tier scheduling this invention code length 9000 9000 code rate 8/9 8/9 working frequency 200MHZ 200MHZ number of iterations 8 8 Throughput 2.44Gbps 4.89Gbps

Table 12 1/3 bit rate throughput comparison

Performance Traditional single-tier scheduling this invention code length 25344 25344 code rate 1/3 1/3 working frequency 200MHZ 200MHZ number of iterations 8 8 Throughput 480Mbps 1.92Gps

It can be seen from the table that the throughput rate of the double-layer scheduling LDPC decoder designed by the present invention is significantly improved compared with the single-layer scheduling decoder, especially at low code rate, no matter at high code rate or low code rate. It is especially obvious that the throughput rate of the double-layer scheduling decoder designed by the present invention is more than 3 times that of the single-layer scheduling decoder under the 1/3 code rate. At the same time, the dual-layer scheduling decoder designed by the present invention is compatible with multiple code rates, can be manually switched between 1/3 and 8/9 code rates, and supports all 51 boost values under the basic matrix BG1 and the basic matrix BG2 at the same time. The minimum value is 2 and the maximum value is 384, so the dual-layer scheduling decoder designed by the present invention has good generality and configurability.

1.2 Resource occupation

The resource occupancy of the decoder is as follows

Table 13 Resource occupancy of dual-layer scheduling decoder

resource single layer scheduling decoding this invention LUTs 136640 273280 LUTRAM 1560 4149 FF 46608 73748 BRAM 177 201 DSP 1 2 IO 2 2 BUFG 5 8 PLL 1 1

Since the double-layer scheduling decoder designed by the present invention needs to read the variable nodes of the double-layer and calculate at the same time, it will consume more BRAM resources and LUT resources in terms of resource occupation. Addresses are allocated reasonably, so the total resources are not multiplied.

1.3 Simulation results

The following is a comparison between the floating-point simulation performance of LDPC codes and the fixed-point hardware simulation performance of double-layer scheduling. It can be observed that the LDPC decoder designed under the present invention hardly loses the performance of LDPC codes under double-layer scheduling.

It can be seen from the simulation results and throughput rate results that under the premise of ensuring performance, the decoder of the present invention can have higher throughput rates for LDPC codes with high and low code rates, and meet the basic requirements of 5G communication.

It should be noted that the embodiments of the present invention may be implemented by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using special purpose logic; the software portion may be stored in memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those of ordinary skill in the art will appreciate that the apparatus and methods described above may be implemented using computer-executable instructions and/or embodied in processor control code, for example on a carrier medium such as a disk, CD or DVD-ROM, such as a read-only memory Such code is provided on a programmable memory (firmware) or a data carrier such as an optical or electronic signal carrier. The device of the present invention and its modules can be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., It can also be implemented by software executed by various types of processors, or by a combination of the above-mentioned hardware circuits and software, such as firmware.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art is within the technical scope disclosed by the present invention, and all within the spirit and principle of the present invention Any modifications, equivalent replacements and improvements made within the scope of the present invention should be included within the protection scope of the present invention.

Claims (10)

1. a double-layer scheduling decoder based on 5G LDPC, is characterized in that, the described double-layer scheduling decoder based on 5G LDPC comprises: LLR memory, global control unit, precomputing layer control unit, waiting layer control unit, two groups of shift networks, 768 calculation units and check node storage units; The global control unit controls the current decoding group and the number of decoding iterations; The precomputing layer control unit and the waiting layer control unit are used to control the input sequence of the two-layer variable nodes input from the LLR memory to the calculation unit and the output sequence of the updated variable nodes written to the LLR memory, and store the data from the check node at the same time. The unit reads the relevant check node; Two sets of shift networks are used for the shift of two-layer variable nodes; The calculation unit is used for the interaction between the two-layer variable node and the corresponding checksum to obtain the updated variable node. 2. The double-layer scheduling decoder based on 5G LDPC as claimed in claim 1, wherein the two-layer variable node comprises: a first-layer variable node and a waiting-layer variable node; the first-layer variable node is odd-numbered layer variable nodes; the waiting layer variable nodes are even-numbered layer variable nodes. 3. A 5GLDPC-based double-layer scheduling decoder double-layer scheduling method applied to the 5G LDPC-based double-layer scheduling decoder according to any one of claims 1-2, it is characterized in that, described based on 5GLDPC The double-layer scheduling method of the double-layer scheduling decoder includes: The control unit reads the two-layer variable nodes from the LLR memory and enters the calculation unit through the shift network respectively, interacts with the corresponding check nodes, and obtains the updated variable nodes. 4. The 5G LDPC-based double-layer scheduling decoder double-layer scheduling method according to claim 3, wherein the 5G LDPC-based double-layer scheduling decoder double-layer scheduling method comprises the following steps: Step 1: Divide each layer of the basic check matrix of 5G into odd-numbered layers and even-numbered layers, decode each adjacent odd-numbered layer and even-numbered layer at the same time, and divide adjacent odd-numbered layers and even-numbered layers into one group; In step 2, the first layer computing unit inputs the variable nodes required for the calculation of this layer, and immediately calculates and outputs the updated variable nodes. For non-orthogonal groups, the first layer and the waiting layer are not calculated at the same time due to the existence of conflicting variable nodes. The conflicting variable nodes first enter the calculation unit of the first calculation layer for calculation, the waiting layer first inputs the non-conflicting variable nodes, and after the calculation of the first calculation layer is completed, the updated variable nodes are output, and the waiting layer calculation unit continues to input the conflicting variable nodes. Calculation; for the orthogonal group, there are no conflicting variable nodes in the first calculation layer and the waiting layer, and the calculation is performed at the same time; Step 3: After the calculation of the waiting layer is completed, when the output and update conflicting variable nodes and other variable nodes are started, the decoding control unit controls the first calculation layer and the waiting layer to input the next group of respective variable nodes, and starts the calculation of the next group; Step 4: After the calculation of all groups is completed, the number of decoding iterations is incremented by 1. If the maximum number of decoding iterations is reached, the decoder ends the calculation and outputs the decoding result; otherwise, steps 2 and 3 are repeated. 5 . The 5G LDPC-based dual-layer scheduling method for a decoder according to claim 4 , wherein each layer of the 5G basic parity check matrix adopts a block parallel structure. 6 . 6. The 5G LDPC-based dual-layer scheduling decoder double-layer scheduling method according to claim 4, wherein said dividing adjacent odd-numbered layers and even-numbered layers into one group comprises: two layers of each group It is divided into a pre-computation layer and a waiting layer; the odd-numbered layer is a pre-computation layer; the even-numbered layer is a waiting layer. 7. The double-layer scheduling method for a 5G LDPC-based decoder according to claim 4, wherein the step 2 further comprises: during the decoding and scheduling, reordering the input and output sequence of the variable nodes of each layer arrangement. 8. The double-layer scheduling method for a 5G LDPC-based decoder according to claim 7, wherein the rearranging the input and output order of the variable nodes of each layer comprises: The input order of the first calculation layer for all groups is adjusted so that the variable nodes that do not conflict with the previous group are input first, and then other variable nodes are input. The input order of the waiting layer of the non-orthogonal group is adjusted to first input the variable nodes that do not conflict with the first calculation layer of this group, and then input the conflict variable nodes between the groups that conflict with the previous group, and wait for the first calculation layer to update the conflict variable nodes. , and finally enter the intragroup conflict variable node. The input order of the waiting layer of the orthogonal group is adjusted to first input the variable nodes that have no conflict with the previous group, and then input other variable nodes, without waiting in the middle. The output order of the precomputed layer of the non-orthogonal group is adjusted to output the conflict variable nodes in the group that conflict with the waiting layer of this group first, and then output other variable nodes. The output order of the precomputed layer of the orthogonal group is adjusted to output the conflicting variable nodes between groups that conflict with the next group first, and then output other variable nodes. The output order of the waiting layer of all groups is adjusted to output the conflict variable nodes between groups that conflict with the next group first, and then output other variable nodes. 9. The double-layer scheduling method of a 5G LDPC-based decoder according to claim 7, wherein the rearrangement of the input and output sequence of the variable nodes of each layer further comprises: the current group first outputs and the next The group has conflicting variable nodes. 10 . An information data processing terminal, wherein the information data processing terminal is configured to execute the 5G LDPC-based double-layer scheduling method for a decoder and decoder according to any one of claims 1-7. 11 .

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