CN114823779B - Splicing display screen - Google Patents
Splicing display screen Download PDFInfo
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- CN114823779B CN114823779B CN202210379606.5A CN202210379606A CN114823779B CN 114823779 B CN114823779 B CN 114823779B CN 202210379606 A CN202210379606 A CN 202210379606A CN 114823779 B CN114823779 B CN 114823779B
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- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000010410 layer Substances 0.000 claims description 136
- 239000010409 thin film Substances 0.000 claims description 28
- 239000002346 layers by function Substances 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 19
- 238000005538 encapsulation Methods 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 239000003086 colorant Substances 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 14
- 239000012790 adhesive layer Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
- H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
- H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
- H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
本申请实施例公开了一种拼接显示屏，包括母板、至少两子板以及LED发光基板，所述至少两子板绑定在一所述母板上，相邻两个所述子板拼接形成拼缝；所述LED发光基板绑定在所述母板上，并位于所述拼缝内。本申请旨在解决大尺寸中的拼接屏在拼接工艺中拼缝的技术难题，以达到无缝拼接显示的目的。
The embodiment of the present application discloses a spliced display screen, comprising a motherboard, at least two sub-boards and an LED light-emitting substrate, wherein the at least two sub-boards are bound to one of the motherboards, and two adjacent sub-boards are spliced to form a splicing seam; the LED light-emitting substrate is bound to the motherboard and is located in the splicing seam. The present application aims to solve the technical problem of splicing seams in the splicing process of large-size spliced screens, so as to achieve the purpose of seamless splicing display.
Description
Technical Field
The application relates to the technical field of display, in particular to a spliced display screen.
Background
OLED (Organic LIGHT EMITTING Diode) display devices have self-luminescence, do not need backlight source, have high contrast, thin thickness, wide viewing angle, fast reaction speed, can be used for excellent characteristics such as flexible panel, curved surface panel, and the like, are uniformly recognized as the mainstream technology of next generation display, and are favored by various large display manufacturers. However, the development of OLED technology has been mainly applied in the middle-small size field, and the technology of splicing is still needed for large-size OLED display.
Disclosure of Invention
The embodiment of the application provides a spliced display screen, which aims to solve the technical problem of splicing seams of a large-size spliced screen in a splicing process so as to achieve the aim of seamless spliced display.
The embodiment of the application provides a spliced display screen, which comprises the following components:
A motherboard;
At least two sub-boards, which are bound on one mother board and are spliced to form a splice, and
The LED light-emitting substrate is bound on the motherboard and is positioned in the splice.
Optionally, in some embodiments of the present application, the LED light-emitting substrate includes an array substrate and a plurality of first pixel units, where the array substrate is bound to the motherboard, and the plurality of first pixel units are arranged on a surface of the array substrate facing away from the motherboard.
Optionally, in some embodiments of the present application, the array substrate includes a first substrate, an electrode layer, a first connection electrode, and a second connection electrode, the first pixel unit includes at least one LED device, the electrode layer includes a first bonding pad and a second bonding pad;
The LED device comprises a motherboard, a first substrate, an electrode layer, an LED device, a first connecting electrode, a second connecting electrode, a first binding pad and a second connecting electrode, wherein the first substrate is bound and connected to the motherboard, the electrode layer is arranged on one side of the first substrate, which is away from the motherboard, the LED device is bound and connected with the electrode layer, the first connecting electrode and the second connecting electrode are arranged on one side of the first substrate, which faces the motherboard, the first connecting electrode is electrically connected with the first binding pad, the second connecting electrode is electrically connected with the second binding pad, and the first connecting electrode and the second connecting electrode are electrically connected with the motherboard.
Optionally, in some embodiments of the application, the motherboard includes:
A substrate;
An insulating layer arranged on the substrate, an opening arranged at the position of the insulating layer corresponding to the joint, a first connecting electrode and a second connecting electrode arranged in the opening, and
The metal layer is arranged on the insulating layer and comprises a first conductive pad and a second conductive pad, at least part of the first conductive pad and at least part of the second conductive pad are positioned in the open hole, the first conductive pad is connected with the first connecting electrode in a binding mode, and the second conductive pad is connected with the second connecting electrode in a binding mode.
Optionally, in some embodiments of the present application, the motherboard further includes a first driving functional layer, the first driving functional layer is disposed between the substrate and the insulating layer, the first driving functional layer includes a first thin film transistor, and a source or a drain of the first thin film transistor is connected to the first conductive pad.
Optionally, in some embodiments of the present application, the daughter board includes:
the second substrate is provided with a plurality of bonding pads on one surface close to the motherboard, and the bonding pads are connected and bound to the motherboard;
a second driving functional layer disposed on a surface of the second substrate opposite to the motherboard, the second driving functional layer including a plurality of second thin film transistors, one of the second thin film transistors being electrically connected to one of the bonding pads, and
The second pixel units are arranged on one surface of the second driving functional layer, which is away from the motherboard, at intervals.
Optionally, in some embodiments of the present application, the horizontal distance between two adjacent first pixel units is a, and the horizontal distance between two adjacent second pixel units is B;
the horizontal distance between the first pixel unit of the LED light-emitting substrate near the edge of the sub-board and the second pixel unit of the adjacent sub-board is C, and A=B=C.
Optionally, in some embodiments of the present application, the second driving function layer includes:
the flat layer is arranged on one surface, away from the motherboard, of the second thin film transistor;
a plurality of anodes, wherein the anodes are arranged on the flat layer, and one anode is connected with the source electrode or the drain electrode of one second thin film transistor;
The pixel definition layer is arranged on one surface of the flat layer, which is away from the motherboard, and is provided with a plurality of openings, and one opening exposes one anode;
The second pixel unit comprises a plurality of light-emitting layers, wherein the colors of the light-emitting layers are different;
the daughter board further comprises an encapsulation layer, and the encapsulation layer is arranged on one surface, away from the mother board, of the pixel definition layer.
Optionally, in some embodiments of the present application, the tiled display screen further includes a cover plate, where the cover plate is disposed on a surface of the encapsulation layer of each of the daughter boards, which is away from the motherboard, and covers the LED light emitting substrate.
Optionally, in some embodiments of the present application, the tiled display screen further includes a black flat layer, a plurality of first color film layers, and a plurality of second color film layers;
The black flat layer is arranged between the packaging layer of each sub-board and the cover plate, a plurality of through holes are formed in the black flat layer corresponding to the light-emitting layers, and the first color film layer is arranged in one through hole;
The second color film layers correspond to the first pixel units, and one second color film layer is arranged between one surface, away from the array substrate, of the first pixel unit and the cover plate.
Optionally, in some embodiments of the present application, the black flat layer extends to cover a peripheral side surface of the sub-board to form a shielding portion, and the shielding portion is located between the peripheral side surface of the sub-board and the peripheral side surface of the LED substrate.
The spliced display screen provided by the application comprises a mother board, at least two daughter boards and an LED luminous substrate, wherein the at least two daughter boards are bound on one mother board, and the adjacent two daughter boards are spliced to form a splice. The LED luminous substrate is bound on the mother board and positioned in the splice. Therefore, the LED luminous substrate is added between the two sub-board splicing units, so that the splice joint is normally displayed, and the technical problem that a large-size spliced screen is spliced in the splicing process is solved, so that the aim of seamless splicing display is fulfilled.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first embodiment of a tiled display screen according to the present application;
Fig. 2 is a schematic diagram of a spliced sub-board and an LED light emitting substrate of the spliced display screen provided by the present application;
FIG. 3 is a schematic diagram of a second embodiment of a tiled display screen according to the present application;
fig. 4 is a schematic structural diagram of a third embodiment of a tiled display screen according to the present application.
Reference numerals illustrate:
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the application. In the present application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower directions of the device in actual use or operation, and specifically the directions of the drawings in the drawings, while "inner" and "outer" are used with respect to the outline of the device.
The embodiment of the application provides a spliced display screen 100. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.
Referring to fig. 1, a tiled display screen 100 according to a first embodiment of the present application includes a motherboard 10, at least two sub-boards 20, and an LED light emitting substrate 30, wherein at least two sub-boards 20 are bound to a motherboard 10, and two adjacent sub-boards 20 are tiled to form a tile 90. The LED lighting substrate 30 is bound to the motherboard 10 and is located within the seam 90.
So through increasing LED luminescent substrate 30 in the middle of two sub-board 20 concatenation units to make the normal demonstration of seam 90 department, and then solve the technical problem of seam 90 in the concatenation technology of jumbo size concatenation screen, in order to reach the purpose of seamless concatenation demonstration.
The sub-board 20 is typically an Organic Light-Emitting Diode (OLED), and a plurality of Organic electroluminescent display panels are spliced together to meet the requirements of mutually spliced and collaborative display of the screens. And the same motherboard 10 is used for electrically driving so as to ensure the stability of the spliced daughter board 20 and LED luminous substrate 30.
In an embodiment of the application, the LED light emitting substrate 30 includes an array substrate 31 and a plurality of first pixel units 32, the array substrate 31 is bound to the motherboard 10, and the plurality of first pixel units 32 are arranged on a surface of the array substrate 31 facing away from the motherboard 10. The array of the plurality of first pixel units 32 is arranged on the array substrate 31 to make the overall structure of the spliced screen more compact, and simultaneously ensure the display effect. In addition, the arrangement may be performed in other manners, such as forming a single row arrangement by using a plurality of sub-boards 20, or arranging by using a special pattern, such as a "rice" shape or other flower shape, etc., without limitation.
Further, the array substrate 31 includes a first substrate 311, an electrode layer 312, a first connection electrode 313, and a second connection electrode 314. The first pixel unit 32 includes at least one LED device 321. The electrode layer 312 includes a first bonding pad 3121 and a second bonding pad 3122. The first substrate 311 is bound and connected to the motherboard 10, the electrode layer 312 is disposed on a side of the first substrate 311 away from the motherboard 10, the LED device 321 is bound and connected to the electrode layer 312, the first connection electrode 313 and the second connection electrode 314 are disposed on a side of the first substrate 311 facing the motherboard 10, the first connection electrode 313 is electrically connected to the first binding pad 3121, the second connection electrode 314 is electrically connected to the second binding pad 3122, and the first connection electrode 313 and the second connection electrode 314 are both electrically connected to the motherboard 10.
The LED device 321 is welded and bound to the electrode layer 312, and the LED device 321 is a tricolor LED chip, where the LED device 321 may be a Mini-LED (sub-millimeter light emitting diode) chip or a Micro-LED (Micro light emitting diode), and the size of the Mini-LED lamp is in a micron level, which can provide higher resolution, thereby improving the display effect. Unlike the organic electroluminescent display panel, which needs to encapsulate the whole effective light emitting area, the micro LED or miniLED is based on a self-encapsulation technology, i.e., the micro LED or miniLED encapsulates a single sub-pixel, and no additional encapsulation design is needed, so that the size of the boundary can be reduced to zero, and the influence of the boundary caused by the whole encapsulation of the organic electroluminescent display panel is overcome. The Micro-LED or Mini-LED adopts a standard RGB arrangement, and the plurality of LED devices 321 includes a red LED device, a green LED device, and a blue LED device. And electrical conduction between the electrode layer 312 and the motherboard 10 is achieved through the first connection electrode 313 and the second connection electrode 314. When the polyimide substrate 11 is used as the first substrate 311, the polyimide is a flexible material, so that the flexibility of the polyimide substrate can be provided for large-size tiled display, and the display effect can be further improved.
Further, the motherboard 10 includes a substrate 11, an insulating layer 12 and a metal layer 13, the insulating layer 12 is disposed on the substrate 11, an opening 121 is formed at a position of the insulating layer 12 corresponding to the seam 90, and the first connection electrode 313 and the second connection electrode 314 are disposed in the opening 121. The metal layer 13 is disposed on the insulating layer 12, the metal layer 13 includes a first conductive pad 131 and a second conductive pad 132, at least a portion of the first conductive pad 131 and at least a portion of the second conductive pad 132 are disposed in the opening 121, the first conductive pad 131 is bonded to the first connection electrode 313, and the second conductive pad 132 is bonded to the second connection electrode 314.
The metal layer 13 is bonded to the daughter board 20 for electrical conduction. The opening 121 is formed in the insulating layer 12 for accommodating the first connecting electrode 313 and the second connecting electrode 314, so that the structure between the motherboard 10 and the LED light-emitting substrate 30 is more compact, the whole size of the spliced screen is more favorable to be thinned, meanwhile, the first conductive pad 131 at the bottom of the opening 121 is bound and connected with the first connecting electrode 313, and the second conductive pad 132 at the bottom of the opening 121 is bound and connected with the second connecting electrode 314, so that the electrical conduction between the motherboard 10 and the LED light-emitting substrate 30 is realized, and the stability after connection between the motherboard 10 and the LED light-emitting substrate 30 is further improved. In addition, the first conductive pad 131 and the second conductive pad 132 extend to cover the hole wall of the opening 121, and partially extend to a surface of the insulating layer 12 facing away from the substrate 11. So as to improve the stability of the first conductive pad 131 and the second conductive pad 132 after being disposed, and further ensure the electrical conduction between the first conductive pad 131 and the second conductive pad 132 and the first connection electrode 313 and the second connection electrode 314, respectively. It should be noted that, a conductive adhesive layer 80 is further disposed between the insulating layer 12 and each of the sub-board 20 and the first substrate 311, and the conductive adhesive layer 80 is filled in the opening 121. The conductive adhesive layer 80 not only improves the connection stability between the motherboard 10 and the LED light-emitting substrate 30 and the daughter board 20, but also improves the electrical conduction between the metal layer 13 and the LED light-emitting substrate 30 and the daughter board 20, and of course, the conductive adhesive layer 80 may be other adhesive layers.
In an embodiment of the present application, the daughter board 20 includes a second substrate 21, a second driving functional layer 22, and a plurality of second pixel units 23, where a plurality of pads 211 are disposed on a surface of the second substrate 21 adjacent to the motherboard 10, and the plurality of pads 211 are connected and bound to the motherboard 10. The second driving functional layer 22 is disposed on a surface of the second substrate 21 facing away from the motherboard 10, and the second driving functional layer 22 includes a plurality of second thin film transistors 221, and the second thin film transistors 221 are electrically connected to a bonding pad 211. The plurality of second pixel units 23 are arranged on one surface of the second driving functional layer 22 away from the motherboard 10at intervals.
It is understood that the material of the second substrate 21 may be plastic or glass, or may be the same as that of the first substrate 311. Further, a buffer layer 25, an inorganic insulating layer 26, and the like may be sequentially stacked on the second substrate 21 and the second driving function layer 22. The second substrate 21 is bound and fixed at the motherboard 10 through a plurality of bonding pads 211, and the plurality of bonding pads 211 are electrically connected with the plurality of second thin film transistors 221 respectively, so that the motherboard 10 can control the light emitting intensity of the plurality of second pixel units 23 through the second thin film transistors 221. And a plurality of second pixel units 23 are arranged in an array manner on the second driving functional layer 22, so that the structural arrangement is more compact.
Optionally, the second driving functional layer 22 includes a planarization layer 222, a plurality of anodes 223, and a pixel defining layer 224, where the planarization layer 222 is disposed on a side of the second thin film transistor 221 facing away from the motherboard 10. A plurality of anodes 223 are disposed on the planarization layer 222, and one anode 223 is connected to the source or drain of a second thin film transistor 221. The pixel defining layer 224 is disposed on a surface of the flat layer 222 facing away from the motherboard 10, and the pixel defining layer 224 is provided with a plurality of openings 2241, wherein an anode 223 is exposed through one of the openings 2241. The second pixel unit 23 includes a plurality of light emitting layers 231, and the colors of the plurality of light emitting layers 231 are different. A light emitting layer 231 is disposed within an opening 2241.
Wherein the planarization layer 222 is formed on the side of the second thin film transistor 221 facing away from the mother substrate 10 by physical deposition or chemical deposition. A pixel defining layer 224 is formed on a surface of the planarization layer 222 facing away from the motherboard 10, and a plurality of openings 2241 are formed in the pixel defining layer 224 to expose a plurality of anodes 223, so that an anode 223 can be electrically connected to the light emitting layer 231 located in one of the openings 2241. The light emitting layer 231 may include a red light emitting layer 231, a blue light emitting layer 231, a green light emitting layer 231, and the like. The daughter board 20 further includes an encapsulation layer 24, and the encapsulation layer 24 is disposed on a side of the pixel definition layer 224 facing away from the motherboard 10. Wherein, when the light emitting layer 231 emits light and propagates outward, there is a surface plasmon effect at the metal/dielectric interface, which causes a decrease in the light emitting efficiency, so that the effect can be improved by providing the encapsulation layer 24, and the encapsulation layer 24 can also form a protection for the second driving function layer 22. Further, the tiled display screen 100 further includes a cover plate 40, where the cover plate 40 is disposed on a surface of the encapsulation layer 24 of each daughter board 20 facing away from the motherboard 10, and covers the LED light emitting substrate 30. Wherein, not only is the cover plate 40 used to protect each sub-board 20 and the LED light-emitting substrate 30, but also the flatness of the spliced screen can be ensured.
Referring to fig. 2 in combination, further, the horizontal distance between two adjacent first pixel units 32 is a. The horizontal distance between two adjacent second pixel units 23 is B. The horizontal distance between the first pixel unit 32 at the edge of the LED light emitting substrate 30 near the sub-board 20 and the second pixel unit 23 of the adjacent sub-board 20 is C, a=b=c. The distance value relationship between each pixel of the sub-board 20 and the LED light-emitting substrate 30 is set to satisfy a=b=c, so that the light-emitting effect on the LED light-emitting substrate 30 is the same as the light-emitting effect on the sub-board 20, and the display effect at the seam 90 is the same as the display effect at each sub-board 20, so as to achieve the purpose of seamless joint display.
Referring to fig. 3, the display panel 100 according to the second embodiment of the present application is different from the display panel 100 according to the first embodiment in that the motherboard 10 further includes a first driving functional layer 14, the first driving functional layer 14 is disposed between the substrate 11 and the insulating layer 12, the first driving functional layer 14 includes a first thin film transistor 141, and a source or a drain of the first thin film transistor 141 is connected to the first conductive pad 131. In the display panel, a thin film transistor may be used as a switching device or a driving device. The first thin film transistor 141 and the LED light emitting substrate 30 are disposed opposite to each other, so that the first thin film transistor 141 is added at the position of the motherboard 10 connected with the LED light emitting substrate 30, and the voltage given by the LED light emitting substrate 30 can be adjusted by the first thin film transistor 141, so as to adjust the light emitting intensity thereof, thereby keeping the same with the display effect of the daughter board 20, and achieving truly seamless splicing.
Still further, the tiled display screen 100 further includes a black planarization layer 50, a plurality of first color film layers 60, and a plurality of second color film layers 70. The black planarization layer 50 is disposed between the package layer 24 and the cover 40 of each sub-board 20, and the black planarization layer 50 has a plurality of through holes corresponding to the plurality of light emitting layers 231, and a first color film layer 60 is disposed in one of the through holes. The second color film layers 70 correspond to the first pixel units 32, and the second color film layers 70 are disposed between a surface of the first pixel units 32 facing away from the array substrate 31 and the cover plate 40.
The first color film layer 60 and the second color film layer 70 may include a red filter, a green filter, and a blue filter that are disposed at intervals. The red filter, the green filter, and the blue filter may include diffusion particles and be filters having a diffusion effect. The red filter, the green filter, and the blue filter may have a rectangular shape and be alternately arranged. The red filter, the green filter, the blue filter, and the black and white planarization layer 50 may be formed on the sub-board 20 or the first pixel unit 32 by printing. By providing the black planarization layer 50, the first color film layer 60, and the second color film layer 70 to form a filter layer, when the light emitted from the light emitting layer 231 passes through the filter layer, the light can be diffused to various angles outside the tiled display screen 100 under the effect of the diffusion particles. The black planarization layer 50 may be used to divide adjacent color resistors, shade gaps of colors, prevent light leakage or color mixing, and further ensure a display effect of the tiled display screen 100.
Further, the black flat layer 50 extends to cover the peripheral side surface of the sub-board 20 to form a shielding portion 51, and the shielding portion 51 is located between the peripheral side surface of the sub-board 20 and the peripheral side surface of the LED substrate 11. Wherein the black flat layer 50 is formed with a shielding portion 51 between the peripheral side surface of the sub-board 20 and the peripheral side surface of the LED substrate 11 to further eliminate the problem of visual deviation of the splice area.
Referring to fig. 4, the third embodiment of the present application is different from the above embodiments in that the LED light emitting substrate 30 further includes a third driving functional layer 315, the third driving functional layer 315 is disposed between the first substrate 311 and the electrode layer 312 and is electrically connected to the electrode layer 312, and the third driving functional layer 315 includes a third thin film transistor 3151, and a source or a drain of the third thin film transistor 3151 is connected to the first connection electrode 313 or the second connection electrode 314, so that the voltage applied to the LED device 321 can be adjusted by the third thin film transistor 3151, and the light emitting intensity thereof can be adjusted, so that the display effect of the sub-board 20 is kept consistent, and seamless splicing in a real sense is achieved.
While the foregoing describes a tiled display screen 100 provided in the embodiments of the present application in detail, specific examples are applied to illustrate the principles and embodiments of the present application, and the above examples are only for aiding in understanding of the method and core concept of the present application, and meanwhile, the present application should not be construed as being limited to the embodiments and application scope of the present application, since the concept of the present application is modified by those skilled in the art.
Claims (9)
1. A tiled display screen, comprising:
A motherboard;
At least two sub-boards, which are bound on one mother board and are spliced to form a splice, and
The LED light-emitting substrate is bound on the motherboard and is positioned in the joint, and comprises an array substrate and a plurality of first pixel units, wherein the array substrate is bound on the motherboard, and the plurality of first pixel units are arranged on one surface of the array substrate, which is away from the motherboard, in an array manner;
The array substrate comprises a first substrate, an electrode layer, a first connecting electrode and a second connecting electrode, wherein the first pixel unit comprises at least one LED device;
The LED device comprises a motherboard, a first substrate, an electrode layer, an LED device, a first connecting electrode, a second connecting electrode, a first binding pad and a second connecting electrode, wherein the first substrate is bound and connected to the motherboard, the electrode layer is arranged on one side of the first substrate, which is away from the motherboard, the LED device is bound and connected with the electrode layer, the first connecting electrode and the second connecting electrode are arranged on one side of the first substrate, which faces the motherboard, the first connecting electrode is electrically connected with the first binding pad, the second connecting electrode is electrically connected with the second binding pad, and the first connecting electrode and the second connecting electrode are electrically connected with the motherboard.
2. The tiled display screen according to claim 1, wherein the motherboard includes:
A substrate;
An insulating layer arranged on the substrate, an opening arranged at the position of the insulating layer corresponding to the joint, a first connecting electrode and a second connecting electrode arranged in the opening, and
The metal layer is arranged on the insulating layer and comprises a first conductive pad and a second conductive pad, at least part of the first conductive pad and at least part of the second conductive pad are positioned in the open hole, the first conductive pad is connected with the first connecting electrode in a binding mode, and the second conductive pad is connected with the second connecting electrode in a binding mode.
3. The tiled display screen according to claim 2, wherein the motherboard further comprises a first driving functional layer disposed between the substrate and the insulating layer, the first driving functional layer comprising a first thin film transistor, a source or a drain of the first thin film transistor being connected to the first conductive pad.
4. The tiled display screen according to claim 1, wherein the daughter board includes:
The second substrate is provided with a bonding pad on one surface close to the motherboard, and the bonding pad is connected and bound with the motherboard;
a second driving functional layer disposed on a surface of the second substrate opposite to the motherboard, the second driving functional layer including a plurality of second thin film transistors, one of the second thin film transistors being electrically connected to one of the bonding pads, and
The second pixel units are arranged on one surface of the second driving functional layer, which is away from the motherboard, at intervals.
5. The tiled display screen according to claim 4, wherein the horizontal distance between two adjacent first pixel elements is a; the horizontal distance between two adjacent second pixel units is B;
the horizontal distance between the first pixel unit of the LED light-emitting substrate near the edge of the sub-board and the second pixel unit of the adjacent sub-board is C, and A=B=C.
6. The tiled display screen according to claim 4, wherein the second drive function layer includes:
the flat layer is arranged on one surface, away from the motherboard, of the second thin film transistor;
a plurality of anodes, wherein the anodes are arranged on the flat layer, and one anode is connected with the source electrode or the drain electrode of one second thin film transistor;
The pixel definition layer is arranged on one surface of the flat layer, which is away from the motherboard, and is provided with a plurality of openings, and one opening exposes one anode;
The second pixel unit comprises a plurality of light-emitting layers, wherein the colors of the light-emitting layers are different;
the daughter board further comprises an encapsulation layer, and the encapsulation layer is arranged on one surface, away from the mother board, of the pixel definition layer.
7. The tiled display screen according to claim 6, further comprising a cover plate disposed on a side of the encapsulation layer of each of the sub-boards facing away from the motherboard and covering the LED lighting substrate.
8. The tiled display screen of claim 7, further comprising a black planar layer, a plurality of first color film layers, and a plurality of second color film layers;
The black flat layer is arranged between the packaging layer of each sub-board and the cover plate, a plurality of through holes are formed in the black flat layer corresponding to the light-emitting layers, and the first color film layer is arranged in one through hole;
The second color film layers correspond to the first pixel units, and one second color film layer is arranged between one surface, away from the array substrate, of the first pixel unit and the cover plate.
9. The tiled display screen of claim 8, wherein the black planar layer extends over the peripheral side of the sub-board forming a barrier between the peripheral side of the sub-board and the peripheral side of the LED lighting substrate.
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| CN111653207A (en) * | 2020-07-30 | 2020-09-11 | 上海天马微电子有限公司 | Display module assembly, display device and spliced screen |
| CN112767849A (en) * | 2021-02-01 | 2021-05-07 | Tcl华星光电技术有限公司 | Tiled display panel, driving method thereof and tiled display device |
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| TW201539403A (en) * | 2014-04-01 | 2015-10-16 | Gio Optoelectronics Corp | Tiled display apparatus |
| CN110634417B (en) * | 2019-10-29 | 2021-10-22 | 云谷（固安）科技有限公司 | Display module and display device |
| CN114038340B (en) * | 2021-11-29 | 2023-10-13 | 深圳市华星光电半导体显示技术有限公司 | Spliced display device and spliced display screen |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111653207A (en) * | 2020-07-30 | 2020-09-11 | 上海天马微电子有限公司 | Display module assembly, display device and spliced screen |
| CN112767849A (en) * | 2021-02-01 | 2021-05-07 | Tcl华星光电技术有限公司 | Tiled display panel, driving method thereof and tiled display device |
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