CN114823285A - Ultrathin chip and flattening method and application thereof - Google Patents

Abstract

The invention relates to an ultra-thin chip and a planarization method and application thereof. The planarization method includes the following steps: providing a chip, the chip including a silicon substrate and a functional layer arranged in layers, and the edge of the chip is warped in the direction of the functional layer; pre-compressing the chip to make the The edge of the chip is warped in the direction of the silicon substrate; and a thin film with a thickness of less than or equal to 5 μm is formed on the surface of the silicon substrate away from the functional layer to obtain a flattened ultra-thin chip. The planarization method can increase the permanent tensile stress introduced by the film of the same thickness, thereby improving the warpage degree of the ultra-thin chip on the basis of increasing the thickness less, thereby improving the packaging yield and reliability of the ultra-thin chip.

Description

Ultra-thin chip and its planarization method and application

technical field

The invention relates to the field of chip technology, in particular to an ultra-thin chip and a planarization method and application thereof.

Background technique

Ultra-thin chips have broad application prospects. When the thickness of ultra-thin chips is less than 50 μm, ultra-thin chips have good flexibility and can be applied to flexible electronics. However, as the thickness of the ultra-thin chip decreases, its bending stiffness decreases exponentially. At this time, the residual stress introduced by the damage layer on the back of the ultra-thin chip and the mismatch strain introduced by the front functional layer will cause the ultra-thin chip to warp. This leads to problems such as low packaging yield and poor reliability.

The damage layer on the back of the ultra-thin chip can be removed by chemical mechanical polishing process. The functional layer on the front is the active area of the ultra-thin chip and cannot be removed. Therefore, the traditional flattening method of the ultra-thin chip is to deposit a thin film on the back. However, The permanent tensile stress of the film increases as the thickness of the film increases, so it is difficult to improve the warpage of ultra-thin chips on the basis of adding less thickness.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide an ultra-thin chip and a planarization method and application thereof in view of the above problems. The planarization method can increase the permanent tensile stress introduced by the film of the same thickness, so as to improve the thickness on the basis of increasing less thickness. The degree of warpage of ultra-thin chips, thereby improving the packaging yield and reliability of ultra-thin chips.

The present invention provides a method for flattening an ultra-thin chip, comprising the following steps:

A chip is provided, the chip includes a stacked silicon substrate and a functional layer, and the edge of the chip is warped toward the direction of the functional layer;

pre-compressing the chip to warp the edge of the chip in the direction of the silicon substrate; and

A thin film with a thickness of less than or equal to 5 μm is formed on the surface of the silicon substrate away from the functional layer to obtain a planarized ultra-thin chip.

In one embodiment, when the edge of the chip is warped in the direction of the functional layer, the warpage degree is α, and the value range of α is 10 μm-1000 μm.

In one embodiment, when the edge of the chip is warped in the direction of the silicon substrate, the warpage degree is β, and the value of β ranges from 10 μm to 1000 μm.

In one embodiment, the absolute value of the difference between α and β is less than or equal to 100 μm.

In one embodiment, the step of pre-compressing the chip includes: forming a protective film on the surface of the functional layer away from the silicon substrate, and then fixing the chip with the protective film with a clamp, The surface of the silicon substrate away from the protective film is pre-compressed by applying pressure.

In one embodiment, the material of the thin film is selected from at least one of metal, SiN, SiO ₂ or polymer materials.

In one embodiment, the polymer material is selected from at least one of wafer bonding film, polyimide or parylene.

In one embodiment, the thickness of the chip is less than or equal to 50 μm.

An ultra-thin chip is obtained after the chip is flattened by the above-mentioned flattening method.

A flexible electronics, including the above-mentioned ultra-thin chip.

The flattening method for an ultra-thin chip provided by the present invention introduces temporary compressive stress into the chip by pre-compressing the chip, so that in the step of forming a thin film on the surface of the silicon substrate away from the functional layer, the permanent compressive stress introduced by the thin film of the same thickness The tensile stress increases, and the tensile stress of the film on the back of the chip increases, and then on the basis of adding less thickness, the warpage degree of the ultra-thin chip is improved, and the flattening of the ultra-thin chip is realized.

Description of drawings

Fig. 1 is the schematic diagram of the chip whose edge is warped toward the direction of the functional layer;

FIG. 2 is a schematic flowchart of a planarization method for an ultra-thin chip;

In the figure, 10, chip; 101, silicon substrate; 102, functional layer; 20, thin film; 30, ultra-thin chip.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant embodiments. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the present disclosure is provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The ultra-thin chip 30 provided by the present invention and its planarization method and application will be further described below.

As shown in FIG. 1 and FIG. 2 , the planarization method of the ultra-thin chip 30 provided by the present invention includes the following steps:

S10, a chip 10 is provided, the chip 10 includes a stacked silicon substrate 101 and a functional layer 102, and the edge of the chip 10 is warped in the direction of the functional layer 102;

S20, pre-compressing the chip 10 to warp the edge of the chip 10 toward the direction of the silicon substrate 101; and

S30 , a thin film 20 with a thickness of less than or equal to 5 μm is formed on the surface of the silicon substrate 101 away from the functional layer 102 to obtain a planarized ultra-thin chip 30 .

It can be understood that the surface of the silicon substrate 101 away from the functional layer 102 is the back of the chip 10 , and the surface of the functional layer 102 away from the silicon substrate 101 is the front of the chip 10 . In one embodiment, the silicon substrate 101 is away from the functional layer 102 . There is a damaged layer on the surface of the silicon substrate, the functional layer 102 includes a device doping layer, an intermediate metal dielectric layer and a passivation layer arranged in layers, and the silicon substrate 101 is bonded to the device doping layer.

In the chip 10, residual stress will be introduced into the damaged layer, and mismatch strain will be introduced in the formation process of the device doping layer, the intermediate metal dielectric layer and the passivation layer, such as lattice mismatch, defects, growth stress, thermal strain, etc.; residual Both stress and mismatch strain can cause chip 10 to warp.

In step S10, the silicon substrate 101 is the convex surface of the chip 10, and the functional layer 102 is the concave surface of the chip 10. It should be noted that the definition of the convex surface is that any point on the surface of the convex surface is a cut surface, and the surface is always below the cut surface. ; The definition of concave surface is: any point on the surface of the concave surface is cut, and the surface is always the earthwork of the cut surface.

The chip 10 can be purchased as a raw material for the planarization method of the ultra-thin chip 30, or can be prepared by itself.

In one embodiment, the chip 10 is uniaxially warped, that is, two mutually perpendicular edges in the in-plane direction of the chip 10, one edge has a curvature of 0, and the other edge has a curvature greater than 0. At this time , the bending direction is parallel to one edge of the chip 10 , and one edge has almost no warpage.

When the edge of the chip 10 warps in the direction of the functional layer 102 , the warpage degree of the chip 10 is α, and the value of α ranges from 10 μm to 1000 μm, more preferably from 500 μm to 900 μm.

In step S20, by pre-compressing the chip 10, a temporary compressive stress is introduced into the chip 10, so that in the step of step S30, the permanent tensile stress introduced by the film 20 of the same thickness is increased, and then on the basis of increasing the thickness less , improving the warpage degree of the ultra-thin chip 30 and realizing the flattening of the ultra-thin chip 30 .

It should be noted that, in the chip 10 in step S20, the functional layer 102 is the convex surface of the chip 10, and the silicon substrate 101 is the concave surface of the chip 10; when the edge of the chip 10 is warped in the direction of the silicon substrate 101, the The degree of warpage is β, and the value range of β is 10 μm-1000 μm, more preferably 500 μm-900 μm.

It should be noted that the present invention does not specifically limit the method of pre-compressing the chip 10. In one embodiment, the step of pre-compressing the chip 10 includes: forming a protective film on the surface of the functional layer 102 away from the silicon substrate 101, Then use a clamp to fix the chip 10 with the protective film, and apply pressure on the surface of the silicon substrate 101 away from the protective film for pre-compression. Optionally, the clamp is selected from a concave clamp, and the protective film is attached to the surface of the concave clamp. Fixation is achieved while introducing temporary compressive stress.

The value of α and the value of β can be the same or different. In order to better balance the stress and prevent the chip from warping too much and breaking in the opposite direction, in one embodiment, the absolute value of the difference between α and P is less than or It is equal to 100 μm, preferably, the absolute value of the difference between α and β is less than or equal to 70 μm, and further preferably, the absolute value of the difference between α and β is less than or equal to 30 μm.

In one embodiment, before the step of forming the thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102, the method further includes polishing the surface of the silicon substrate 101 away from the functional layer 102 to remove the damaged layer of the silicon substrate 101, which can be It is understood that the thickness of the damaged layer is smaller than the thickness of the silicon substrate 101 in the ultra-thin chip 30 .

In one embodiment, the material of the thin film 20 is selected from at least one of metal, SiN, SiO ₂ or a polymer material, wherein the polymer material has better flexibility than other materials, which is more conducive to the ultra-thin chip 30 . It is used in flexible electronics, and the polymer material can be directly bonded to the flexible circuit board in the subsequent mounting of the ultra-thin chip 30. Therefore, the material of the film 20 is preferably selected from polymer materials. The material is selected from at least one of die attach film (DAF), polyimide or parylene.

When the material of the thin film 20 is selected from metals, the step of forming the thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102 includes sequentially forming a first metal thin film 20 and a second metal thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102 For the metal thin film 20, in one embodiment, the material of the first metal thin film 20 and the silicon substrate 101 have high peel strength titanium, and the material of the second metal thin film 20 is selected from at least one of copper, nickel or silver.

In order to better reduce the warpage of the ultra-thin chip 30, in one embodiment, the thickness of the thin film 20 is calculated based on the theory of large-deformation slabs and bridges or the theory of thin-film substrate systems. Specifically, the theory of large-deformation slabs and bridges is used to analyze the system The geometric equation of , the thin film substrate system theory introduces the mismatch strain into the geometric equation, and finally the governing equation satisfied when the warpage curvature of the system is zero is given by the energy minimum principle.

In one embodiment, the thin film 20 is formed on the surface of the silicon substrate 101 away from the functional layer 102 by atomic layer deposition (ALD) or vapor deposition (CVD).

In one embodiment, after the step of forming the thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102 , the temporary compressive stress is released to obtain the ultra-thin chip 30 .

The flattening method of the ultra-thin chip 30 provided by the present invention can increase the permanent tensile stress introduced by the film 20 of the same thickness, so as to improve the warpage degree of the ultra-thin chip 30 on the basis of increasing the thickness less, thereby improving the ultra-thin chip 30 packaging yield and reliability.

The present invention provides an ultra-thin chip 30 obtained by flattening the chip 10 through the above-mentioned flattening method.

The ultra-thin chip 30 provided by the present invention has good flexibility and flatness, and can be well applied to flexible electronics.

In one embodiment, the thickness of the ultra-thin chip 30 is less than 50 μm, more preferably 20 μm-50 μm.

In one embodiment, the degree of warpage of the ultra-thin chip 30 is less than or equal to 100 μm, more preferably 30 μm-70 μm.

The present invention also provides a flexible electronics comprising the ultra-thin chip 30 as described above.

In one embodiment, the flexible electronics further includes a flexible substrate, and the flexible substrate is used to integrate the above-mentioned ultra-thin chip 30 .

In one embodiment, the material of the flexible substrate is a flexible material, including polydimethylsiloxane, aliphatic-aromatic copolyester, hydrogel or biocompatible dressing, which can be determined according to actual needs, here No restrictions apply.

The flexible electronics provided by the present invention has excellent flexibility and flatness, can realize mass production of products, and can be widely used in many fields such as wearable electronic devices, paper-based displays and health monitoring systems.

Hereinafter, the ultra-thin chip 30 and its planarization method and application will be further described through the following specific embodiments.

In the planarization method of the ultra-thin chip 30 provided in the embodiment 1-8 and the comparative example 1-4, the ultra-thin chip 30 includes a silicon substrate 101 , and a device doped layer and an intermediate metal layer are stacked on the surface of the silicon substrate 101 . A dielectric layer and a passivation layer, wherein the device doping layer, the intermediate metal dielectric layer and the passivation layer together constitute the functional layer 102 of the chip 10 , the surface of the silicon substrate 101 away from the functional layer 102 is the back of the chip 10 , and the functional layer 102 The surface away from the silicon substrate 101 is the front surface of the chip 10 .

Example 1

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 800 μm.

Choose to deposit DAF on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation plate bridge theory, the thickness of the DAF is calculated to be 5 μm. After the deposition is completed, the adhesive is debonded by ultraviolet light irradiation to release the temporary compressive stress, and the thickness of the DAF is 30 μm. For the ultra-thin chip 30, the edge of the ultra-thin chip 30 is warped in the direction of the functional layer 102, and the warpage degree is 100 μm.

Example 2

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 800 μm.

Select to deposit SiO ₂ on the surface of the silicon substrate 101 away from the functional layer 102. Based on the theory of the film 20 substrate system, the thickness of SiO ₂ is calculated to be 5 μm. The ultra-thin chip 30 is 30 μm, and the edge of the ultra-thin chip 30 is warped in the direction of the functional layer 102 , and the warpage degree is 200 μm.

Example 3

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 800 μm.

Choose to deposit SiN on the surface of the silicon substrate 101 away from the functional layer 102. Based on the theory of the film 20 substrate system, the thickness of SiN is calculated to be 5 μm. After the deposition, the adhesive is debonded by ultraviolet light irradiation to release the temporary compressive stress, and the thickness is 30 μm. For the ultra-thin chip 30, the edge of the ultra-thin chip 30 is warped toward the direction of the functional layer 102, and the warpage degree is 150 μm.

Example 4

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 800 μm.

Choose to deposit copper on the surface of the silicon substrate 101 away from the functional layer 102. Since copper has poor adhesion to the silicon substrate 101, it is easy to fall off. Therefore, before depositing copper, deposit titanium first. Based on the large deformation plate bridge theory, the calculation results The thickness of titanium is 0.5 μm, and the thickness of copper is 4.5 μm. After the deposition, the adhesive is debonded by ultraviolet light irradiation to release temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 faces the functional layer 102 The direction of warpage is 250μm.

Example 5

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 1600 μm.

Choose to deposit DAF on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation plate bridge theory, the thickness of the DAF is calculated to be 5 μm. After the deposition is completed, the adhesive is debonded by ultraviolet light irradiation to release the temporary compressive stress, and the thickness of the DAF is 30 μm. For the ultra-thin chip 30, the edge of the ultra-thin chip 30 is warped toward the direction of the silicon substrate 101, and the warpage degree is 300 μm.

Example 6

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

The front side of the chip 10 is temporarily bonded to the protective film, and then the protective film of the chip 10 is attached to the concave jig to introduce temporary compressive stress, so that the functional layer 102 of the chip 10 is the convex surface of the chip 10, and the silicon lining of the chip 10 The bottom 101 is the concave surface of the chip 10, and the degree of warpage is 100 μm.

Choose to deposit DAF on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation plate bridge theory, the thickness of the DAF is calculated to be 5 μm. After the deposition is completed, the adhesive is debonded by ultraviolet light irradiation to release the temporary compressive stress, and the thickness of the DAF is 30 μm. For the ultra-thin chip 30, the edge of the ultra-thin chip 30 is warped toward the direction of the functional layer 102, and the warpage degree is 300 μm.

Comparative Example 1

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

A DAF of 5 μm is deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm.

Comparative Example 2

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

5μm Siθ ₂ is deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm.

Comparative Example 3

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

Select to deposit 5 μm SiN on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm.

Comparative Example 4

The chip 10 is provided with a thickness of 25 μm and a warpage of 800 μm. The silicon substrate 101 of the chip 10 is a convex surface of the chip 10 , and the functional layer 102 of the chip 10 is a concave surface of the chip 10 .

Select to deposit 0.5 μm of titanium and 4.5 μm of copper on the surface of the silicon substrate 101 away from the functional layer 102 in sequence to obtain an ultra-thin chip 30 with a thickness of 30 μm. The edge of the ultra-thin chip 30 is warped in the direction of the functional layer 102 . The curvature is 550 μm.

It should be noted that the terms "first" and "second" involved in the present invention are only to distinguish similar objects, and do not represent a specific order of objects. "First" and "second" may be used when permitted Swap a particular order or precedence. It is understood that "first" and "second" distinctions may be interchanged under appropriate circumstances to enable the embodiments of the invention described herein to be practiced in sequences other than those illustrated or described herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that when the term "comprising" is used in this specification, it refers to the presence of features, steps, operations, elements and/or components, but does not exclude one or more other features, steps, operations, elements, the presence of components and/or combinations thereof. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

The implementations described in the above exemplary embodiments do not represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with some aspects of the invention as recited in the appended claims. The terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, product or device comprising a list of elements includes not only those elements, but also other not expressly listed elements, or also include elements inherent to such a process, method, product or device. Without further limitation, it does not preclude the presence of additional identical or equivalent elements in a process, method, product or apparatus comprising the stated elements.

The technical features of the above embodiments can be combined arbitrarily. In order to simplify the description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, all It is considered to be the range described in this specification.

The above examples only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims (10)

1. a flattening method of an ultra-thin chip, is characterized in that, comprises the following steps: A chip is provided, the chip includes a stacked silicon substrate and a functional layer, and the edge of the chip is warped toward the direction of the functional layer; pre-compressing the chip to warp the edge of the chip in the direction of the silicon substrate; and A thin film with a thickness of less than or equal to 5 μm is formed on the surface of the silicon substrate away from the functional layer to obtain a planarized ultra-thin chip. 2 . The method for flattening an ultra-thin chip according to claim 1 , wherein when the edge of the chip is warped in the direction of the functional layer, the warpage degree is α, and the value range of α is 10 μm -1000μm. 3 . The planarization method of an ultra-thin chip according to claim 2 , wherein when the edge of the chip is warped in the direction of the silicon substrate, the warpage degree is β, and the value range of β is 3 . 10μm-1000μm. 4 . The method for planarizing an ultra-thin chip according to claim 3 , wherein the absolute value of the difference between α and β is less than or equal to 100 μm. 5 . 5. The method for planarizing an ultra-thin chip according to claim 3, wherein the step of pre-compressing the chip comprises: forming a protective film on the surface of the functional layer away from the silicon substrate, and then The chip with the protective film is fixed with a clamp, and pressure is applied to the surface of the silicon substrate away from the protective film for pre-compression. 6 . The method for planarizing an ultra-thin chip according to claim 1 , wherein the material of the thin film is selected from at least one of metal, SiN, SiO ₂ or polymer materials. 7 . 7 . The method for planarizing an ultra-thin chip according to claim 6 , wherein the polymer material is selected from at least one of wafer bonding film, polyimide or parylene. 8 . 8 . The method for planarizing an ultra-thin chip according to claim 1 , wherein the thickness of the chip is less than or equal to 50 μm. 9 . 9. An ultra-thin chip, characterized in that, the chip is obtained by flattening the chip by the flattening method according to any one of claims 1-8. 10. A flexible electronics, characterized in that it comprises the ultra-thin chip as claimed in claim 9.

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