CN114822348A - Source driver circuit, display device, and display driving method - Google Patents

Abstract

The invention provides a source driving circuit, a display device and a display driving method. The source electrode driving circuit of the embodiment of the invention comprises a serial-parallel conversion module, N first buffers, a second buffer, an arithmetic unit and a digital-analog conversion module, wherein N is an integer greater than 1: the N first buffers are sequentially cascaded; the output end of the serial-parallel conversion module is connected with the input end of a first-level first buffer in the N first buffers; the output ends of the N first buffers are connected with the input end of the arithmetic unit; the output end of the arithmetic unit is connected with the input end of the second buffer; and the output end of the second buffer is connected with the input end of the digital-to-analog conversion module. The embodiment of the invention improves the relevance of each pixel and surrounding pixels in the display data optimization process, is beneficial to improving the display effect, has relatively low realization cost and is beneficial to reducing the cost.

Description

Source driver circuit, display device, and display driving method

technical field

Embodiments of the present invention relate to the field of display technology, and in particular, to a source driving circuit, a display device, and a display driving method.

Background technique

With the development of display technology, the requirements for display effect are getting higher and higher, and the quality of the display signal provided by the signal source is relatively fixed. Rendering and other methods optimize the display effect. However, this method usually optimizes the display data by increasing the processor. However, the cost of this method is relatively high, and the improvement of the display effect is relatively limited.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a source driving circuit, a display device, and a display driving method, so as to reduce costs and improve the optimization effect for a display interface.

In order to solve the above-mentioned problems, the present invention is realized as follows:

In a first aspect, an embodiment of the present invention provides a source driver circuit, including a serial-to-parallel conversion module, N first buffers, a second buffer, an operator, and a digital-to-analog conversion module, wherein N is greater than 1 Integer:

the N first buffers are cascaded in sequence;

The output end of the serial-to-parallel conversion module is connected to the input end of the first-stage first buffer in the N first buffers;

The output ends of the N first buffers are all connected with the input ends of the arithmetic unit;

The output end of the arithmetic unit is connected to the input end of the second buffer;

The output end of the second buffer is connected to the input end of the digital-to-analog conversion module.

In some embodiments, the number of data channels of the first buffer is smaller than the number of data channels of the second buffer.

In a second aspect, an embodiment of the present invention provides a display device, comprising a display panel and the source driver circuit according to any one of the first aspect, the source driver circuit is used to drive the display panel to display an image, so The display panel includes a plurality of sub-pixel columns, and the data channels of the second buffer are in one-to-one correspondence with the sub-pixel columns.

In a third aspect, an embodiment of the present invention provides a display driving method, which is applied to the display device described in the second aspect, and the method includes the following steps:

The serial-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal;

The N first buffers store the first display data in a parallel format, wherein the nth level first buffer among the N first buffers is storing the first display of the M+1th row of pixels When the data is used, the first display data of the pixels in the M-th row is stored in the n+1-th level first buffer, wherein n is a positive integer less than N, and M is a positive integer;

The arithmetic unit generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is based on the first display data. Generated from pixel data of a plurality of pixels associated with the location;

The second buffer stores the second display data generated by the arithmetic unit and sends it to the digital-to-analog conversion module;

The digital-to-analog conversion module converts the second display data in the digital data signal format into the third display data in the analog data signal format.

In some embodiments, the N first buffers store the first display data converted into parallel format, including:

On the rising edge of the K th latch signal, store the first display data of the K th row in the L th level first register to the L+1 th level first register, where K is a positive integer and L is less than N positive integer of .

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

Between the rising edge of the K th release signal and the rising edge of the K+1 th latch signal, the arithmetic unit generates second display data according to the first display data stored in the N first buffers.

In some embodiments, the operator is turned on on the rising edge of the release signal and turned off on the rising edge of the latch signal.

In some embodiments, the plurality of pixels associated with the positions include a plurality of pixels located in adjacent rows and/or adjacent columns.

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

According to the pixel data of row X, column Y, the pixel data of row X, column Y+1, the pixel data of row X+1, column Y, and the pixel data of row X+1, Y+ The pixel data of column 1 generates pixel data of row X, column 2Y-1 and pixel data of row X, column 2Y in the second display data, where X and Y are positive integers.

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

In the first display data, the first difference between the pixel data of the Xth row and the Yth column and the pixel data of the Xth row and the Y+1th column is greater than the preset pixel difference threshold, and the X+1th row Yth In the case where the second difference between the pixel data of the column and the pixel data of the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, the Xth row and the Yth column of the first display data are set. The pixel data is used as the pixel data of the Xth row and the 2nd Y column in the second display data;

Under the condition that at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, the pixel data of the Xth row and the Yth column of the first display data is and the average value of the pixel data of the X-th row, Y+1 column, and the pixel data of the X-th row and the 2-Y column in the second display data.

In the embodiment of the present invention, by designing a multi-level first buffer, the first buffer is used to store the first display data of multiple sub-pixels, and then the display data stored in the first buffer is read by an arithmetic unit to process the display data , because the N first buffers are cascaded in sequence, the operator can read N lines of display data at the same time and generate a new line of display data according to multiple lines of display data, which improves the correlation between each pixel and surrounding pixels in the process of display data optimization. , which helps to improve the display effect. Meanwhile, the technical solution of this embodiment mainly relies on the improvement and realization of the source driving circuit, and the realization cost is relatively low, which helps to reduce the cost.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative labor.

1 is a schematic structural diagram of a source driver circuit in the related art;

2 is a schematic diagram of the corresponding relationship between display data and data channels in the related art;

Fig. 3 is a sequence diagram showing data transmission in the related art;

4 is a schematic diagram of the flow of display data in the related art;

5A is a schematic structural diagram of a source driving circuit in an embodiment of the present invention;

5B is a schematic structural diagram of a source driving circuit in an embodiment of the present invention;

FIG. 6 is a timing diagram showing data transmission in an embodiment of the present invention;

7 is a schematic diagram of the flow of display data in an embodiment of the present invention;

8 is a schematic diagram of generating second display data in an embodiment of the present invention;

9 is another schematic diagram of generating second display data in an embodiment of the present invention;

10a is another schematic diagram of generating second display data in an embodiment of the present invention;

10b is another schematic diagram of generating second display data in an embodiment of the present invention;

10c is another schematic diagram of generating second display data in an embodiment of the present invention;

10d is another schematic diagram of generating second display data in an embodiment of the present invention;

FIG. 11 is a schematic diagram of an image optimization result in an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the related art, a display device includes a display panel, a timing control board, and a source driver circuit (also called a source driver IC), wherein the display panel usually includes gate lines (or signal lines), data lines, and a plurality of pixels. The data lines The data signal used to provide each pixel can be, for example, the display gray scale of the pixel, and the gate line is usually used to provide the switching signal of the pixel, so that the control data line can transmit the data signal to each pixel.

Each pixel usually includes a plurality of sub-pixels of different colors. Exemplarily, a pixel may include three sub-pixels of red, green, and blue, or may include four sub-pixels of red, green, green, and blue, and may also include red and green. , blue, and white sub-pixels, etc., and the specific structure of each pixel is not further limited here.

Each pixel is usually arranged according to a certain rule. For example, if the physical resolution of the display panel is 2a*2b, it means that there are 2a pixels in each row, which is called the horizontal resolution, and there are 2b pixels in each column, which is called the horizontal resolution. It is the vertical resolution. Generally speaking, the sub-pixels are also arranged according to certain rules. For example, a certain column of sub-pixels may be all green sub-pixels, and the red sub-pixels and blue sub-pixels in another column of sub-pixels are alternately arranged.

The timing control board is used to provide timing control signals to realize timing control. The source driving circuit is used for converting the received digital data signal into an analog data signal capable of driving the pixels of the display panel to display images. In this way, under the control of the timing control signal and the converted analog data signal, the display panel can be controlled to display an image.

As shown in FIG. 1 , a source driver circuit in the related art includes a serial-parallel conversion module, a buffer, a digital-to-analog conversion module and a power amplifying module.

The timing control signal sends the display data to which the timing control signal is added to the source driver circuit. At this time, the display data is a serial data signal and is a digital data signal.

The serial-to-parallel conversion module converts the serial data signal sent by the timing control board into a parallel data signal, and then outputs it through the output channel. Here, the number of output channels is consistent with the number of sub-pixel columns of the input signal, and the output channels are in one-to-one correspondence with the data channels of the buffer, the data channels of the digital-to-analog conversion module, the data channels of the power amplifier module, and the sub-pixel columns of the display panel .

It should be understood that, in this embodiment, it can be understood that the buffer digital-to-analog conversion module and the like include multiple data channels, and each data channel can be understood as a circuit structure for processing the first display data of one sub-pixel.

The buffer is responsible for the storage and transfer of row data, and specifically includes a first-order buffer and a second-order buffer in this embodiment.

The digital-to-analog conversion module combines the digital data signal with the analog voltage to generate an analog data signal. The power amplification module is responsible for amplifying the power of the output signal, and the amplified display data is output to the display panel, which can drive the display panel to display images.

As shown in FIG. 2 , the number of sub-pixels included in each pixel is 3, and the number of display panel columns corresponding to each source driver IC is Y for exemplary illustration.

During implementation, the digital data signal of sub-pixel 1 of pixel 1 of a certain row transmitted from the timing control board is received by channel 1 of the serial-to-parallel conversion module to channel 1 of the first-level register, and then transmitted to channel 1 of the second-level register , the analog voltage is converted into an analog data signal at the channel 1 of the digital-to-analog conversion module, and finally sent to the sub-pixel 1 of the pixel 1 in the corresponding row of the display panel.

As shown in Figure 3, during the working process, in the T1 period, the source driver IC and the timing control board perform initial clock training to make their clock signals consistent.

After the initial clock training is completed, the timing control board sends each row of data information in turn.

The data information of a row generally includes the clock training information, control data information and display data of the row, wherein, regarding the sending and control process of the clock training information and the control data information, reference may be made to the related art, which is not further limited in this embodiment. In this embodiment, only the content related to the display data will be further described later.

Please continue to refer to Figure 3. The time for the timing control board to send a line of data is T2, which is also the time for the source driver IC to receive a line of data.

After the source driver IC recognizes that the transmission of the control data information is completed, it controls the serial-to-parallel conversion module to receive the display data, and the serial-to-parallel conversion module transmits the received data to the first-level buffer in real time for latching. After the display data of the line is received, the first latch signal is generated to send the data in the first-level register to the second-level register, and the first-level register begins to prepare to receive the display data of the second line.

It should be understood that each data channel of the buffer directly connected to the serial-parallel conversion module corresponds to the display data of one column of sub-pixels in the received display data, and each data channel of the buffer corresponding to different columns of sub-pixels receives the display data. Times are different.

In order to improve the processing effect of display data, a first buffer and a second buffer are provided.

Specifically, different data channels of the first buffer can receive display data at different times, and then save and process the data in the first buffer. After the first buffer sends the processed display data to the second buffer, The second buffer sends the display data to the display panel at the specified time, and at the same time, the first buffer can continue to receive the next line of display data, which reduces the interference in the process of saving and transmitting the processed data and the subsequently received data. possibility.

More specifically, the latch signal is generally located in the clock training phase of the next row. In this embodiment, the latch action is taken as an example to be triggered by the rising edge of the latch signal for illustration.

When the source driver IC generates the first latch signal, the first release signal is also generated internally, and the rising edge of the release signal is located before the rising edge of the first latch signal, that is, corresponding to the T4+T5 period, the release signal is The falling edge is located after the rising edge of the first latch signal, that is, corresponding to the T6+T7 period.

The falling edge of the release signal will turn on the connection switch between the power amplifier module and the display panel, releasing the data signal in the second-stage buffer to the display panel, and the rising edge will turn off the connection switch and stop the output, or connect the display panel to A fixed intermediate voltage is connected for charge sharing, usually the intermediate voltage is set to half of the maximum analog voltage used by the source driver IC.

That is to say, at the end of the T5 period, the rising edge of the latch signal triggers the latch operation. At the end of the T6 period, the falling edge of the latch signal ends the latch operation, completing the latching of the display data. Next, at T7 When the period ends, the data signal in the second-stage buffer is released to the display panel under the control of the release signal, so as to drive the display panel to display a picture.

Therefore, the falling edge of the first release signal releases the display data signal of the first line in the second-level register to the first line of the display panel to display it; the rising edge of the second release signal closes the display of the first line Output of the data signal; the time from the falling edge of the first release signal to the rising edge of the second release signal is the period of T8+T9, which is the time that the analog voltage of the display data of the first row is maintained on the data line of the display panel.

In the period T10, the processing of the display data of the next line is started referring to the above process.

As shown in FIG. 4 , according to the above process, each row displays the flow of data among the modules in the source driver IC. Here, each module refers to the above-mentioned serial-parallel conversion module, buffer, digital-to-analog conversion module, and power amplifier module.

Embodiments of the present invention provide a source driving circuit.

As shown in FIG. 5A , in one embodiment, the source driver circuit includes a serial-parallel conversion module, N first buffers, a second buffer, an operator, and a digital-to-analog conversion module. Specifically, this embodiment The N first registers in FIG. 5A are the first to Nth order registers shown in FIG. 5A , and the second register is the N+1th order register.

The source driving circuit may further include a power amplifying module. In this embodiment, N is an integer greater than 1, and may specifically be different values such as 2, 3, 4, . . .

In this embodiment, the N first buffers are cascaded in sequence, and the output terminal of the serial-to-parallel conversion module is connected to the input terminal of the first-level first buffer among the N first buffers. It should be understood that this implementation The x-th stage first register in the example refers to the x-th stage register shown in FIG. 5A . The outputs of the N first registers are all connected to the input of the arithmetic unit, the output of the arithmetic unit is connected to the input of the second register, and the output of the second register is connected to the input of the digital-to-analog conversion module.

As shown in FIG. 5B , in this embodiment, N is equal to 2 for exemplary illustration.

In this embodiment, the two first registers are specifically the first-level register and the second-level register shown in FIG. 5B , and the second register is specifically the third-level register shown in FIG. 5B .

The output ends of the first-order register and the second-order register are both connected to the input end of the arithmetic unit, and the output end of the arithmetic unit is connected to the third-order register.

In some embodiments, the number of data channels in the first buffer may be equal to the number of data channels in the second buffer. In this case, the operator reads the pixel data associated with each pixel and performs optimization processing to obtain the optimized pixel data. Pixel data, which can optimize the display effect.

In other embodiments, the number of data channels of the first buffer is smaller than the number of data channels of the second buffer.

In this embodiment, compared with the first buffer, the second buffer has a larger number of data channels, so that the operator can obtain more columns of display data based on the display data in the first buffer, so as to realize the The super-resolution processing of the display data can improve the display effect.

Exemplarily, if the line resolution of the display panel is 2a, that is, each line includes 2a pixels, and each pixel includes three subpixels of different colors, then each line includes a total of 6a subpixels, and the data channel of the second buffer The number should be 6a, and the number of channels of the two first buffers should both be less than 6a, for example, it may be 3a, but not limited thereto. Correspondingly, the number of output channels of the serial-parallel conversion module is 3a, the data channel of the arithmetic unit is 6a, and the data channel of the digital-to-analog conversion module is 6a.

An embodiment of the present invention provides a display device, including a display panel and any one of the above source driver circuits, the source driver circuit is used to drive the display panel to display images, the display panel includes a plurality of sub-pixel columns, and the second buffer The data channels correspond to the sub-pixel columns one-to-one. It should be understood that the display device can also control the timing control board, etc., which will not be further limited and described here.

An embodiment of the present invention provides a display driving method, which is applied to the above-mentioned display device.

In one embodiment, the display driving method includes the following steps:

The serial-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal;

the N first buffers store the first display data in a parallel format;

The arithmetic unit generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is based on the first display data. Generated from pixel data of a plurality of pixels associated with the location;

The second buffer stores the second display data generated by the arithmetic unit and sends it to the digital-to-analog conversion module;

The digital-to-analog conversion module converts the second display data in the digital data signal format into the third display data in the analog data signal format.

It should be understood that, in the technical solution of this embodiment, the serial-parallel conversion module obtains the serial first display data, and then converts it into the parallel first display data. In modules such as buffers, arithmetic units, and digital-to-analog conversion modules, the display data is processed in parallel in each data channel, and the display data in the same column is processed sequentially in the data channels of each module.

In the technical solution of this embodiment, after the conversion is completed by the serial-parallel conversion module, it is input to the N first registers.

In this embodiment, when storing the first display data of the pixels in the M+1th row, the nth-level first buffer among the N first buffers stores the first display data of the pixels in the Mth row to the n+th row. Level 1 first buffer, wherein n is a positive integer smaller than N, and M is a positive integer.

It should be understood that, in this embodiment, a row of pixel data actually includes data of a plurality of sub-pixels included in each pixel in the row of pixels.

Exemplarily, when N is equal to 2, the first-level first buffer (ie, the first-level buffer shown in FIG. 5B ) first acquires the display data of the first line in the first display data, and then the first level The first register saves the display data of the first line to the second-level first register (ie, the second-level register shown in FIG. 5B ), and then the first-level first register obtains the display data of the second line. At this time, The arithmetic unit can simultaneously acquire the display data of the first line and the display data of the second line in the first display data from the first buffer of the first level and the first buffer of the second level.

The arithmetic unit performs processing according to the read display data of the first line and the display data of the second line, and obtains the second display data.

It should be understood that, in the embodiment shown in FIG. 1, only one line of display data can be read and processed. Compared with the embodiment shown in FIG. 1, this embodiment can read multiple lines of display data at the same time. For sub-pixels, not only the display data of the target sub-pixel can be obtained, but also the display data of other sub-pixels associated with its position, so that the display data can be optimized according to these associated sub-pixels.

It should be understood that the sub-pixel associated with the target sub-pixel position refers to the pixel corresponding to the target sub-pixel among the pixels associated with the target pixel position including the target sub-pixel. Exemplarily, if the target sub-pixel is a red sub-pixel, the associated sub-pixel may be a red sub-pixel in pixels adjacent to the red sub-pixel.

In this way, each sub-pixel in a pixel can be optimized according to the display data of the sub-pixel associated with the sub-pixel position, and it can also be understood that the pixel data of each pixel is based on the display data of the pixel associated with the pixel position. optimized.

In some embodiments, the plurality of pixels associated with the positions include a plurality of pixels located in adjacent rows and/or adjacent columns. That is to say, in this embodiment, the display effect can be optimized according to the pixels of adjacent rows or adjacent columns.

The second display data calculated and generated is first stored in the second register (ie, the third-level register shown in FIG. 5B ), and then sent to the subsequent digital-to-analog conversion module by the second register, and the format is a digital data signal. The second display data is converted into third display data whose format is an analog data signal, and the third display data can be subsequently processed as needed, such as power amplification, and then the display panel is driven to display images.

In this way, the embodiment of the present invention designs a multi-level first buffer, uses the first buffer to store the first display data of a plurality of sub-pixels, and then reads the display data stored in the first buffer through an arithmetic unit, so as to compare the display data For processing, since the N first buffers are cascaded in sequence, the operator can read N lines of display data at the same time and generate a new line of display data according to multiple lines of display data, which improves the display data optimization process between each pixel and surrounding pixels. Correlation helps to improve the display effect. Meanwhile, the technical solution of this embodiment mainly relies on the improvement and realization of the source driving circuit, and the realization cost is relatively low, which helps to reduce the cost.

In some embodiments, the N first buffers store the first display data converted into parallel format, including:

On the rising edge of the K th latch signal, store the first display data of the K th row in the L th level first register to the L+1 th level first register, where K is a positive integer and L is less than N positive integer of .

Exemplarily, when K is equal to 1 and L is equal to 1, on the rising edge of the first latch signal, the first display data of the first row in the first buffer of the first level is stored to the first display data of the second level. in the buffer.

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

Between the rising edge of the K th release signal and the rising edge of the K+1 th latch signal, the arithmetic unit generates second display data according to the first display data stored in the N first buffers.

When generating the second display data, between the rising edge of the first release signal and the rising edge of the second latch signal, the operator obtains the first display data in the N first buffer areas to generate the second display data.

In some embodiments, the operator is turned on on the rising edge of the release signal and turned off on the rising edge of the latch signal.

As shown in FIG. 6 and FIG. 7 , in the technical solution of this embodiment, the phase of the release signal corresponding to one row of display data corresponds to the latch signal timing of the next row. On the rising edge of the release signal, in addition to closing the connection between the power amplifier module and the display panel, the operation function of the arithmetic unit is also turned on, and on the rising edge of the latch signal, the data in the first register of the first level is sent to the next level the first register and turn off the arithmetic unit.

As shown in FIG. 6 and FIG. 7 , specifically, at the rising edge of a latch signal, the display data of the first line in the first buffer of the first level is stored in the first buffer of the second level, and the first line of the first buffer of the first level is stored. A buffer starts to prepare to store the display data of the second line. By the first rising edge of the release signal, that is, in the period of T5+T6, the first-level first buffer has already stored most of the display data of the second line.

Next, at the first rising edge of the release signal, the operator starts to perform operation on the first display data in the first-level first buffer and the second-level first buffer to obtain second display data.

The generated second display data is directly latched into the second register, and before the rising edge of the second latch signal, the entire operation and storage of the first line of display data and the second line of display data are completed, that is, in the T7 period. All operations and storage of the data displayed on the first line and the data displayed on the second line are completed within the system.

In the T7 period, the connection between the power amplification module and the display panel is also closed. Specifically, the external output of the third-stage buffer can be turned off, or the display panel can be connected to a certain fixed intermediate voltage for charge sharing.

As shown in Figure 7, and so on, the rising edge of the second latch signal causes the second-level first buffer to latch the display data of the second line sent by the first-level first buffer, and the first-level first buffer Prepare to store the third row of data, and turn off the arithmetic function of the calculator;

The falling edge of the first release signal will send the new display data of the first line stored in the third-level register to the display panel; the rising edge of the second release signal will close the data output of the third-level register and start the operation at the same time device.

It should be understood that, for the last column of pixels, since there is no next column of pixels, the processing process can be omitted, and the impact on the display effect can be ignored.

It is exemplified by performing super-division processing on the first display data and N is equal to 2. Specifically, when N is equal to 2, two adjacent pixels are taken as a group, and each pixel includes three sub-pixels. In this way, The first display data includes the display data of the 2a columns of pixels, that is, the display data of the 6a columns of sub-pixels, and the generated second display data actually includes the display data of the 12a columns of sub-pixels.

In this embodiment, the display data of a new column of sub-pixels is generated from the display data of two adjacent columns of sub-pixels in the first display data, and the generated new column of sub-pixels is located between the above-mentioned two adjacent columns of sub-pixels. The number of sub-pixel rows of the obtained second display data is the same as that of the first display data, and the number of sub-pixel columns of the obtained second display data is twice that of the first display data. Correspondingly, the number of pixel rows of the second display data is Also the same as the first display data, the number of pixel columns is twice that of the first display data.

It should be understood that, for the last column of sub-pixels in the first display data, since there is no next column of sub-pixels, it is impossible to obtain a new column of sub-pixels in the second display data by referring to the above method. However, other methods, such as The last column of sub-pixels in the second display data is obtained by directly copying the pixels in the previous column, calculating interpolation, or the like.

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

According to the pixel data of row X, column Y, the pixel data of row X, column Y+1, the pixel data of row X+1, column Y, and the pixel data of row X+1, Y+ The pixel data of column 1 generates pixel data of row X, column 2Y-1 and pixel data of row X, column 2Y in the second display data, where X and Y are positive integers.

As shown in FIG. 8 and FIG. 9 , exemplarily, in this embodiment, the data in the first-level buffer channel 1, the data in the second-level buffer channel 1, and the data in the first-level buffer channel 4 are used. , The data in the second-stage buffer channel 4 is operated, and the generated data is input to the third-stage buffer channel 1 and channel 4. Use the data in the first-level register channel 4, the data in the second-level register channel 4, the data in the first-level register channel 7, and the data in the second-level register channel 7 to perform operations, and the generated data input To the third level buffer channel 7 and channel 10. By analogy, the display data of each data channel can be obtained.

As shown in FIG. 8 , the data in the first-level buffer channel 1, the data in the second-level buffer channel 1, the data in the first-level buffer channel 4, and the data in the second-level buffer channel 4 are actually Corresponding to the display data of the corresponding sub-pixels in the adjacent four pixels, in this way, the display data input to the third-stage buffer channel 7 and channel 10 obtained according to the four display data can actually be understood as the second Display data of corresponding sub-pixels in two adjacent pixels in the display data.

By analogy, the display data of two adjacent sub-pixels in the second display data can be calculated from the display data of four adjacent sub-pixels in the first display data, since each pixel is composed of multiple sub-pixels, as shown in FIG. 9 . It can be understood from the pixel level that the display data of two adjacent pixels in the second display data are determined by the display data of four adjacent pixels in the first display data.

It should be understood that the last column of pixels required for the second display data may be omitted, or may be generated with reference to the last column of pixels in the first display data, and the influence on the display effect can be ignored.

As shown in FIG. 9 , in this embodiment, two levels of first buffers are set, wherein the first level of the first buffer stores the display data of pixel 2-1 and pixel 2-2, and the second level of buffer stores the display data of pixel 2-1 and pixel 2-2. Stored in is the display data of pixel 1-1 and pixel 1-2.

During implementation, the display data of these four pixels is called, and the pixel 1-1* is generated as the display data of the first row and the first column in the second display data, and the pixel 1-1** is generated as the first row in the second display data. Display data in the second column.

Similarly, call pixel 1-2, pixel 1-3, pixel 2-2 and pixel 2-3 in the first display data to generate pixel 1-2* as the first row, third column and pixel 1 in the second display data -2** as the display data of the first row and the fourth column in the second display data. By analogy, the second display data can be obtained.

It should be understood that the above situation is only for the two first buffers set in this embodiment. If three first buffers are set, the display data of three rows of pixels can be stored at the same time, and the operator can pass the three rows of pixels. of the first display data to generate the second display data.

During implementation, different numbers of first buffers may be set as required to achieve image optimization.

Obviously, more data channels can be set to call more columns of display data as needed. For example, three or more columns of first display data can be called to generate second display data by referring to the above process.

In some embodiments, the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, including:

In the first display data, the first difference between the pixel data of the Xth row and the Yth column and the pixel data of the Xth row and the Y+1th column is greater than the preset pixel difference threshold, and the X+1th row Yth In the case where the second difference between the pixel data of the column and the pixel data of the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, the Xth row and the Yth column of the first display data are set. The pixel data is used as the pixel data of the Xth row and the 2nd Y column in the second display data;

Under the condition that at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, the pixel data of the Xth row and the Yth column of the first display data is and the average value of the pixel data of the X-th row, Y+1 column, and the pixel data of the X-th row and the 2-Y column in the second display data.

In one embodiment, the preset pixel difference threshold is set to 70. Obviously, the preset pixel threshold can be adjusted as required, which is not limited here.

The difference value of the pixel data is actually determined according to the pixel value of each sub-pixel included in the pixel.

As shown in Figures 10a to 10d, each sub-pixel in the pixels of the first row can be processed in the following manner.

As shown in Figure 10a, in two adjacent rows, if the difference between the pixel values of the sub-pixels in the two columns is greater than 70, the pixel values of the sub-pixels in the first column are copied to the newly generated column 1* to keep the different regions image with high contrast.

As shown in Figure 10b, in two adjacent rows, if the difference between the pixel values of the two columns of sub-pixels is less than 70, then calculate the mean of the pixel values of the two columns of sub-pixels in the first row of pixels as the newly generated first row. 1*The pixel value of the pixel in the column, so that the image transition can be made smoother.

As shown in Figure 10c and Figure 10d, in two adjacent rows, if the difference between the pixel values of the sub-pixels in the adjacent two columns of the first row is not greater than 70, then regardless of the relationship between the pixel values of the sub-pixels in the adjacent two columns of the second row However, the average value of the pixel values of the two columns of sub-pixels in the first row of pixels is used as the pixel value of the 1*column sub-pixels newly generated in the first row, so that the image transition can be made smoother.

For the last row of pixels, since there is no next row of pixels, the average value of the pixel values of two adjacent columns can be used, or the pixel value of the previous row can be copied.

As shown in Figure 11, through the above processing method, the contrast can be maintained for areas with high pixel value differences, and for areas with relatively low pixel value differences, the transition effect of different areas can be improved, making the transition smoother.

The technical solution of this embodiment realizes the super-resolution of the horizontal resolution of the display signal, and improves the optimization effect of the display screen. When performing data expansion operations, adjacent column pixel data and adjacent row data can be included to optimize the expansion effect and improve the display quality. Compared with the conventional design, the total number of effective channels of each register in the technical solution of the embodiment of the present invention does not increase, which reduces the cost increase. The increase of the control signal will not increase the difficulty of control and help to control the cost.

It should be noted that it should be understood that the division of the above modules is only a division of logical functions, and in actual implementation, all or part of them may be integrated into a physical entity, or may be physically separated. And these modules can all be implemented in the form of software calling through processing elements; they can also all be implemented in hardware; some modules can also be implemented in the form of calling software through processing elements, and some modules can be implemented in hardware. For example, the determination module may be a separately established processing element, or may be integrated into a certain chip of the above-mentioned device to be implemented, in addition, it may also be stored in the memory of the above-mentioned device in the form of program code, and a certain processing element of the above-mentioned device may Call and execute the function of the above determined module. The implementation of other modules is similar. In addition, all or part of these modules can be integrated together, and can also be implemented independently. The processing element described here may be an integrated circuit with signal processing capability. In the implementation process, each step of the above-mentioned method or each of the above-mentioned modules can be completed by an integrated logic circuit of hardware in the processor element or an instruction in the form of software.

For example, each module, unit, sub-unit or sub-module may be one or more integrated circuits configured to implement the above method, such as: one or more Application Specific Integrated Circuit (ASIC), or, one or more A microprocessor (digital signal processor, DSP), or one or more field programmable gate arrays (Field Programmable Gate Array, FPGA), etc. For another example, when a certain module above is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processors that can invoke program codes. For another example, these modules can be integrated together and implemented in the form of a system-on-a-chip (SOC).

The above are preferred implementations of the embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and Retouching should also be regarded as the protection scope of the present invention.

Claims (10)

1. A source driver circuit, characterized in that, comprising a serial-parallel conversion module, N first buffers, a second buffer, an operator and a digital-to-analog conversion module, wherein N is an integer greater than 1: the N first buffers are cascaded in sequence; The output end of the serial-to-parallel conversion module is connected to the input end of the first-stage first buffer in the N first buffers; The output ends of the N first buffers are all connected with the input ends of the arithmetic unit; The output end of the arithmetic unit is connected to the input end of the second buffer; The output end of the second buffer is connected to the input end of the digital-to-analog conversion module. 2 . The source driving circuit of claim 1 , wherein the number of data channels of the first buffer is smaller than the number of data channels of the second buffer. 3 . 3. A display device, comprising a display panel and the source driver circuit according to claim 1 or 2, the source driver circuit being used to drive the display panel to display an image, the display panel comprising a plurality of There are sub-pixel columns, and the data channels of the second buffer are in one-to-one correspondence with the sub-pixel columns. 4. A display driving method, characterized in that, applied to the display device according to claim 3, the method comprises the following steps: The serial-parallel conversion module converts the input first display data from a serial format to a parallel format, wherein the first display data is a digital data signal; The N first buffers store the first display data in a parallel format, wherein the nth level first buffer among the N first buffers is storing the first display of the M+1th row of pixels When the data is used, the first display data of the pixels in the M-th row is stored in the n+1-th level first buffer, wherein n is a positive integer less than N, and M is a positive integer; The arithmetic unit generates second display data according to the first display data stored in the N first buffers, wherein the pixel data of each pixel in the second display data is based on the first display data. Generated from pixel data of a plurality of pixels associated with the location; The second buffer stores the second display data generated by the arithmetic unit and sends it to the digital-to-analog conversion module; The digital-to-analog conversion module converts the second display data in the digital data signal format into the third display data in the analog data signal format. 5. The method according to claim 4, wherein the N first buffers store the first display data converted into a parallel format, comprising: On the rising edge of the K th latch signal, store the first display data of the K th row in the L th level first register to the L+1 th level first register, where K is a positive integer and L is less than N positive integer of . 6. The method according to claim 5, wherein the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, comprising: Between the rising edge of the K th release signal and the rising edge of the K+1 th latch signal, the arithmetic unit generates second display data according to the first display data stored in the N first buffers. 7. The method according to claim 5 or 6, wherein the arithmetic unit is turned on at the rising edge of the release signal, and turned off at the rising edge of the latch signal. 8. The method according to any one of claims 4, wherein the plurality of pixels associated with the positions comprise a plurality of pixels located in adjacent rows and/or adjacent columns. 9. The method according to claim 8, wherein the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, comprising: According to the pixel data of row X, column Y, the pixel data of row X, column Y+1, the pixel data of row X+1, column Y, and the pixel data of row X+1, Y+ The pixel data of column 1 generates pixel data of row X, column 2Y-1 and pixel data of row X, column 2Y in the second display data, where X and Y are positive integers. 10. The method according to claim 9, wherein the arithmetic unit generates the second display data according to the first display data stored in the N first buffers, comprising: In the first display data, the first difference between the pixel data of the Xth row and the Yth column and the pixel data of the Xth row and the Y+1th column is greater than the preset pixel difference threshold, and the X+1th row Yth In the case where the second difference between the pixel data of the column and the pixel data of the X+1th row and the Y+1th column is greater than the preset pixel difference threshold, the Xth row and the Yth column of the first display data are set. The pixel data is used as the pixel data of the Xth row and the 2nd Y column in the second display data; Under the condition that at least one of the first difference and the second difference is not greater than the preset pixel difference threshold, the pixel data of the Xth row and the Yth column of the first display data is and the average value of the pixel data of the X-th row, Y+1 column, and the pixel data of the X-th row and the 2-Y column in the second display data.

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