CN114822341A - display device - Google Patents

Abstract

The invention provides a display device. The display device comprises a display panel, a grid driver and a source driver. The display panel comprises a plurality of sub-pixels which are arranged into a plurality of rows and a plurality of columns, wherein three first sub-pixels have different colors and form a pixel, and the first sub-pixels are arranged on the same row. The gate driver is electrically connected to a plurality of gate lines, wherein the number of the gate lines is less than the number of the rows, each gate line corresponds to at least two rows, and each gate line is electrically connected to at least two sub-pixels in each row. The source driver is electrically connected to the plurality of data lines, the number of the data lines is greater than the number of the rows, and each row corresponds to at least two data lines.

Description

display device

technical field

The present disclosure relates to a display device that can strike a balance between charging time and cost.

Background technique

A typical display device has a gate driver, a source driver and a plurality of sub-pixels. The gate driver is electrically connected to the sub-pixels through gate lines, and the source driver is electrically connected to the sub-pixels through data lines. During the display period of a picture, the gate driver turns on the thin film transistors in the sub-pixels row by row through the gate line, and the source driver transmits gray-scale signals to the sub-pixels through the data lines, thereby charging the capacitors in the sub-pixels . As the resolution of the display device increases, the time for the sub-pixels to be charged becomes shorter. On the other hand, the increase of data lines leads to the need to configure more source drivers, which increases the cost. How to strike a balance between charging time and cost is a concern of those skilled in the art.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a display device to solve at least one of the above problems.

Embodiments of the present invention provide a display device including a display panel, a gate driver and a source driver. The display panel includes a plurality of sub-pixels arranged in a plurality of rows and columns, wherein three first sub-pixels have different colors and form one pixel, and the first sub-pixels are arranged on the same row. The gate driver is electrically connected to a plurality of gate lines, wherein the number of gate lines is less than the number of columns, each gate line corresponds to at least two columns, and each gate line is electrically connected to at least two columns in each row. sub-pixels. The source driver is electrically connected to a plurality of data lines, the number of the data lines is greater than the number of rows, and each row corresponds to at least two data lines.

In some embodiments, the two first sub-pixels are electrically connected to the same gate line and are respectively electrically connected to two different data lines. When the gate driver turns on the two first sub-pixels, the source driver transmits two gray-scale signals to the two first sub-pixels through two different data lines respectively.

In some embodiments, the first sub-pixels are electrically connected to the same gate line and are respectively electrically connected to three different data lines. When the gate driver turns on the first sub-pixel, the source driver transmits three gray-scale signals to the first sub-pixel through three different data lines respectively.

In some embodiments, the first sub-pixel and the second sub-pixel are arranged in the same row, and the first sub-pixel and the second sub-pixel are electrically connected to the same one of the gate lines and are electrically connected to each other. to four different data lines in the data lines. When the gate driver turns on the first sub-pixel and the second sub-pixel, the source driver transmits four gray-scale signals to the first sub-pixel and the second sub-pixel respectively through four different data lines.

In some embodiments, every n sub-pixels in each row are electrically connected to the same gate line, where n is a positive integer greater than or equal to 2.

In some embodiments, the above-mentioned n sub-pixels are electrically connected to different n data lines among the data lines.

The beneficial effect of the present invention lies in that, the present invention achieves that through "the display panel includes a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns, wherein three first sub-pixels have different colors and form one pixel, and the first sub-pixels are arranged in On the same row, the gate driver is electrically connected to a plurality of gate lines, wherein the number of gate lines is less than the number of columns, each gate line corresponds to at least two columns, and each gate line is electrically connected to each At least two sub-pixels in a row. The source driver is electrically connected to a plurality of data lines, the number of data lines is greater than the number of rows, and each row corresponds to at least two data lines" design, so that the number of source drivers can be strike the right balance between (i.e. cost) and charging time

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a schematic diagram illustrating a display device according to an embodiment.

FIG. 2 is a schematic diagram illustrating the connection of a plurality of sub-pixels according to an embodiment.

FIG. 3 is a signal timing diagram according to an embodiment.

FIG. 4 is a schematic diagram illustrating a display device according to an embodiment.

FIG. 5 is a schematic diagram illustrating the connection of a plurality of sub-pixels according to an embodiment.

FIG. 6 is a signal timing diagram according to an embodiment.

FIG. 7 is a schematic diagram illustrating a display device according to an embodiment.

FIG. 8 is a schematic diagram illustrating the connection of a plurality of sub-pixels according to an embodiment.

FIG. 9 is a signal timing diagram according to an embodiment.

The reference numbers are as follows:

100: Display device

110: Gate driver

120: source driver

130: Display panel

131～134, 141～144: Subpixels

S1～S12: data line

G1～G6: Gate lines

R1～R12: Column

C1～C6: row

M1～M4: thin film transistor

R: red

G: green

B: blue

310,320,610,620,910,920: Time interval

Detailed ways

Regarding the "first", "second" and the like used herein, it does not mean a particular order or order, but only for distinguishing elements or operations described in the same technical terms.

FIG. 1 is a schematic diagram illustrating a display device according to an embodiment. Referring to FIG. 1 , the display device 100 includes a gate driver 110 , a source driver 120 and a display panel 130 . The display panel 130 includes a plurality of sub-pixels, and the sub-pixels are arranged in a plurality of rows C1 - C6 and a plurality of columns R1 - R12 . Each sub-pixel has a specific color, "R", "G" and "B" in FIG. 1 represent red, green and blue, respectively. In this embodiment, each pixel includes three sub-pixels with different colors, and the three sub-pixels are arranged vertically, ie, arranged on the same row. For example, the sub-pixels 131-133 form a pixel and are arranged vertically, while the sub-pixel 134 is located in the same row but belongs to another pixel. By such arrangement, the number of rows can be reduced and the number of columns can be increased.

The gate driver 110 is electrically connected to the gate lines G1-G6, the number of the gate lines G1-G6 is smaller than the number of the columns R1-R12, and each gate line corresponds to two columns, for example, the gate line G1 corresponds to Columns R1, R2, gate line G2 corresponds to columns R3, R4, and so on. In this embodiment, each gate line is electrically connected to at least two sub-pixels in each row. For example, the gate line G1 is electrically connected to the sub-pixels 131 and 132, and the gate line G2 is electrically connected to the sub-pixels 131 and 132. Sub-pixel 133 and sub-pixel 134, and so on.

The source driver 120 is electrically connected to the data lines S1-S12. The number of the data lines S1-S12 is greater than the number of the rows C1-C6, and each row corresponds to two data lines. For example, the row C1 corresponds to the data lines S1, S2, row C2 corresponds to data lines S3, S4, and so on. The two data lines corresponding to the same row are electrically connected to the sub-pixels alternately. For example, the data line S1 is electrically connected to the sub-pixel 131 and the sub-pixel 133, and the data line S2 is electrically connected to the sub-pixel 132 and the sub-pixel 134. .

It is worth noting that the gate lines G1-G6 are also electrically connected to the sub-pixels on the rows C2-C6 through the dotted lines in the figure. For example, gate line G1 is also electrically connected to sub-pixels "R" and "G" on rows C2-C6 and columns R1, R2. For the specific connection relationship, please refer to FIG. 2 . Here, the sub-pixels on the rows C1 and C2 and the columns R1 to R4 are used as examples. Each sub-pixel has a thin film transistor, and the gate line G1 is electrically connected to the gates of the thin film transistors M1 ˜ M4 . The drain of each thin film transistor is electrically connected to the pixel electrode in the corresponding sub-pixel. The source of the thin film transistor M1 is electrically connected to the data line S1, the source of the thin film transistor M2 is electrically connected to the data line S3, the source of the thin film transistor M3 is electrically connected to the data line S2, and the source of the thin film transistor M4 is electrically connected Connect to data line S4. In other words, the sub-pixels 131 and 132 are electrically connected to the same gate line G1 but are electrically connected to different data lines S1 and S2 respectively, and the sub-pixels 141 and 142 are electrically connected to the same gate line G1 but are respectively electrically connected to different data lines S1 and S2. It is electrically connected to different data lines S3 and S4.

During the period of displaying a picture, the gate driver 110 will turn on the corresponding thin film transistor through the gate line, which is also called "turning on the sub-pixel", and the source driver 120 will transmit the grayscale signal to the corresponding TFT through the data line. In the sub-pixels, the pixel electrode and the common electrode in each sub-pixel form a capacitor, and the capacitor is charged according to the gray-scale signal. In this embodiment, each data line has a buffer, and the source driver 120 temporarily stores the gray-scale signal in the corresponding buffer before transmitting the gray-scale signal. When the corresponding sub-pixel is turned on, these The grayscale signal will be transmitted to the data line. Specifically, please refer to FIG. 2 and FIG. 3 , in the time interval 310 , the source driver 120 temporarily stores the gray-scale signal to be transmitted to the sub-pixel 131 in the buffer of the data line S1 , and transmits the gray-scale signal to be transmitted to the sub-pixel 131 temporarily in the buffer of the data line S1 . The grayscale signals of the pixel 132 are temporarily stored in the buffer of the data line S2, and the grayscale signals to be transmitted to the sub-pixels 141 and 142 are also temporarily stored in the buffers of the data lines S3 and S4, which are not shown in FIG. 3 for simplicity. Out data lines S3 and S4. During the time interval 320, the gate line G1 is at a high level to turn on the thin film transistors M1-M4. At this time, the gray-scale signals in the buffer are transmitted to the sub-pixels 131, 132, 141 and 131 through the data lines S1-S4, respectively. 142. Also in the time interval 320, the grayscale signals to be transmitted to the sub-pixels 133, 134, 143, and 144 are temporarily stored in the buffer, and the gate line G2 is at a high level in the next time interval, and so on.

FIG. 4 is a schematic diagram illustrating a display device according to an embodiment. In the embodiment of FIG. 4, each gate line is electrically connected to three sub-pixels in the same row. For example, the sub-pixels 131-133 are electrically connected to the same gate line G1 and are electrically connected to the data lines S1-S3, respectively. Referring to FIG. 5 and FIG. 6 , the gate line G1 is electrically connected to the gates of the thin film transistors in the sub-pixels 131 - 133 and 141 - 143 . In the time interval 610, the source driver 120 temporarily stores the gray-scale signals to be transmitted to the sub-pixels 131-133 in the buffers of the data lines S1-S3, and temporarily stores the gray-scale signals to be transmitted to the sub-pixels 141-143 in the buffers of the data lines S1-S3. in the buffers of the data lines S4 to S6. In the time interval 620, the gate line G1 is at a high level, and the above-mentioned grayscale signals are respectively transmitted to the sub-pixels 131-133 through the data lines S1-S3, and respectively transmitted to the sub-pixels 141-143 through the data lines S4-S6. .

FIG. 7 is a schematic diagram illustrating a display device according to an embodiment. In the embodiment of FIG. 7, each gate line is electrically connected to four sub-pixels in the same row. For example, the sub-pixels 131-134 are electrically connected to the same gate line G1 and are electrically connected to the data lines S1-S4, respectively. Referring to FIG. 8 and FIG. 9 , the gate line G1 is electrically connected to the gates of the thin film transistors in the sub-pixels 131 - 134 and 141 - 144 . In the time interval 910, the source driver 120 temporarily stores the gray-scale signals to be transmitted to the sub-pixels 131-134 in the buffers of the data lines S1-S3, and temporarily stores the gray-scale signals to be transmitted to the sub-pixels 141-144 in data in the buffers of lines S4 to S8. In the time interval 920, the gate line G1 is at a high level, and the above-mentioned grayscale signals are respectively transmitted to the sub-pixels 131-134 through the data lines S1-S4, and respectively transmitted to the sub-pixels 141-144 through the data lines S5-S8.

From another perspective, in the above-mentioned embodiment, every n sub-pixels in each row are electrically connected to the same gate line and electrically connected to n different data lines, where n is greater than or equal to 2 A positive integer of , the n sub-pixels are turned on and charged at the same time. In the embodiments of FIGS. 1 to 3 , n=2; in the embodiments of FIGS. 4 to 6 , n=3; and in the embodiments of FIGS. 7 to 9 , n=4. In other embodiments, the positive integer n may also be greater than 4. Notably, time interval 910 is greater than time interval 610 , and time interval 610 is greater than time interval 310 .

Both designs are combined in this disclosure. The first design is to vertically arrange three sub-pixels of a pixel. At this time, the number of data lines will become 1/3 times the original, and the charging time of each sub-pixel will become 1/3 times the original. The second design is that every n sub-pixels in a row are electrically connected to the same gate line and are electrically connected to n different data lines. At this time, the number of data lines will become n times the original, while the The charging time of the pixel will become n times the original. Therefore, combining the above two designs, the number of data lines will become n/3 times the original, and the charging time of each sub-pixel will become n/3 times the original. For example, assuming that the resolution of the display panel 130 is 7680×4320, the display time of each frame is 1/60 of a second, each source driver 120 can provide 960 data lines, and in one pixel of a conventional display panel, The three sub-pixels are arranged horizontally, so a total of 7680×3=23040 data lines are required, a total of 23040÷960=24 source drivers are required, and the charging time of each subpixel is 1÷60÷4320=3.858 microseconds. When the first design above is adopted, a total of 7680 data lines and 7680÷960=8 source drivers are required, and the charging time of each sub-pixel is 1÷60÷(4320×3)=1.286 microseconds. Although the first design can change the source driver and charging time, it is not flexible. When the above two designs are adopted, a total of 7680×n data lines and 8×n source drivers are required, and the charging time of each sub-pixel is 1.286×n microseconds. Different positive integers n can be designed in different products, so that an appropriate balance can be achieved between the number of source drivers (ie, cost) and charging time.

The above-mentioned display panel 130 can be a fringe field switching (FFS) panel, an in-plane switching (IPS) panel, a twisted nematic (TN) panel, a vertical alignment (vertical alignment) VA) panels or other suitable panels.

Although the present invention has been disclosed by the above examples, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention as defined in the appended claims.

Claims (6)

1. A display device comprising: A display panel includes a plurality of sub-pixels arranged in a plurality of rows and columns, three first sub-pixels in the plurality of sub-pixels have different colors and form a pixel, and a plurality of the first sub-pixels arranged on the same one of a plurality of said lines; a gate driver electrically connected to a plurality of gate lines, wherein the number of the plurality of gate lines is less than the number of the plurality of the columns, and each of the gate lines corresponds to at least one of the plurality of the columns Two, each gate line is electrically connected to at least two of the sub-pixels in each row; and A source driver electrically connected to a plurality of data lines, wherein the number of the plurality of data lines is greater than the number of the plurality of the rows, and each row corresponds to at least two of the plurality of the data lines. 2 . The display device of claim 1 , wherein two of the plurality of first sub-pixels are electrically connected to the same gate line among the plurality of gate lines and are respectively electrically connected to the plurality of the plurality of gate lines. 3 . two different data lines in the above data lines, During the period when the gate driver turns on two of the first sub-pixels, the source driver transmits two gray-scale signals to the first sub-pixels through the different two data lines respectively. The two of them. 3 . The display device of claim 1 , wherein the plurality of first sub-pixels are electrically connected to the same gate line among the plurality of gate lines and are respectively electrically connected to the plurality of data lines. 4 . Three different data lines, When the gate driver turns on the plurality of first sub-pixels, the source driver transmits three gray-scale signals to the plurality of first sub-pixels through the three different data lines respectively. 4. The display device of claim 1, wherein a plurality of the first sub-pixels and a second sub-pixel are arranged on the same row among the plurality of the rows, and the plurality of the first sub-pixels and the The second sub-pixel is electrically connected to the same gate line among the plurality of gate lines and is respectively electrically connected to four different data lines among the plurality of data lines, When the gate driver turns on the first sub-pixels and the second sub-pixels, the source driver transmits four grayscale signals to the first sub-pixels and the second sub-pixels through the four different data lines respectively. the second subpixel. 5 . The display device of claim 1 , wherein every n sub-pixels in each of the plurality of rows are electrically connected to the same one of the plurality of gate lines, and n is a positive value greater than or equal to 2. 6 . Integer. 6. The display device of claim 5, wherein the n sub-pixels are electrically connected to different n data lines among the plurality of data lines.

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