CN114815945B - A dual-loop digital LDO structure and control method with adjustable step size - Google Patents

Abstract

The invention provides a double-loop digital LDO structure with adjustable step length and a control method thereof. When the voltage of the current output end is in the quantifiable range of the Flash ADC, the switching state of each large-size power transistor in the large-size power transistor array is directly calculated, so that the voltage step is quickly recovered within a certain range, and coarse adjustment is realized; when the voltage of the current output end is positioned in the middle voltage range of the Flash ADC after the voltage is divided by the resistor chain, the fine adjustment loop generates different control codes through multiple detection and counting, and small-size power tubes with different sizes are controlled to be opened or closed, so that fine adjustment is realized, and the problem that the digital low-dropout linear voltage stabilizer is unstable in adjustment under fixed compensation and is too long in time is solved.

Description

A dual-loop digital LDO structure and control method with adjustable step size

technical field

The invention relates to the technical field of fine-grained power management, in particular to a double-loop digital LDO structure and control method with adjustable step size.

Background technique

The popularity of mobile devices has led to rapid development of low-voltage integrated circuit systems in recent years, and high-efficiency and high-performance power management systems supply power to them. Low-dropout linear regulators (LDOs) are widely used in SoCs with multiple voltage domains and various load circuits for fine-grained power delivery and energy management. Traditional analog LDOs have the advantages of small output voltage ripple, fast response time, and high power supply rejection ratio. When used in modules that are sensitive to power supply noise, they can provide a stable power supply voltage, which has great advantages. However, its design needs to consider the stability of the system. With the continuous improvement of IC technology, low operating voltage has become a trend. At this time, it is difficult to design an analog LDO with a high-gain error amplifier. The digital LDO can work at low voltage. Since the digital circuit works based on the beat of the clock, the execution units and media units such as dynamic memory and memory are sometimes in the working state, and sometimes in the low demand and high retention state. The digital LDO can operate at a lower power The voltage regulation function is realized through digital control, and it is not sensitive to changes in process, voltage and temperature, and has better robustness. However, its simple control logic and fixed adjustment steps take too long to stabilize at lower operating frequencies, and tend to cause system instability at higher operating frequencies.

Contents of the invention

The object of the present invention is to provide a double-loop digital LDO structure and control method with adjustable step size, which solves the problems of unstable regulation and long time for digital low-dropout linear regulators under fixed compensation.

The present invention is realized through the following technical solutions:

A double-loop digital LDO structure with adjustable step size, including a reference voltage module, a quantization module 3, a control module, a power tube array and a load output terminal;

The quantization module includes Flash ADC and dynamic clock comparator; the reference voltage module generates three reference voltages, which are the maximum reference voltage, the target reference voltage, and the minimum reference voltage; the power tube array includes a large-size power tube array and a small-size power tube array; The size of each power tube in the small-size power tube array is different; the size of the large-size power tube in the large-size power tube array is larger than the largest size of the small-size power tube in the small-size power tube array;

The maximum reference voltage and minimum reference voltage of the reference voltage module are connected to the reference signal input terminal of the Flash ADC, the target reference voltage of the reference voltage module is connected to the reference signal input terminal of the dynamic clock comparator, and the voltage signal input terminals of the Flash ADC and the dynamic clock comparator Both are connected to the load output terminal;

The input terminal of the control module is connected to the output terminal of the Flash ADC and the dynamic clock comparator, and the control signal output terminal of the control module is connected to the input terminal of the large-size power tube array and the input terminal of the small-size power tube array; the output terminal of the large-size power tube array is connected to the output terminal of the small-size power tube array The output end of the power tube array is connected with the load output end.

Preferably, the control module includes a four-bit counter, a bidirectional shift register array and a loop controller;

The output end of the Flash ADC is connected to the input end of the loop controller, and the control signal output end of the loop controller is connected to the input end of the large-size power tube array; the output end of the dynamic clock comparator is connected to the input end of the four-bit counter, The output end of the four-bit counter is connected with the control signal input end of the bidirectional shift register array, and the output end of the bidirectional shift register array is connected with the input end of the small-sized power tube array; the enable signal output end of the loop controller is connected with the dynamic Connect to the enable signal input of the clock comparator.

Further, a clock circuit is also included, and the output end of the clock circuit is connected with the clock signal input end of the dynamic clock comparator and the clock signal input end of the bidirectional shift register array.

Preferably, the Flash ADC is composed of a resistor and a continuous time comparator.

Preferably, all power tubes in the large-size power tube array have the same size, and the large-size power tube array can flow the maximum load current.

Preferably, the size of each small-sized power tube in the small-sized power tube array is gradually reduced by a multiple of 1/2 ^N , where N is 1, 2, 3,..., n, and n is the number of small-sized power tubes minus 1; and The size of the largest size small size power tube is a quarter of the size of the large size power tube.

The control method of the double-loop digital LDO structure with adjustable step size includes:

Flash ADC divides the voltage range into four voltage ranges through the resistor chain, which are higher than the maximum reference voltage, from the maximum reference voltage to the target reference voltage, from the target reference voltage to the minimum reference voltage, and below the minimum reference voltage, and detect the current load output in real time The voltage at the terminal is in the voltage interval, and the detection result generates a four-digit code value and outputs it to the control module. When the voltage at the output terminal of the current load is in a voltage interval lower than the minimum reference voltage or in a voltage interval higher than the maximum reference voltage, the control module directly controls The number of large-sized power transistors in the large-sized power transistor array is turned on, so that the voltage at the output end of the load returns to the quantization range of the Flash ADC; when the voltage at the output end of the current load is between the maximum reference voltage and the target reference voltage or between the target reference voltage and the minimum reference voltage When jumping back and forth in the voltage range, the control module sends an enable signal to the dynamic clock comparator, and the dynamic clock comparator turns on and compares the voltage at the output terminal of the current load with the target reference voltage, and outputs the comparison result to the control module, and the control module According to the comparison result, the number of small-sized power transistors in the small-sized power transistor array is controlled, so that the voltage at the output end of the load is gradually stabilized at the target reference voltage value.

Preferably, when the control module includes a four-bit counter, a bidirectional shift register array and a loop controller;

The voltage at the output terminal of the current load is quantized by the Flash ADC to generate a 4-bit coarse control code CR[3:0]. The coarse control code CR[3:0] contains the voltage range of the current load output terminal. The coarse control The code CR[3:0] is output to the loop controller;

The loop controller performs transfer decoding on the coarse adjustment control code CR[3:0]. If the current voltage range of the output terminal of the load is higher than the maximum reference voltage or lower than the minimum reference voltage, the transfer decoding The coarse adjustment control code of the code directly controls the number of large-scale power transistors turned on; if the current voltage range of the output terminal of the load is the voltage range from the maximum reference voltage to the target reference voltage or from the target reference voltage to the minimum reference voltage, the loop The controller will generate the enable signal EN to the dynamic clock comparator and the freeze signal to the Flash ADC, the Flash ADC freezes, the dynamic clock comparator turns on and compares the voltage at the output terminal of the current load with the target reference voltage, and the comparison result is compared with the four-bit counter clock The terminals are connected, and the four-bit counter detects the comparison results in multiple cycles to generate a four-bit fine-tuning control code FN[3:0], which controls the corresponding bidirectional shift register to shift, and controls the small size power transistors of different sizes to turn on quantity.

Further, when the difference between the voltage at the output terminal of the current load and the target reference voltage reaches the quantization accuracy range of the dynamic clock comparator, the fine-tuning control code FN[3:0] controls the corresponding No. 0 bidirectional shift with the default initial value 0000 The register is shifted left or right, and then the corresponding No. 0 small-size power tube is turned on or off, and the voltage at the load output terminal is adjusted with the largest step size, so that the voltage at the load output terminal is stable around the target reference voltage value.

Compared with the prior art, the present invention has the following beneficial effects:

The double-loop digital LDO structure with adjustable step length of the present invention, Flash ADC, control module, large-size power tube array, and load output end form a rough adjustment loop, and the dynamic clock comparator, control module, and small-size power tube array , The load output constitutes a fine-tuning loop. In the specific operation, the voltage at the output terminal is adjusted roughly and finely. When the voltage at the current output terminal is within the quantifiable range of the Flash ADC, the switching states of the large-sized power transistors in the large-sized power transistor array are directly calculated, so that the voltage step When the voltage at the current output terminal is in the middle voltage range of the FlashADC after being divided by the resistor chain, the coarse adjustment loop loses the quantization function, and the voltage at the output terminal is relatively close to the target reference voltage value at this time. Close, the fine-tuning loop generates different control codes through multiple detection counts, controls the small-sized power tubes of different sizes to turn on or off, and recovers the voltage at the output terminal quickly and stably with adjustable steps to achieve fine-tuning. It solves the problem of unstable adjustment and long time of digital low dropout linear regulator under fixed compensation.

Further, the use of multiple sets of bidirectional shift register arrays and small-sized adjustment tubes improves the adjustment accuracy;

Further, the use of continuous-time comparators enables fast transient response and is not clocked.

In the method of the present invention, when the output voltage changes sharply, the coarse adjustment loop performs instantaneous and rapid adjustment. The loop determines the small-sized power tube working in this cycle by calculating the number of fluctuations in the output terminal voltage within several cycles, that is, the adjustment step of this fine adjustment is determined, and the small change in the output terminal next time will cause the small-sized power tube to also occur. Change, that is to achieve the purpose of adjustable step size. This control method can not only react instantaneously and make a quick response, but also realize stable regulation of the output terminal voltage by changing different step sizes, and reduce overshoot caused by large steps.

Description of drawings

Fig. 1 is a schematic diagram of the present invention;

Fig. 2 is a structural representation of the present invention;

Fig. 3 is the control flowchart of the present invention;

Among them, 1 is the clock circuit, 2 is the reference voltage module, 3 is the quantization module, 4 is the loop controller, 5 is the four-bit counter, 6 is the bidirectional shift register array, 7 is the power tube array, 8 is the load output terminal .

Detailed ways

In order to further understand the present invention, the present invention will be described below in conjunction with the examples. These descriptions are only to further explain the features and advantages of the present invention, and are not intended to limit the claims of the present invention.

As shown in FIG. 1 , the double-loop digital LDO structure with adjustable step size according to the present invention includes a reference voltage module 2 , a quantization module 3 , a control module, a power tube array 7 and a load output terminal 8 .

As shown in Figure 2, the quantization module 3 includes a Flash ADC and a dynamic clock comparator composed of a continuous time comparator; the reference voltage module 2 generates three reference voltages, which are respectively the maximum reference voltage Vrefh, the target reference voltage Vref, and the minimum reference voltage Vrefl; The power tube array 7 includes a large-size power tube array and a small-size power tube array. Ensure that the large-sized power tube array can flow through the maximum load current, usually the size of each power tube is the same, and the grid width is at the millimeter level; the size of the small-sized power tube array is gradually reduced from 0 to 15 in multiples of 1/2 ^N , and Wherein the maximum value is a quarter of the large size power tube. N is 1, 2, 3,..., n, where n is the number of small-sized power tubes minus 1.

The maximum reference voltage Vrefh and the minimum reference voltage Vrefl of the reference voltage module 2 are connected to the reference signal input terminal of the Flash ADC, the target reference voltage Vref of the reference voltage module 2 is connected to the reference signal input terminal of the dynamic clock comparator, and the Flash ADC and the dynamic clock comparator The input end of the voltage signal is connected with the output end 8 of the load.

The input terminal of the control module is connected to the output terminal of the Flash ADC and the dynamic clock comparator, and the control signal output terminal of the control module is connected to the input terminal of the large-size power tube array and the input terminal of the small-size power tube array; the output terminal of the large-size power tube array is connected to the output terminal of the small-size power tube array The output end of the power tube array is connected with the load output end 8 .

The Flash ADC, the control module, the large-size power tube array, and the load output terminal 8 form a coarse adjustment loop, and the dynamic clock comparator, the control module, the small-size power tube array, and the load output terminal 8 form a fine-tuning loop.

The control method of the double-loop digital LDO structure with adjustable step size of the present invention is:

The continuous time comparator in the Flash ADC detects in real time the quantization interval of the voltage of the load output terminal 8 (that is, higher than the maximum reference voltage, between the maximum reference voltage and the target reference voltage, between the target reference voltage and the minimum reference voltage, low The detection result is output to the control module. When the voltage of the load output terminal 8 is lower than the minimum reference voltage or higher than the maximum reference voltage, the control module directly controls the large-size power tube array to adjust the current, that is, turn on or off a certain A large number of large-size power tubes, so that the voltage at the load output terminal 8 returns to the quantization range of the Flash ADC, and coarse adjustment is performed through the control code; when the voltage at the load output terminal 8 is within the range of the maximum reference voltage and the target reference voltage or the target When the reference voltage jumps back and forth between the minimum reference voltage range, the control module controls the dynamic clock comparator to turn on, and the dynamic clock comparator compares the voltage of the load output terminal 8 with the target reference voltage, and outputs the comparison result to the control module to control According to the comparison result, the module controls the small-size power tube array to adjust the current, that is, turn on or off a certain number of small-size power tubes, so that the voltage at the load output terminal 8 gradually stabilizes at the target reference voltage value.

Example

Referring to Figures 1 to 3, the double-loop digital LDO structure with adjustable step size according to the embodiment of the present invention includes a clock circuit 1, a reference voltage module 2, a quantization module 3, a control module, a power transistor array 7 and a load output terminal 8 . The control module includes a four-bit counter 5 , a bidirectional shift register array 6 and a loop controller 4 .

The input end of the quantization module 3 is connected with the reference voltage module 2 and the load output end 8, the input end of the loop controller 4 is connected with the output end of the quantization module 3, the output end of the clock circuit 1 is connected with the input end of the quantization module 3 connected, the input end of the four-bit counter 5 is connected with the output end of the quantization module 3, the input end of the bidirectional shift register array 6 is connected with the output end of the four-bit counter 5 and the output end of the clock circuit 1, and the power tube array The input terminal of 7 is connected with the output terminal of the bidirectional shift register array 6, the output terminal of the loop controller 4 and the load output terminal 8.

As shown in Figure 2, the quantization module 3 includes a Flash ADC and a dynamic clock comparator composed of a continuous time comparator; the reference voltage module 2 generates three reference voltages, which are respectively the maximum reference voltage Vrefh, the target reference voltage Vref, and the minimum reference voltage Vrefl; The power tube array 7 includes a large-size power tube array and a small-size power tube array.

The maximum reference voltage Vrefh and the minimum reference voltage Vrefl of the reference voltage module 2 are connected to the input terminal of the Flash ADC, the target reference voltage Vref of the reference voltage module 2 is connected to the input terminal of the dynamic clock comparator, and the input terminals of the Flash ADC and the dynamic clock comparator are connected to the The load output terminals 8 are connected.

The output end of the Flash ADC is connected to the input end of the loop controller 4, the control signal output end of the loop controller 4 is connected to the input end of the large-size power tube array, and the output end of the large-size power tube array is connected to the load output end 8 The output end of dynamic clock comparator is connected with the input end of four-bit counter 5, and the output end of four-bit counter 5 is connected with the control signal input end of bidirectional shift register array 6, and the output end of bidirectional shift register array 6 is connected with small The input terminal of the size power tube array is connected, and the output terminal of the small size power tube array is connected with the load output terminal 8; the output terminal of the clock circuit 1 is connected with the clock signal input terminal of the dynamic clock comparator and the clock signal of the bidirectional shift register array 6 input connection. The enable signal output end of the loop controller is connected with the enable signal input end of the dynamic clock comparator.

The use of continuous time comparators can achieve fast transient response and is not controlled by the clock. Multiple sets of bidirectional shift register arrays and small size adjustment tubes improve the adjustment accuracy and achieve a good compromise between speed and accuracy.

The control method of the double-loop digital LDO structure with adjustable step size described in the embodiment of the present invention comprises the following steps:

The reference voltage module generates three reference voltage values, namely the maximum reference voltage Vrefh, the minimum reference voltage Vrefl and the target reference voltage Vref. The Flash ADC of the quantization module divides Vrefh and Vrefl into 4 voltage ranges through resistor chain voltage division, which are higher than Vrefh, Vrefh-Vref, Vref-Vrefl and lower than Vrefl respectively, so as to have different quantization thresholds, and the load output terminal 8 After the voltage is quantized by the continuous time comparator in the Flash ADC, a 4-bit coarse control code CR[3:0] is generated. The coarse control code CR[3:0] contains the current voltage range of the load output terminal 8 , the result is output to the loop controller; the loop controller performs transfer decoding on the coarse control code CR[3:0], if the voltage range of the current load output terminal 8 is higher than Vrefh or lower than Vrefl, Then the adjusted coarse-tuning control code directly controls the number of large-scale power tubes turned on; if the voltage range of the current load output terminal 8 is Vrefh-Vref or Vref-Vrefl, the coarse-tuning loop cannot perform subdivision discrimination. The timing loop controller will generate the fine-tuning loop enable signal EN to the dynamic clock comparator and the coarse-tuning loop freeze signal to the Flash ADC, the Flash ADC is frozen, the dynamic clock comparator is turned on and the voltage of the load output terminal 8 is equal to the target The reference voltage Vref is compared (the dynamic clock comparator is controlled by the clock, and the voltage at the output terminal is compared with the target reference voltage when the clock arrives). The comparison result produces four-bit fine-tuning control code FN[3:0], which correspond to different sizes of adjustment steps and bidirectional shift registers, control the shifting of bidirectional shift registers, and control small-sized power transistors of different sizes to turn on or The number of closures.

When the voltage of the current load output terminal 8 is in the Vrefh-Vref or Vref-Vrefl voltage range, the output voltage is closer to the target reference voltage, that is, when the difference between the current load output terminal 8 voltage and the target reference voltage reaches the dynamic clock comparator When the quantization accuracy is within the range, the fine-tuning control code FN[3:0] controls the corresponding No. 0 bidirectional shift register to shift left or right with the default initial value of 0000, and then the corresponding No. 0 small-size power tube is turned on or off. Adjust the voltage at the load output terminal with the maximum step size, so that the voltage at the load output terminal is stable around the target reference voltage value. Since the size of the small-size power tube array in the fine-tuning loop is much smaller than the large-size power tube array, the voltage at the load output terminal After detection, the change is still within the fine-tuning range, but the original comparison result changes at this time, and the fine-tuning control code FN changes after adding 1 to the four-bit counter. 0001~1111 correspond to different bidirectional shift registers and small-size For power tubes, the adjustment step size decreases in turn, 1111 represents the minimum step size, and its small-sized power tube has the smallest size. Within the fine-tuning range, the dynamic clock comparator continuously compares the voltage at the load output terminal with the target reference voltage, which is generated by a four-bit counter. The fine-tuning control code controls the small-sized power tubes of different sizes to turn on or off, and the voltage at the output end of the load changes accordingly with different adjustment steps, and gradually stabilizes at the target reference voltage value.

In the method of the present invention, when the output voltage changes sharply, the coarse adjustment loop performs instantaneous and rapid adjustment. The four-bit counter under the beat determines the bidirectional shift register and its corresponding small-sized power tube working in this cycle by calculating the fluctuation number of output terminal voltage in several cycles, that is, the adjustment step size of this fine adjustment is determined, and the next time When the clock beat arrives, the slight change of the output terminal makes the four-bit counter increase or decrease by 1, and the corresponding bidirectional shift register and small-sized power tube also change, that is, the purpose of adjustable step size is realized. This structure and control method can not only respond instantaneously and make a quick response, but also realize stable adjustment of the output terminal voltage by changing different step sizes, and reduce overshoot caused by large steps.

The digital LDO is widely used in the field of fine-grained power management, and plays an important role in the low-voltage and low-power operation of the digital integrated circuit. The structure and method proposed by the invention meet the fast and stable response of the digital LDO.

The above content is only to illustrate the technical ideas of the present invention, and cannot limit the protection scope of the present invention. Any changes made on the basis of the technical solutions according to the technical ideas proposed in the present invention shall fall within the scope of the claims of the present invention. within the scope of protection.

Claims (4)

1. A control method for a double-loop digital LDO structure with adjustable step size, characterized in that, the adjustable step-size double-loop digital LDO structure includes a reference voltage module (2), a quantization module (3), and a control module , power tube array (7) and load output terminal (8); Quantization module (3) includes Flash ADC and dynamic clock comparator; reference voltage module (2) generates three reference voltages, which are maximum reference voltage, target reference voltage, and minimum reference voltage; power tube array (7) includes large-scale power tube array and small-size power tube array; the size of each power tube in the small-size power tube array is different; the size of the large-size power tube in the large-size power tube array is larger than the largest size of the small-size power tube in the small-size power tube array; The maximum reference voltage and minimum reference voltage of the reference voltage module (2) are connected to the reference signal input terminal of the Flash ADC, the target reference voltage of the reference voltage module (2) is connected to the reference signal input terminal of the dynamic clock comparator, and the Flash ADC is compared with the dynamic clock The voltage signal input terminals of the device are all connected to the load output terminal (8); The input terminal of the control module is connected to the output terminal of the Flash ADC and the dynamic clock comparator, and the control signal output terminal of the control module is connected to the input terminal of the large-size power tube array and the input terminal of the small-size power tube array; the output terminal of the large-size power tube array is connected to the output terminal of the small-size power tube array The output end of the power tube array is connected to the load output end (8); Flash ADC consists of resistors and continuous time comparators; The size of each small-sized power tube in the small-sized power tube array is

, N is 1,2,3,...,n, n is the number of small-sized power tubes minus 1; and the size of the largest small-sized power tube is a quarter of the size of the large-sized power tube; The control module includes a four-bit counter (5), a bidirectional shift register array (6) and a loop controller (4); The output end of the Flash ADC is connected to the input end of the loop controller (4), and the control signal output end of the loop controller (4) is connected to the input end of the large-size power tube array; the output end of the dynamic clock comparator is connected to the four-bit The input terminal of the counter (5) is connected, the output terminal of the four-bit counter (5) is connected with the control signal input terminal of the bidirectional shift register array (6), and the output terminal of the bidirectional shift register array (6) is connected with the small-sized power tube The input end of the array is connected; the enable signal output end of the loop controller (4) is connected with the enable signal input end of the dynamic clock comparator; The methods include: Flash ADC divides the voltage range into four voltage ranges through the resistor chain, which are higher than the maximum reference voltage, from the maximum reference voltage to the target reference voltage, from the target reference voltage to the minimum reference voltage, and below the minimum reference voltage, and detect the current load output in real time The voltage at the terminal (8) is in the voltage range, and the detection result generates a four-digit code value and outputs it to the control module. When the voltage at the output terminal (8) of the current load is in the voltage range lower than the minimum reference voltage or in a In the voltage range, the control module directly controls the number of large-size power tubes in the large-size power tube array to restore the voltage at the load output terminal (8) to within the quantization range of the Flash ADC; when the current load output terminal (8) voltage is within When the voltage range from the maximum reference voltage to the target reference voltage or from the target reference voltage to the minimum reference voltage jumps back and forth, the control module sends an enable signal to the dynamic clock comparator, and the dynamic clock comparator turns on and outputs the current load (8) The voltage is compared with the target reference voltage, and the comparison result is output to the control module. According to the comparison result, the control module controls the number of small-size power tubes in the small-size power tube array, so that the voltage of the load output terminal (8) gradually stabilizes at the target Reference voltage value; When the control module includes a four-bit counter (5), a bidirectional shift register array (6) and a loop controller (4); The voltage of the current load output terminal (8) is quantized by the Flash ADC to generate a 4-bit coarse control code CR[3:0]. The coarse control code CR[3:0] contains the current load output terminal (8) voltage interval, the coarse control code CR[3:0] is output to the loop controller; The loop controller performs transfer decoding on the coarse control code CR[3:0]. If the current voltage range of the load output terminal (8) is higher than the maximum reference voltage or lower than the minimum reference voltage, then The coarse-tuning control code after transfer decoding directly controls the number of large-scale power transistors turned on; if the voltage range of the current load output terminal (8) is the voltage from the maximum reference voltage to the target reference voltage or from the target reference voltage to the minimum reference voltage interval, the loop controller will generate the enable signal EN to the dynamic clock comparator and the freeze signal to the Flash ADC, the Flash ADC freezes, the dynamic clock comparator turns on and compares the voltage of the current load output terminal (8) with the target reference voltage For comparison, the comparison result is connected to the clock terminal of the four-bit counter, and the four-bit counter detects the comparison result in multiple cycles to generate a four-bit fine-tuning control code FN[3:0], which controls the corresponding bidirectional shift register to shift , to control the number of small power tubes of different sizes turned on. 2. The control method of the dual-loop digital LDO structure with adjustable step size according to claim 1, characterized in that, when the difference between the voltage of the current load output terminal (8) and the target reference voltage reaches the quantization of the dynamic clock comparator When the accuracy is within the range, the fine-tuning control code FN[3:0] controls the corresponding No. 0 bidirectional shift register to shift left or right with the default initial value of 0000, and then the corresponding No. 0 small-size power tube is turned on or off to The maximum step size adjusts the voltage of the load output terminal (8), so that the voltage of the load output terminal (8) is stable around the target reference voltage value. 3. The control method of the dual-loop digital LDO structure with adjustable step size according to claim 1, characterized in that the structure further includes a clock circuit (1), the output terminal of the clock circuit (1) and the dynamic clock comparator The clock signal input end of the clock signal is connected with the clock signal input end of the bidirectional shift register array (6). 4. the control method of the double-loop digital LDO structure with adjustable step size according to claim 1, characterized in that, the size of each power tube in the large-size power tube array is the same, and the large-size power tube array can flow through maximum load current.

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