CN114793115B - Voltage-mode PAM-4 driver fused with combiner - Google Patents

Abstract

The application relates to a voltage-mode PAM-4 driver integrated with a combiner. The device comprises a first voltage mode branch, a second voltage mode branch, a third voltage mode branch, a fourth voltage mode branch and a load; the first voltage mode branch and the second voltage mode branch form an anode output end, and the third voltage mode branch and the fourth voltage mode branch form a cathode output end; the voltage mode branch circuit includes: the three-state gate selector group and the matching impedance, one end of the matching impedance is connected with the output end of the three-state gate selector group, and the other end of the matching impedance is connected with the load; the conduction of the tristate gate selector in the tristate gate selector group is realized through the control of the clock level, and the output weight of the tristate gate selector group is determined through the output impedance of the voltage mode branch. The application adopts the output of the three-state gate selector to directly drive the matched impedance to generate final output, eliminates the full-speed intermediate node, and relieves the limitation of parasitic capacitance limitation bandwidth to the data transmission speed.

Description

A voltage mode PAM-4 driver integrated with a combiner

Technical Field

The present application relates to the technical field of integrated circuit design, and in particular to a voltage-mode PAM-4 driver integrated with a combiner.

Background Art

Voltage mode drivers have the characteristics of high linearity and high swing, and have been widely used in high-speed serial port transmitters modulated by PAM-4 (Four Pulse Amplitude Modulation). The traditional structure is shown in Figure 1. The combiner converts the low-speed parallel input into a serial output, which is then sent to the channel by the driver. The driver input nodes A, B, C, and D are in full-rate transmission state (that is, the data rate is equal to the baud rate), and the bandwidth at this node is required to be no less than the Nyquist frequency. However, due to the presence of parasitic capacitance at the node (mainly including the driver input stage gate capacitance and the combiner output drain capacitance), and in order to achieve impedance matching, the driver often uses a large-size inverter, which further increases the parasitic capacitance and limits the improvement of bandwidth, making the traditional structure unable to meet the requirements of the ever-increasing data transmission speed.

Summary of the invention

Based on this, in order to solve the above technical problems, the present invention proposes a voltage-mode PAM-4 driver integrated with a combiner to alleviate the bandwidth limitation caused by parasitic capacitance.

A first voltage mode branch, a second voltage mode branch, a third voltage mode branch, a fourth voltage mode branch and a load; the first voltage mode branch and the second voltage mode branch constitute a positive differential signal output terminal, and the third voltage mode branch and the fourth voltage mode branch constitute a negative differential signal output terminal; the voltage mode branch includes: a three-state gate selector group and a matching impedance, one end of the matching impedance is connected to the output end of the three-state gate selector group, and the other end of the matching impedance is connected to the load; the conduction of the three-state gate in the three-state gate selector group is achieved by controlling the clock level, and the weight of the synthesized output is determined by the size of the voltage mode branch output impedance.

In one of the embodiments, it also includes an NRZ signal output terminal and a multi-phase clock signal output terminal: the input terminal of the three-state gate selector group is connected to the NRZ signal output and the clock signal output terminal respectively; the three-state gate is turned on when the clock signal output is a high level, and generates a high-impedance output when the clock signal output is a low level.

In one embodiment, the first voltage mode branch includes: one end of the three-state gate selector group is connected to the positive pole of the L_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the three-state gate selector group is connected to the matching impedance R1 to output the positive signal.

In one embodiment, the second voltage mode branch includes: one end of the three-state gate selector group is connected to the positive pole of the M_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the three-state gate selector group is connected to the matching impedance R2 to output the positive signal.

In one embodiment, the first voltage-mode branch and the second voltage-mode branch are in parallel; the output impedance of the first voltage-mode branch is twice the output impedance of the second voltage-mode branch, and through the control of the clock level, the second voltage-mode branch and the first voltage-mode branch are synthesized with a weight of 2:1 to output a positive differential signal.

In one embodiment, the third voltage mode branch includes: one end of the three-state gate selector group is connected to the negative pole of the L_D terminal in the NRZ signal output end to obtain the signal; the other end of the three-state gate selector group is connected to the matching impedance R3 to output the negative pole signal.

In one embodiment, the fourth voltage mode branch includes: one end of the three-state gate selector group is connected to the negative pole of the M_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the three-state gate selector group is connected to the matching impedance R4 to output the negative pole signal.

In one embodiment, the third voltage mode branch and the fourth voltage mode branch are in parallel structure; the output impedance of the third voltage mode branch is twice the output impedance of the fourth voltage mode branch, and through the control of the clock level, the fourth voltage mode branch and the third voltage mode branch are synthesized with a weight of 2:1 to output a negative pole differential signal.

In one of the embodiments, it also includes a matching impedance RL; converting the parallel positive differential signal and the negative differential signal into a serial differential output signal, superimposing them at the end of the matching impedance RL, and then sending them to the channel.

In one embodiment, the three-state gate selector group may be composed of two or more three-state gates, which is generally an even multiple of 2; and the three-state gates are connected in parallel.

The above structure is different from the traditional structure in which the data stream first passes through the combiner and then passes through the driver. In the present invention, a three-state gate selector group and matching impedance are used to form four branches. The conduction of the three-state gate selector in the three-state gate selector group is realized by controlling the clock level. Therefore, under the control of the two-phase clock, each branch directly drives the matching impedance with the output of the three-state gate selector to generate a positive differential output signal and a negative differential output signal. The differential output signal is superimposed on the load, and the parallel-to-serial conversion is completed and then output to the signal channel; the present invention eliminates the full-speed intermediate node and alleviates the limitation of the parasitic capacitance limiting bandwidth on the data transmission speed. Compared with the traditional structure, the large-size inverter is omitted, the area consumption is reduced, and the dynamic power consumption is reduced at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a traditional voltage-mode PAM-4 driver.

FIG. 2 is a schematic diagram of a voltage mode PAM-4 driver proposed in the present invention.

FIG3 is a diagram showing a specific application scenario of the voltage mode PAM-4 driver proposed in the present invention.

DETAILED DESCRIPTION

In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

To facilitate understanding, the basic concepts are explained. NRZ signal is non-return-to-zero encoding, which uses high and low signal levels to represent 1 and 0 of digital logic signals, and can transmit 1 bit of logic information per clock cycle; PAM-4, also known as four-level pulse amplitude modulation, is a modulation technology that uses 4 different signal levels for signal transmission. When certain rules are used to convert the logic signal in binary into four different levels for signal output, the logic information that can be transmitted per clock cycle becomes 2 bits, doubling, thereby increasing the bandwidth data transmission rate.

The tri-state gate selector is a tri-state circuit that can provide three different output values: logic "0", logic "1" and high impedance state, which is mainly used to isolate the logic gate from the rest of the system. So when its input is high potential, it is connected, and when the input is low potential, it is disconnected.

Matched impedance refers to a working state in which the load impedance and the internal impedance of the excitation source are adapted to each other to obtain the maximum power output. No signal will be reflected back to the source point to obtain the maximum efficiency.

In one of the embodiments, as shown in FIG2 , a voltage-mode PAM-4 driver schematic diagram is proposed, including: a first voltage-mode branch 201, a second voltage-mode branch 202, a third voltage-mode branch 203, a fourth voltage-mode branch 204 and a load RL; the first voltage-mode branch 201 and the second voltage-mode branch 202 constitute a positive differential signal output terminal, and the third voltage-mode branch 203 and the fourth voltage-mode branch 204 constitute a negative differential signal output terminal; the voltage-mode branch includes: a three-state gate selector group and a matching impedance, one end of the matching impedance is connected to the output end of the three-state gate selector group, and the other end of the matching impedance is connected to the load; the conduction of the three-state gates in the three-state gate selector group is realized by controlling the clock level, and the weight of the output of the three-state gate selector group is determined by the size of the matching impedance.

It is worth noting that the four voltage-mode branch structures in the present invention are the same; the first voltage-mode branch and the second voltage-mode branch are connected to the positive terminal of the NRZ signal, wherein the output impedance of the first voltage-mode branch is twice the output impedance of the second voltage-mode branch, so under the control of the clock signal, the positive differential signal Vop is output according to the weight of 2:1; the third voltage-mode branch and the fourth voltage-mode branch are symmetrical structures, except that they are connected to the negative terminal of the NRZ signal, and under the control of the clock signal, the negative differential signal Von is output according to the weight of 2:1.

The descriptions such as "first" and "second" involved therein only represent the naming method, without distinguishing between size and order, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated; the voltage-mode output impedance mentioned is the output impedance of the three-state gate and the matching impedance connected to it as a whole.

It also includes an NRZ signal output terminal and a multi-phase clock signal output terminal: the input terminal of the three-state gate selector group is respectively connected to the NRZ signal output and the clock signal output terminal; the three-state gate is turned on when the clock signal output is a high level, and generates a high-impedance output when the clock signal output is a low level.

The first voltage mode branch includes: one end of the three-state gate selector group is connected to the positive pole of the L_D terminal in the NRZ signal output terminal, and the signal is obtained according to whether the three-state gate is turned on; the other end of the three-state gate selector group is connected to the matching impedance R1 to output the positive pole signal of the L_D terminal.

The second voltage mode branch includes: one end of the three-state gate selector group is connected to the positive pole of the M_D terminal in the NRZ signal output terminal, and the signal is obtained according to whether the three-state gate is turned on; the other end of the three-state gate selector group is connected to the matching impedance R2 to output the positive pole signal of the M_D terminal.

The first voltage-mode branch and the second voltage-mode branch are in parallel structure; the output impedance of the first voltage-mode branch is twice the output impedance of the second voltage-mode branch. Through the control of the clock level, the second voltage-mode branch and the first voltage-mode branch are synthesized with a weight of 2:1 to output a positive differential signal.

The third voltage mode branch includes: one end of the three-state gate selector group is connected to the negative pole of the L_D terminal in the NRZ signal output terminal, and the signal is obtained according to whether the three-state gate is turned on; the other end of the three-state gate selector group is connected to the matching impedance R3 to output the negative pole signal of the L_D terminal.

The fourth voltage mode branch includes: one end of the three-state gate selector group is connected to the negative pole of the M_D terminal in the NRZ signal output terminal, and the signal is obtained according to whether the three-state gate is turned on; the other end of the three-state gate selector group is connected to the matching impedance R4 to output the negative pole signal of the M_D terminal.

The third voltage mode branch and the fourth voltage mode branch are in parallel structure; the output impedance of the third voltage mode branch is twice the output impedance of the fourth voltage mode branch. Through the control of the clock level, the fourth voltage mode branch and the third voltage mode branch are synthesized with a weight of 2:1 to output a negative differential signal.

It also includes a matching impedance RL; converting the parallel positive differential signal and the negative differential signal into a serial differential output signal, superimposing them at the matching impedance RL, and then sending them to the channel.

The three-state gate selector group can be composed of two or more three-state gates, which is generally an even multiple of 2; the three-state gates adopt a parallel structure.

In one of the embodiments, as shown in FIG3 , a specific application scenario of a voltage mode PAM-4 driver integrated with a combiner is described in detail:

Referring to FIG3 , the tri-state gate Sel1\Sel2 and the matching impedance R1 form the first voltage-mode branch, and the output impedance is 150 ohms; the tri-state gate Sel3\Sel4 and the matching impedance R2 form the second voltage-mode branch, and the output impedance is 75 ohms; the tri-state gate Sel5\Sel6 and the matching impedance R3 form the third voltage-mode branch, and the output impedance is 150 ohms; the tri-state gate Sel7\Sel8 and the matching impedance R4 form the fourth voltage-mode branch, and the output impedance is 75 ohms, and the differential output load RL=100 ohms. According to the resistance voltage division rule, when the second voltage-mode branch and the fourth voltage-mode branch synthesize the output signal, their weights are twice that of the first voltage-mode branch and the third voltage-mode branch, so that the function of synthesizing the NRZ signal into the PAM-4 output signal can be completed.

The descriptions such as "sel1" and "sel2" involved therein only represent the naming method, without distinguishing between size and order, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features.

The structure of the present invention also includes an NRZ signal output end and a two-phase clock signal output end, wherein the NRZ input signal is: four pairs of differential signals: M_D0P/M_D0N, M_D1P/M_D1N, L_D0P/L_D0N, L_D1P/L_D1N, and the two-phase clock signal is: clock CK0 with an input clock of 0 phase and clock CK180 with an input clock of 180.

The input end of the tri-state gate Sel1\Sel2 is connected to the matching impedance R1, the input end of the tri-state gate Sel1 is connected to the L_D0P end and the clock CK0 end; the input end of the tri-state gate Sel2 is connected to the L_D1P end and the clock CK180 end.

The input end of the tri-state gate Sel3\Sel4 is connected to the matching impedance R2, the input end of the tri-state gate Sel3 is connected to the M_D0P end and the clock CK0 end; the input end of the tri-state gate Sel4 is connected to the M_D1P end and the clock CK180 end.

The input end of the tri-state gate Sel5\Sel6 is connected to the matching impedance R3, the input end of the tri-state gate Sel5 is connected to the L_D0N end and the clock CK0 end; the input end of the tri-state gate Sel6 is connected to the L_D1N end and the clock CK180 end.

The input end of the tri-state gate Sel7\Sel8 is connected to the matching impedance R4, the input end of the tri-state gate Sel7 is connected to the M_D0N end and the clock CK0 end; the input end of the tri-state gate Sel8 is connected to the M_D1N end and the clock CK180 end.

Take Sel1\Sel2 to illustrate the working principle of the tri-state gate: when the clock CK0 is high, CK180 is low, Sel2 outputs high impedance, Sel1 is turned on, and L_D0P is selected to the output terminal V1p; similarly, when CK0 is low, CK180 is high, and L_D1P is selected to the output terminal V1P. Therefore, under the control of the two-phase clock CK0/CK180, Sel1\Sel2 realizes a 2:1 combiner.

Similarly, by increasing the number of tri-state gates and controlling multi-phase clocks, the function of multiple combiners based on the same principle can also be realized.

The overall working principle of the PAM-4 driver of the present invention is: when the clock CK0 is at a high level, the three-state gate Sel1 and the three-state gate Sel3 are turned on, and M_D0P and L_D0P are synthesized according to a weight of 2:1 to output a positive differential signal Vop; the three-state gate Sel5 and the three-state gate Sel7 are turned on, and M_D0N and L_D0N are synthesized according to a weight of 2:1 to output a negative differential signal Von.

When the clock CK180 is at a high level, the three-state gate Sel2 and the three-state gate Sel4 are turned on, and M_D1P and L_D1P are synthesized according to a weight of 2:1 to output the positive differential signal Vop; the three-state gate Sel6 and the three-state gate Sel8 are turned on, and M_D1N and L_D1N are synthesized according to a weight of 2:1 to output the negative differential signal Von.

The positive differential signal Vop and the negative differential signal Von are converted from parallel to serial into a serial differential output signal, which is then superimposed at the matching impedance RL end and sent to the channel.

The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims (10)

1. A voltage mode PAM-4 driver integrated with a combiner, comprising: A first voltage-mode branch, a second voltage-mode branch, a third voltage-mode branch, a fourth voltage-mode branch and a load; the first voltage-mode branch and the second voltage-mode branch constitute a positive differential signal output terminal, and the third voltage-mode branch and the fourth voltage-mode branch constitute a negative differential signal output terminal; The voltage mode branch includes: a tri-state gate selector group and a matching impedance, one end of the matching impedance is connected to the output end of the tri-state gate selector group, and the other end of the matching impedance is connected to the load; The conduction of the tri-state gates in the tri-state gate selector group is achieved by controlling the clock level, and the weight of the synthesized output is determined by the size of the voltage-mode branch output impedance. 2. The voltage mode PAM-4 driver integrated with a combiner according to claim 1, characterized in that it also includes an NRZ signal output terminal and a multi-phase clock signal output terminal: The input end of the tri-state gate selector group is respectively connected to the NRZ signal output and the multi-phase clock signal output end; The tri-state gate is turned on when the clock signal output is at a high level, and generates a high-impedance output when the clock signal output is at a low level. 3. A voltage-mode PAM-4 driver integrated with a combiner according to claim 2, characterized in that the first voltage-mode branch comprises: One end of the tri-state gate selector group is connected to the positive pole of the L_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the tri-state gate selector group is connected to the matching impedance R1 to output the positive pole signal. 4. A voltage-mode PAM-4 driver integrated with a combiner according to claim 2 or 3, characterized in that the second voltage-mode branch comprises: One end of the tri-state gate selector group is connected to the positive pole of the M_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the tri-state gate selector group is connected to the matching impedance R2 to output the positive pole signal. 5. The voltage mode PAM-4 driver integrated with a combiner according to claim 4, characterized in that: The first voltage-mode branch and the second voltage-mode branch are in a parallel structure; The output impedance of the first voltage-mode branch is twice the output impedance of the second voltage-mode branch. Through the control of the clock level, the second voltage-mode branch and the first voltage-mode branch are synthesized with a weight of 2:1 to output a positive differential signal. 6. A voltage-mode PAM-4 driver integrated with a combiner according to claim 2, characterized in that the third voltage-mode branch comprises: One end of the tri-state gate selector group is connected to the negative pole of the L_D terminal in the NRZ signal output terminal to obtain the signal; the other end of the tri-state gate selector group is connected to the matching impedance R3 to output the negative pole signal. 7. A voltage-mode PAM-4 driver integrated with a combiner according to claim 2 or 6, characterized in that the fourth voltage-mode branch comprises: One end of the tri-state gate selector group is connected to the negative pole of the M_D terminal in the NRZ signal output terminal to obtain the input signal; the other end of the tri-state gate selector group is connected to the matching impedance R4 to output the negative pole signal. 8. The voltage mode PAM-4 driver integrated with a combiner according to claim 7, characterized in that: The third voltage mode branch and the fourth voltage mode branch are in parallel structure; The output impedance of the third voltage-mode branch is twice the output impedance of the fourth voltage-mode branch. Through the control of the clock level, the fourth voltage-mode branch and the third voltage-mode branch are synthesized with a weight of 2:1 to output a negative differential signal. 9. A voltage mode PAM-4 driver integrated with a combiner according to claim 5 or 8, characterized in that: It also includes matching impedance RL; The parallel positive differential signal and the negative differential signal are converted into a serial differential output signal, which is then superimposed at the matching impedance RL end and then sent to the channel. 10. A voltage mode PAM-4 driver integrated with a combiner according to any one of claims 1 to 9, characterized in that: The three-state gate selector group may be composed of two or more three-state gates, which are generally an even multiple of 2; and the three-state gates are connected in parallel.