CN114793112B - Maximum voltage selection circuit - Google Patents
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- CN114793112B CN114793112B CN202110095515.4A CN202110095515A CN114793112B CN 114793112 B CN114793112 B CN 114793112B CN 202110095515 A CN202110095515 A CN 202110095515A CN 114793112 B CN114793112 B CN 114793112B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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Abstract
本公开涉及集成电路技术领域，提供了一种最大电压选择电路，其包括：连接有第一输入端口和第二输入端口的输入单元，该输入单元根据第一输入电压和第二输入电压生成检测信号；第一输出单元，响应于第一状态的检测信号，根据前述第一输入电压生成输出电压；第二输出单元，响应于第二状态的检测信号，根据前述第二输入电压生成前述的输出电压，该最大电压选择电路根据该检测信号的状态选择前述第一输出单元和前述第二输出单元的其中之一导通，提供前述的输出电压到负载端。由此可实现最大电压选择的同时有效降低其压降损耗，且能减小电路中晶体管的尺寸，进而减小电路集成面积，降低制造成本。
The present disclosure relates to the technical field of integrated circuits, and provides a maximum voltage selection circuit, which includes: an input unit connected to a first input port and a second input port, the input unit generating a detection signal according to a first input voltage and a second input voltage; a first output unit, responding to a detection signal of a first state, generating an output voltage according to the aforementioned first input voltage; a second output unit, responding to a detection signal of a second state, generating the aforementioned output voltage according to the aforementioned second input voltage, and the maximum voltage selection circuit selects one of the aforementioned first output unit and the aforementioned second output unit to be turned on according to the state of the detection signal, and provides the aforementioned output voltage to the load end. In this way, the maximum voltage selection can be achieved while effectively reducing its voltage drop loss, and the size of the transistor in the circuit can be reduced, thereby reducing the circuit integration area and reducing the manufacturing cost.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a maximum voltage selection circuit.
Background
The use of a maximum voltage selection circuit in an integrated circuit is often required, and the main function of the maximum voltage selection circuit is to select one maximum voltage output from a plurality of existing voltages for use by other circuits in the integrated circuit.
Fig. 1 shows a schematic diagram of a three-way voltage maximum voltage selection circuit in the prior art. As shown in fig. 1, the maximum voltage selection circuit 100 includes a first input port connected to a first input voltage VCC1, a second input port connected to a second input voltage VCC2, a third input port connected to a third input voltage VCC3, and an output port providing an output voltage Vmax, and transistors Mp1 to Mp6, and the maximum voltage selection circuit 100 is capable of selecting the maximum voltage as the output voltage Vmax when a voltage difference between the first input voltage VCC1, the second input voltage VCC2, and the third input voltage VCC3 is large. However, since the first input voltage VCC1, the second input voltage VCC2, and the third input voltage VCC3 are not 0 in general, a P-type metal oxide semiconductor field effect transistor (PMOS) having the first input voltage VCC1, the second input voltage VCC2, or the third input voltage VCC3 as a gate voltage will cause a driving capability of the output voltage Vmax to be insufficient, and when the voltage difference between the first input voltage VCC1, the second input voltage VCC2, and the third input voltage VCC3 is small or equal, the PMOS in the maximum voltage selection circuit 100 cannot operate normally, and cannot generate the output voltage Vmax.
Fig. 2 shows a schematic diagram of another prior art maximum voltage selection circuit. As shown in fig. 2, the maximum voltage selection circuit 200 includes a first input port connected to a first input voltage Vin1, a second input port connected to a second input voltage Vin2, and an output port for providing an output voltage Vmax, and a transistor Mp1, a transistor Mp2, a diode D1, and a diode D2, wherein the transistor Mp1 is connected between the first input port and the output port, a control terminal of the transistor Mp1 is connected to the second input port, an anode of the diode D1 is connected to the first input port, a cathode is connected to the output port, the transistor Mp2 is connected between the second input port and the output port, a control terminal of the transistor Mp2 is connected to the first input port, an anode of the diode D2 is connected to the second input port, and a cathode is connected to the output port, and when the transistor Mp1/Mp2 is not turned on, a voltage Vmax of the output node is MAX (Vin 1, 2) -Vd, that is, the voltage Vmax of the first input voltage and the second input voltage Vin2 is subtracted by the diode D1/D2. Vth is defined as the on threshold voltage of the transistor Mp1/Mp 2. When the first input voltage Vin1 is lower than (Vin 2-Vd-Vth), the transistor Mp2 is turned on, the output node is selectively connected to the second input voltage Vin2 through the transistor Mp2, and similarly, when the second input voltage Vin2 is lower than (Vin 1-Vd-Vth), the transistor Mp1 is turned on, and the output node is selectively connected to the first input voltage Vin1 through the transistor Mp 1. Since iload_ron is much smaller than Vd, the voltage output node voltage vmax=vin 2-iload_ron 2 at this time, or vmax=vin 1-iload_ron 1. Wherein Iload is the load current at the output node, ron1/Ron2 is the on-resistance of the transistor Mp1/Mp 2.
In order to have no voltage drop loss, the closer the voltage Vmax of the output node is to the second input voltage Vin2 (or the first input voltage Vin 1), the better. I.e. the smaller Ron2 (Ron 1) the better. And the Ron of a transistor is inversely proportional to its own width to length ratio (W/L) and gate-to-source voltage Vgs. When the first input voltage Vin1 is low, the transistor Mp2 is turned on, and the gate-source voltage vgs=vmax-Vin 1. When the second input voltage Vin2 is low, the transistor Mp1 is turned on, and the gate-source voltage vgs=vmax-Vin 2. Here Vin1/Vin2 is fixed, and for Ron to be small, the size of W/L can be increased, thereby increasing the area, which increases the manufacturing cost of the circuit.
Disclosure of Invention
In order to solve the above technical problems, the present disclosure provides a maximum voltage selection circuit, which can realize the selection of the maximum voltage and effectively reduce the voltage drop loss thereof, and can reduce the size of the transistors in the circuit, thereby reducing the circuit integration area and the manufacturing cost.
According to the present disclosure, there is provided a maximum voltage selection circuit having a first input port connected to a first input voltage, a second input port connected to a second input voltage, and an output port providing an output voltage, wherein the maximum voltage selection circuit further includes:
An input unit connected to the first input port and the second input port, and generating a detection signal according to the first input voltage and the second input voltage;
A first output unit connected to the output terminal, the first input port, and the output port of the input unit, and generating the output voltage according to the first input voltage in response to a detection signal of a first state;
a second output unit connected to the output terminal, the second input port and the output port of the input unit and generating the output voltage according to the second input voltage in response to a detection signal of a second state,
The maximum voltage selection circuit selects one of the first output unit and the second output unit to be conducted according to the state of the detection signal, and provides the output voltage to a load terminal.
Preferably, the first state of the detection signal is a low level, and the second state is a high level.
Preferably, the aforementioned input unit includes:
a first transistor having a first end connected to the second input port and a control end connected to the first input port;
a first current source connected between the second end of the first transistor and ground;
And the input end of the first inverter is connected with the connection node of the first transistor and the first current source, the output end of the first inverter is used for providing the detection signal, the source end of the positive end is connected with the output end, and the negative power supply is grounded.
Preferably, in response to a sum of the first input voltage and the on voltage of the first transistor being smaller than the second input voltage, the first transistor is in an on state, and the input unit provides a detection signal of the first state.
Preferably, in response to the sum of the second input voltage and the on voltage of the first transistor being smaller than the first input voltage, the first transistor is in an off state, and the input unit provides the detection signal of the second state.
Preferably, the aforementioned first output unit includes:
the input end of the second inverter is connected with the output end of the first inverter, and the output end is used for providing an inversion signal of the detection signal;
A second transistor having a first terminal connected to the output port, a second terminal connected to the first input port, and a control terminal connected to an output terminal of the second inverter;
And the anode of the first diode is connected with the second end of the second transistor, and the cathode of the first diode is connected with the output port.
Preferably, the aforementioned second output unit includes:
A third transistor having a first terminal connected to the output port, a second terminal connected to the second input port, and a control terminal connected to the output terminal of the first inverter;
and a second diode having an anode connected to the second terminal of the third transistor and a cathode connected to the output port.
Preferably, any one of the first diode and the second diode is a schottky diode.
Preferably, any one of the first transistor, the second transistor, and the third transistor is a metal oxide semiconductor field effect transistor.
Preferably, the first transistor, the second transistor and the third transistor are P-type metal oxide semiconductor field effect transistors.
The maximum voltage selection circuit has the advantages that the maximum voltage selection circuit is provided with a first input port connected with a first input voltage, a second input port connected with a second input voltage and an output port for providing output voltage, the maximum voltage selection circuit further comprises an input unit connected with the first input port and the second input port and used for generating detection signals according to the first input voltage and the second input voltage, a first output unit connected with the output end of the input unit, the first input port and the output port and used for responding to the detection signals of a first state and used for generating the output voltage according to the first input voltage, and a second output unit connected with the output end of the input unit, the second input port and the output port and used for responding to the detection signals of a second state and used for generating the output voltage according to the second input voltage, and the maximum voltage selection circuit is used for selecting one of the first output unit and the second output unit to be conducted according to the state of the detection signals and used for providing the output voltage to a load end. Therefore, the maximum voltage selection circuit can realize the maximum voltage selection and effectively reduce the voltage drop loss, and the on-resistance of the transistor in the circuit is reduced by increasing the gate-source voltage Vgs of the transistor, so that the transistor with smaller W/L size can be used, the on-resistance the same as that of the prior art scheme is realized, the size of the transistor in the circuit can be reduced, the circuit area is reduced, and the manufacturing cost is reduced.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a three-way voltage maximum voltage selection circuit in the prior art;
FIG. 2 is a schematic diagram of another prior art maximum voltage selection circuit;
FIG. 3 shows a block diagram of a maximum voltage selection circuit provided by an embodiment of the present disclosure;
fig. 4 shows a circuit schematic of the maximum voltage selection circuit shown in fig. 3.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. The present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 3 is a block diagram illustrating a structure of a maximum voltage selection circuit according to an embodiment of the present disclosure, and fig. 4 is a circuit schematic of the maximum voltage selection circuit shown in fig. 3.
Referring to fig. 3 and 4, a maximum voltage selection circuit 300 is provided according to an embodiment of the present disclosure, the maximum voltage selection circuit 300 having a first input port connected to a first input voltage Vin1, a second input port connected to a second input voltage Vin2, and an output port providing an output voltage Vmax, and the maximum voltage selection circuit 300 further includes an input unit 310, a first output unit 320, and a second output unit 330,
The input unit 310 is connected to the first input port and the second input port, and generates a detection signal V2 according to the first input voltage Vin1 and the second input voltage Vin 2;
The first output unit 320 is connected to the output terminal of the input unit 310, the first input port and the output port, and generates the output voltage Vmax according to the first input voltage Vin1 in response to the detection signal V2 of the first state;
The second output unit 330 is connected to the output terminal of the input unit 310, the aforementioned second input port and the aforementioned output port, and generates the aforementioned output voltage Vmax based on the second input voltage Vin2 in response to the detection signal V2 of the second state,
The maximum voltage selection circuit 300 selects one of the first output unit 320 and the second output unit 330 to be turned on according to the state of the detection signal V2, and provides the output voltage Vmax to the load terminal.
Further, the first state of the detection signal V2 is low level, and the second state is high level.
Further, the input unit 310 includes at least a transistor Mp0, a current source I1 and an inverter 301,
The first end of the transistor Mp0 is connected to the second input port, the control end is connected to the first input port, the current source I1 is connected between the second end of the transistor Mp0 and the ground, the connection node of the transistor Mp0 and the current source I1 provides an intermediate node signal V1, the input end of the inverter 301 is connected to the connection node of the transistor Mp0 and the current source I1, the output end is used for providing the detection signal V2, the source end of the positive end is connected to the output port, and the negative power source is grounded.
In a specific implementation scenario, in response to the sum of the first input voltage Vin1 and the on voltage (Vth) of the transistor Mp0 being smaller than the second input voltage Vin2, the transistor Mp0 is in an on state, and the input unit 310 provides the detection signal V2 of the first state.
In another specific implementation scenario, in response to the sum of the second input voltage Vin2 and the on voltage (Vth) of the transistor Mp0 being smaller than the first input voltage Vin1, the transistor Mp0 is in an off state, and the input unit 310 provides the detection signal V2 in the second state.
Further, the aforementioned first output unit 320 includes an inverter 302, a transistor Mp1 and a diode D1,
The input end of the inverter 302 is connected to the output end of the inverter 301, the output end is used for providing an inverted signal V3 of the detection signal V2, the first end of the transistor Mp1 is connected to the output port, the second end is connected to the first input port, the control end is connected to the output end of the inverter 302, the positive electrode of the diode D1 is connected to the second end of the transistor Mp1, and the negative electrode is connected to the output port.
Further, the aforementioned second output unit 330 includes a transistor Mp2 and a diode D2,
The first end of the transistor Mp2 is connected to the output port, the second end is connected to the second input port, the control end is connected to the output end of the inverter 301, the positive electrode of the diode D2 is connected to the second end of the transistor Mp2, and the negative electrode is connected to the output port.
Further, any one of the aforementioned transistors Mp0, mp1 and Mp2 is a metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FILED EFFECT Transistor, abbreviated as MOS Transistor). More specifically, the aforementioned transistors Mp0, mp1 and Mp2 are PMOS transistors.
Further, in the present embodiment, the width-to-length ratio of the transistor Mp1 is the same as that of the transistor Mp2, and the on voltages of the transistor Mp1 and the transistor Mp2 are Vth. Of course, the present disclosure is not limited thereto, and in other alternative embodiments, the aspect ratio of the two may be other different combinations.
Further, any one of the diode D1 and the diode D2 is a schottky diode, and the forward turn-on voltages of the diode D1 and the diode D2 are the same, and are Vd. Of course, the disclosure is not limited thereto, and in other alternative embodiments, the diodes D1 and D2 may be other types of diodes, and the turn-on voltages of the two may be other different combinations.
According to the prior art maximum voltage selection circuit 200 shown in fig. 2, the closer the output voltage Vmax is to the second input voltage Vin2 (or the first input voltage Vin 1) for no voltage drop loss, the better. That is, the smaller the on-resistance Ron2 of the transistor Mp2 (the on-resistance Ron1 of the transistor Mp 1) is, the better. Ron of the transistor is inversely proportional to both W/L and gate-source voltage Vgs. When the first input voltage Vin1 is low, the transistor Mp2 is turned on, the gate-source voltage vgs=vmax-Vin 1, and when the second input voltage Vin2 is low, the transistor Mp1 is turned on, the gate-source voltage vgs=vmax-Vin 2. Here Vin1/Vin2 is constant, and for small Ron, only the W/L size can be increased, which results in an increase in circuit area and thus manufacturing cost.
In the maximum voltage selection circuit 300 provided in the embodiment of the present disclosure, when Vin1 is lower than Vin2-Vth, the transistor Mp0 is turned on to pull the potential of the intermediate node signal V1 to the second input voltage Vin2, and the output voltage is:
Vmax=Vin2-Vd (1)
Where Vd is the forward turn-on voltage of diode D2. Since the potential of the intermediate node signal V1 is higher than the potential of the output voltage Vmax, the voltage of the detection signal V2 is 0V, and the inverted signal V3 of the detection signal V2 is output as Vmax, and as a result, the transistor Mp1 is turned off and the transistor Mp2 is turned on, so that the second input voltage Vin2 is selected, and the output voltage at this time is:
Vmax=Vin2-Iload*Ron2 (2)
wherein Iload is the load current at the output terminal, ron2 is the on-resistance of transistor Mp 2.
Since the voltage of the detection signal V2 is 0V, the gate-source voltage vgs=vmax of the transistor Mp 2.
Similarly, when the second input voltage Vin2 is lower than Vin1-Vth, the transistor Mp0 is turned off, the potential of the intermediate node signal V1 is pulled to 0V by the current source I1, and the voltage of the detection signal V2 is:
V2=Vmax=Vin1-Vd (3)
where Vd is the forward turn-on voltage of diode D1. Meanwhile, the inverted signal V3 of the detection signal V2 is output as 0V, the transistor Mp2 is turned off, and the transistor Mp1 is turned on, so that the first input voltage Vin1 is selected, and at this time, the output voltage is:
Vmax=Vin1-Iload*Ron1 (4)
Wherein Iload is the load current at the output terminal, ron1 is the on-resistance of transistor Mp1. Since the voltage of the inverted signal V3 of the detection signal V2 is 0V, the gate-source voltage vgs=vmax of the transistor Mp1.
As can be seen from the comparison, the maximum voltage selection circuit 300 provided in the embodiment of the present disclosure increases the gate-source voltage Vgs of the transistor Mp 1/Mp 2 by the value of the first input voltage Vin1 or the second input voltage Vin 2. Therefore, the same on-resistance Ron as in the technical scheme shown in fig. 2 can be realized with a small W/L size. Thereby reducing the area of the integrated circuit and saving the manufacturing cost thereof.
In summary, the maximum voltage selection circuit 300 provided in the embodiment of the disclosure has a first input port connected to the first input voltage Vin1, a second input port connected to the second input voltage Vin2, and an output port for providing the output voltage Vmax, and the maximum voltage selection circuit 300 further includes an input unit 310 connected to the first input port and the second input port and generating the detection signal V2 according to the first input voltage Vin1 and the second input voltage Vin2, a first output unit 320 connected to the output terminal of the input unit 310, the first input port, and the output port and generating the output voltage Vmax according to the first input voltage Vin1 in response to the detection signal V2 in a first state, and a second output unit 330 connected to the output terminal of the input unit 310, the second input port, and the output port in response to the detection signal V2 in a second state, generating the output voltage Vmax according to the second input voltage Vin2, and the maximum voltage selection circuit 300 selecting one of the first output unit 320 and the output unit in a second state to the output terminal of the load 330 in response to the detection signal V2. Therefore, the maximum voltage selection circuit 300 can effectively reduce the voltage drop loss while realizing the maximum voltage selection, and reduces the on-resistance by increasing the gate-source voltage Vgs of the transistor (Mp 1/Mp 2) in the circuit, so that the transistor with smaller W/L size can be used to realize the same on-resistance as the prior art scheme (shown in fig. 2), thereby reducing the size of the transistor in the circuit, further reducing the integrated area of the circuit and reducing the manufacturing cost thereof.
It should be noted that although the device is described herein as an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be appreciated by those of ordinary skill in the art that conductivity type refers to a mechanism by which electrical conduction occurs, such as by hole or electron conduction, so conductivity type does not relate to doping concentration but rather to doping type, such as P-type or N-type. It will be appreciated by those of ordinary skill in the art that the terms "during", "when" and "when" as used herein in relation to circuit operation are not strict terms that refer to actions that occur immediately upon initiation of a start-up action, but rather there may be some small but reasonable delay or delays between them and the reactive action (reaction) initiated by the start-up action, such as various transmission delays and the like. The word "about" or "substantially" is used herein to mean that an element value (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation such that the value or position is difficult to strictly assume the stated value. It has been well established in the art that deviations of at least ten percent (10%) (at least twenty percent (20%)) for semiconductor doping concentrations are reasonable deviations from the exact ideal targets described. When used in connection with a signal state, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.
Furthermore, it should be noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Finally, it should be noted that the above-mentioned examples are given for the purpose of illustration only and are not intended to limit the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present disclosure.
Claims (8)
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855724A (en) * | 2005-04-28 | 2006-11-01 | 恩益禧电子股份有限公司 | Buffer circuit |
| CN202713256U (en) * | 2012-06-29 | 2013-01-30 | 快捷半导体(苏州)有限公司 | Largest voltage selection circuit and sub-selection circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2883625B2 (en) * | 1989-03-30 | 1999-04-19 | 株式会社東芝 | MOS type charging circuit |
| JP3138680B2 (en) * | 1998-03-13 | 2001-02-26 | 日本電気アイシーマイコンシステム株式会社 | Output buffer control circuit |
| US7339402B2 (en) * | 2006-02-13 | 2008-03-04 | Texas Instruments Incorporated | Differential amplifier with over-voltage protection and method |
| JP2009118620A (en) * | 2007-11-06 | 2009-05-28 | Okamoto Machine Tool Works Ltd | Counter electromotive force absorption circuit in inductor load driving circuit |
| KR101286241B1 (en) * | 2007-11-26 | 2013-07-15 | 삼성전자주식회사 | Maximum voltage source selector |
| US8947154B1 (en) * | 2013-10-03 | 2015-02-03 | Avogy, Inc. | Method and system for operating gallium nitride electronics |
| US9191001B2 (en) * | 2013-12-20 | 2015-11-17 | Cirrus Logic, Inc. | Transistor devices operating with switching voltages higher than a nominal voltage of the transistor |
| EP3206286A1 (en) * | 2016-02-10 | 2017-08-16 | GE Energy Power Conversion Technology Ltd | Gatespannungsübersteuerung für das schalten von stossströmen in igbt schaltern |
| DE102017212354B4 (en) * | 2017-07-19 | 2019-06-27 | Dialog Semiconductor (Uk) Limited | Low impedance load switch with output current control |
| CN108512536B (en) * | 2018-07-10 | 2023-11-28 | 上海艾为电子技术股份有限公司 | Analog switch with constant on-resistance |
-
2021
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855724A (en) * | 2005-04-28 | 2006-11-01 | 恩益禧电子股份有限公司 | Buffer circuit |
| CN202713256U (en) * | 2012-06-29 | 2013-01-30 | 快捷半导体(苏州)有限公司 | Largest voltage selection circuit and sub-selection circuit |
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