CN114792685B

CN114792685B - Semiconductor memory structure and method for forming the same

Info

Publication number: CN114792685B
Application number: CN202110110180.9A
Authority: CN
Inventors: 王喻柏; 简毅豪; 刘祥伯
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2021-01-26
Filing date: 2021-01-26
Publication date: 2024-11-22
Anticipated expiration: 2041-01-26
Also published as: CN114792685A

Abstract

The semiconductor memory structure comprises a semiconductor substrate, wherein the semiconductor substrate comprises an active region and a cut-off region, the semiconductor memory structure further comprises an isolation structure arranged in the cut-off region, a first gate structure at least extending through the isolation structure in the cut-off region, and a second gate structure at least extending through the active region, the semiconductor memory structure further comprises a doped region arranged in the active region, and the distance between the doped region and the first gate structure is smaller than the distance between the doped region and the second gate structure.

Description

Semiconductor memory structure and forming method thereof

Technical Field

The present application relates to a semiconductor memory structure and a method for forming the same, and more particularly to a dynamic random access memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) devices are widely used in consumer electronics. In order to increase the device density and improve the overall performance within a dram device, current dram device fabrication techniques continue to strive toward the miniaturization of device dimensions. However, as device sizes continue to shrink, many challenges are presented. For example, the source/drain junction leakage current (junction leakage) is improved. Accordingly, there remains a need for improved methods of manufacturing DRAM devices that overcome the problems associated with reduced device sizes.

Disclosure of Invention

The embodiment of the invention provides a semiconductor memory structure. The semiconductor memory structure comprises a semiconductor substrate comprising an active region and a blocking region. The semiconductor memory structure further includes an isolation structure disposed in the blocking region, a first gate structure extending at least through the isolation structure in the blocking region, and a second gate structure extending at least through the active region. The semiconductor memory structure further comprises a doped region arranged in the active region, wherein the distance between the doped region and the first gate structure is smaller than the distance between the doped region and the second gate structure.

The embodiment of the invention provides a method for forming a semiconductor memory structure, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a cutting-off region and an active region. The method also includes forming a first trench-passing blocking region and forming a second trench-passing active region, and forming a patterned masking layer covering a portion of the second trench-passing active region, the patterned masking layer having an opening exposing a portion of the first trench-passing blocking region. The method further includes performing an ion implantation process using the patterned masking layer to form a doped region in the active region, and forming a first gate structure in the first trench and a second gate structure in the second trench.

Drawings

In order to make the features and advantages of the present invention more comprehensible, various embodiments accompanied with figures are described in detail below:

FIGS. 1A-1K are schematic plan views illustrating various stages in forming a semiconductor memory structure, in accordance with some embodiments of the present invention;

FIGS. 1A-1 through 1K-1 and FIGS. 1A-2 through 1K-2 are schematic cross-sectional views illustrating various stages in the formation of a semiconductor memory structure, in accordance with some embodiments of the present invention;

fig. 1K-3 are enlarged schematic views of fig. 1K-2 to illustrate additional details of the semiconductor memory structure.

[ Description of the symbols ]

102 Semiconductor substrate

104 Active area

106 Isolation region

108 Truncated area

110 Isolation structure

112 Lining layer

114 Insulating material

116 Dielectric layer

118 Patterning mask layer

120 Opening pattern

122 Groove(s)

124 Filling material

126 Patterning mask layer

128 Opening pattern

130 Part of

132 Adulterant(s)

134 Doped region

136 Gate dielectric layer

138 Gate liner

140 Gate electrode layer

142 Grid structure

142A portions of the gate structure 142 that pass through the active region 104

142C gate structure 142 passes through portions of isolation structure 110 in the intercepting region 108

144 Concave shape

146 Capping layer

148 Source/drain regions

150 Source/drain regions

152 Contact plug

154 Bit line

158 Dielectric structure

160 Contact plug

160L lower portion of contact plug 160

160U upper portion of contact plug 160

D1 first direction

D2, second direction

D3 third direction

A1 size

A2 size

A3 distance

A4 distance

A5 depth

A6 depth

Detailed Description

The present application will be described more fully hereinafter with reference to the accompanying drawings of embodiments of the application. However, the application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity and the same or similar reference numbers denote the same or similar elements in the various drawings.

Fig. 1A-1K are schematic plan views illustrating various stages in forming a semiconductor memory structure, according to some embodiments of the invention. For ease of illustration, fig. 1A to 1K show reference directions, wherein the first direction D1 is a channel extending direction, the second direction D2 is a word line extending direction (or gate extending direction), and the third direction D3 is a bit line extending direction. The first direction D1 and the second direction D2 may have an acute angle therebetween, for example, in the range of about 10 degrees to about 80 degrees. The second direction D2 is substantially perpendicular to the third direction D3.

Fig. 1A to 1K also indicate reference cross sections, the cross section A-A being the plane parallel to the axial direction of the active region (i.e. the first direction D1) and passing through the active region, and the cross section B-B being the plane parallel to the axial direction of the gate structure (i.e. the second direction D2) and passing through the gate structure.

FIGS. 1A-1 through 1K-1 are schematic cross-sectional views of a semiconductor memory structure taken along the cross-section A-A of FIGS. 1A-1K. FIGS. 1A-2 through 1K-2 are schematic cross-sectional views of a semiconductor memory structure taken along the cross-section B-B of FIGS. 1A through 1K.

A semiconductor memory structure 100 is provided, the semiconductor memory structure 100 comprising a semiconductor substrate 102, as shown in fig. 1A, 1A-1 and 1A-2. The semiconductor substrate 102 includes an active region 104, an isolation region 106, and a blocking region (chop region) 108. The active regions 104 are semiconductor blocks extending along the first direction D1, and each active region 104 is defined by two isolation regions 106 and two cut-off regions 108. Isolation structures 110 are formed in the isolation regions 106 and the blocking regions 108 of the semiconductor substrate 102 so as to surround and electrically isolate the active regions 104.

The isolation regions 106 extend along the first direction D1 and are spaced apart in the second direction D2, thereby dividing the semiconductor substrate 102 into a plurality of semiconductor stripes (not shown). The intercepting region 108 (shown in phantom) is disposed corresponding to the semiconductor stripe and intercepts the semiconductor stripe into a plurality of active regions 104. In the second direction D2, adjacent truncated regions 108 may be offset or non-overlapping.

In some embodiments, the semiconductor substrate 102 is an elemental semiconductor substrate, such as a silicon substrate, or a germanium substrate; or a compound semiconductor substrate such as a silicon carbide substrate, or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

The isolation structures 110 extend downward from the upper surface of the semiconductor substrate 102. The formation of the isolation structures 110 may include, for example, forming trenches corresponding to the isolation regions 106 in the semiconductor substrate 102 using a first patterning process (including a photolithography process and an etching process), and dividing a plurality of semiconductor stripes. Next, a second patterning process (including a photolithography process and an etching process) is used to form trenches corresponding to the intercepting regions 108 and to intercept the semiconductor stripes into a plurality of active regions 104.

The formation of isolation structure 110 may also include forming liner 112 along the sidewalls and bottom of the trench and along the upper surface of semiconductor substrate 102, followed by forming insulating material 114 to overfill the remainder of the trench. An insulating material 114 is nested within the liner 112. Liner 112 is formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable materials, and/or combinations of the foregoing. The insulating material 114 is formed of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), other suitable material, and/or combinations of the foregoing. The insulating material 114 and the liner 112 may be formed of different materials. For example, liner 112 is a silicon oxide layer and insulating material 114 is a silicon nitride layer.

The formation of the isolation structure 110 may also include performing a planarization process (e.g., a back etch process) to remove the insulating material 114 formed over the upper surface of the semiconductor substrate 102 until the liner 112 is exposed. After planarization, a gap may be formed at the upper surface of the insulating material 114, particularly at the upper surface of the insulating material 114 within the wider trench. A dielectric layer 116 may be formed over the upper surface of the semiconductor substrate 102 and fills the gap. Dielectric layer 116 may be a silicon oxide layer formed using atomic layer deposition (atomic layer deposition, ALD).

A patterned masking layer 118 is formed over the upper surface of the semiconductor substrate 102, as shown in fig. 1B, 1B-1, and 1B-2. The patterned mask layer 118 has an opening pattern 120, and the opening pattern 120 extends along the second direction D2. In some embodiments, the patterned masking layer 118 may be a hard mask structure formed of one or more layers of dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable materials, and/or combinations of the foregoing. During formation of the patterned masking layer 118, portions of the dielectric layer 116 exposed from the opening pattern 120 may be removed.

The semiconductor memory structure 100 is subjected to an etching process using the patterned masking layer 118 to remove portions of the semiconductor memory structure 100 not covered by the patterned masking layer 118. The opening pattern 120 of the patterned masking layer 118 is transferred into the active region 104 of the semiconductor substrate 102 and the isolation structure 110 to form a trench 122, as shown in fig. 1C, 1C-1 and 1C-2. The etch depth of trench 122 may be different in active region 104 and isolation structure 110. The grooves 122 extend along the second direction D2 and are aligned in the third direction D3. Trenches 122 extend alternately through the active regions 104 and the isolation structures 110, two trenches 122 extending through one active region 104, and two trenches 122 extending through the intercepting region 108 on either side of that active region 104.

The dimension of the trench 122 in the third direction D3 needs to be smaller than the dimension of the intercepting region 108 in the third direction D3. The etch process that forms trench 122 removes portions of insulating material 114 and liner 112 of isolation structure 110 is exposed from trench 122 in the termination region 108 after the etch process. If the dimension of the trench 122 in the third direction D3 is too large, the thickness of the liner 112 may be too thin or completely vanish after the etching process, thereby adversely affecting the electrical properties (e.g., on-current) of the resulting semiconductor memory device. If the dimensions of the trench 122 in the third direction D3 are too small, the amount of electrode material that is subsequently filled in the trench 122 may be reduced.

A fill material 124 is formed over the semiconductor memory structure 100 as shown in fig. 1D, 1D-1 and 1D-2. A fill material 124 is formed over the patterned masking layer 118 and seals the trench 122. An upper portion of the trench 122 is filled with a filling material 124, and a lower portion of the trench 122 remains unfilled. In some embodiments, the filler material 124 is formed of a carbon-containing material, such as Diamond-like carbon (DLC), a high selectivity transparent (HIGH SELECTIVITY TRANSPARENCY, HST) carbon film, or the like. The fill material 124 is configured to provide a substantially planar upper surface over which a patterned masking layer is subsequently formed.

Next, a patterned masking layer 126 is formed over the fill material 124. The patterned masking layer 126 has a plurality of opening patterns 128 that correspond to the intercepting region 108 of the semiconductor substrate 102 and expose the fill material 124. The patterned masking layer 126 may be a patterned photoresist layer. The same reticle (reticle) may be used for the photolithography process to form patterned masking layer 126 and the photolithography process to form cut-off region 108. In other embodiments, the patterned mask layer 126 may be a patterned hard mask layer.

Using the patterned mask layer 126, an etching process is performed on the filling material 124 to remove portions of the filling material 124 exposed by the opening pattern 128, thereby opening the trenches 122 sealed by the filling material 124. After the etching process, the trench 122 is exposed from the fill material 124 and the patterned masking layer 126 through portions (denoted 130) of the intercepting region 108, as shown in fig. 1E, 1E-1, and 1E-2.

An ion implantation process is performed on the semiconductor memory structure 100 using the patterned masking layer 126 and the patterned fill material 124 to form doped regions 134 in the active region 104, as shown in fig. 1F, 1F-1 and 1F-2. The tilt angle of the ion implantation process may range from about 5 degrees to about 20 degrees. During the ion implantation process, dopants 132 pass through the liner 112 of the isolation structure 110 through the opening pattern 128 of the patterned masking layer 126 and the opening pattern of the patterned fill material 124, and are then implanted into the semiconductor material of the active region 104, thereby forming doped regions 134 at the sides of the active region 104 facing the intercepting region 108. Dopant 132 may be a p-type dopant (e.g., boron or BF 2) or an n-type dopant (e.g., phosphorus or arsenic).

Doped region 134 is configured to balance the conductive carriers induced by the bypass word line passing word line, as will be described in more detail below. The doped region 134 may have a conductivity type that is the same as the conductivity type of the active region 104 of the semiconductor substrate 102, e.g., both are p-type. The doping concentration of the doped region 134 is greater than the doping concentration of the active region 104 of the semiconductor substrate 102. For example, the doping concentration of doped region 134 is about 1 to 2 orders of magnitude higher than the doping concentration of active region 104.

After the ion implantation process, the patterned masking layer 126 and the fill material 124 are removed using an ashing process or an etching process to expose the patterned masking layer 118 and to open other portions of the trenches 122, as shown in fig. 1G, 1G-1, and 1G-2.

A gate dielectric layer 136, a gate liner layer 138, and a gate electrode layer 140 are sequentially formed over the semiconductor memory structure 100, as shown in fig. 1H, 1H-1, and 1H-2. A gate dielectric layer 136 is formed along the sidewalls of the patterned masking layer 118 and the sidewalls and bottom of the trench 122 to partially fill the trench 122. In some embodiments, gate dielectric layer 136 is formed of silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, and/or a combination of the foregoing. In some embodiments, the gate dielectric layer 136 is formed using in-situ vapor generation (in-situ steam generation, ISSG), atomic Layer Deposition (ALD), chemical vapor deposition (chemical vapor deposition, CVD), or a combination of the foregoing.

A gate liner 138 is formed over gate dielectric 136 and partially fills trench 122. In some embodiments, gate liner 138 is formed of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), other suitable materials, and/or combinations of the foregoing. The gate liner 138 may be deposited using Physical Vapor Deposition (PVD), and/or Atomic Layer Deposition (ALD).

A gate electrode layer 140 is formed over gate liner 138 and overfills the remainder of trench 122. In some embodiments, the gate electrode layer 140 is formed of a metallic material, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), other suitable materials, and/or combinations of the foregoing. The gate electrode layer 140 may be deposited using Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), and/or Atomic Layer Deposition (ALD).

According to some embodiments, the gate electrode layer 140 and the gate liner layer 138 are subjected to an etching process to form a recess 144 extending into the semiconductor substrate 102, as shown in fig. 1I, 1I-1, and 1I-2. After the etching process, a gate structure 142 is formed. The gate structure 142 may be used as a word line of the resulting semiconductor memory device, and may also be referred to as a Buried Word Line (BWL).

Each gate structure 142 extends alternately through the active region 104 and the isolation structure 110, two gate structures 142 extend through a single active region 104, and two gate structures 142 extend through the intercepting region 108 on either side of this active region 104. The gate structure 142 includes a gate dielectric layer 136, a gate liner 138, and a gate electrode layer 140. The gate liner 138 has a U-shaped profile and lines between the gate dielectric 136 and the gate electrode 140. The gate electrode layer 140 is nested within the gate liner 138. In addition, the upper surfaces of the gate liner 138 and the gate electrode 140 are at a higher level than the bottom surface of the doped region 134.

Cap layer 146 is formed in recess 144 as shown in fig. 1J, 1J-1 and 1J-2. In some embodiments, cap layer 146 is formed from a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, and/or combinations of the foregoing. Forming the cap layer 146 may include depositing a dielectric material to fill the recess 144 and performing a planarization process to remove the dielectric material formed on the upper surface of the patterned masking layer 118.

According to some embodiments, source/drain regions 148 and 150 are formed in the active region 104 of the semiconductor substrate 102 by an ion implantation process, as shown in fig. 1K-1. Source/drain regions 150 are located in the center of active region 104, and source/drain regions 148 are located at both ends of active region 104. The source/drain regions 148 and 150 and the portion of the gate structure 142 extending through the active region 104 may be combined to form a transistor, e.g., an n-type transistor or a p-type transistor, for use in a resulting semiconductor memory device.

The source/drain regions 148 and 150 are doped and a PN junction (PN junction) is formed between the active region 104 and the source/drain region 148 or 150. The source/drain regions 148 and 150 are of opposite conductivity type to the active region 104 of the semiconductor substrate 102 and opposite conductivity type to the doped region 134. For example, the active region 104 and the doped region 134 are p-type, while the source/drain regions 148 and 150 are n-type. The doping concentration of source/drain regions 148 and 150 may be greater than the doping concentration of doped region 134. For example, the doping concentration of source/drain regions 148 and 150 is about 1 to 2 orders of magnitude higher than the doping concentration of doped region 134. In addition, the bottom surfaces (i.e., the PN junctions described above) of the source/drain regions 148 and 150 may be at a lower level than the top surfaces of the gate liner 138 and the gate electrode layer 140.

Dielectric structure 158 may be formed over semiconductor memory structure 100 and conductive features may be formed in dielectric structure 158 to electrically couple source/drain regions 148 and 150. For example, as shown in fig. 1K, 1K-1 and 1K-2, a contact plug 152 is formed on the source/drain region 150; forming a bit line 154 over the contact plug 152; and forming contact plugs 160 on the source/drain regions 148 and the doped regions 134. During formation of the dielectric structure 158 and the conductive features, the dielectric layer 116, the patterned masking layer 118, and the cap layer 146 over the upper surface of the semiconductor substrate 102 may be removed.

In some embodiments, dielectric structure 158 comprises multiple dielectric layers and is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, multiple layers of the foregoing, and/or combinations of the foregoing.

In some embodiments, contact plugs 152 extend partially into semiconductor substrate 102 and fall on source/drain regions 150. The contact plug 152 may be formed of a semiconductor material, such as polysilicon.

In some embodiments, the bit line 154 extends along the third direction D3 and is electrically coupled to the source/drain region 150 through the contact plug 152. Bit line 154 may be formed of a metal or metal nitride, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), other suitable materials, multilayers of the foregoing, or combinations of the foregoing. A silicide layer may be formed between the bit line 154 and the contact plug 152.

In some embodiments, contact plugs 160 fall on source/drain regions 148 and doped regions 134. The contact plug 160 may include a lower portion 160L and an upper portion 160U. For example, the lower portion 160L of the contact plug 160 is formed of a semiconductor material, such as polysilicon. The upper portion 160U of the contact plug 160 is formed of a metal or metal nitride, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), other suitable materials, a plurality of layers of the foregoing, or a combination of the foregoing. A silicide layer may be formed between the lower portion 160L and the upper portion 160U of the contact plug 160.

Fig. 1K-3 are enlarged schematic views of fig. 1K-2 to illustrate additional details of the semiconductor memory structure 100. As shown in fig. 1K-3, the portion of gate structure 142 that passes through isolation structure 110 in the intercepting region 108 is denoted as 142C, and the portion of gate structure 142 that passes through active region 104 is denoted as 142A. In some cases, during operation, the portion 142C of the gate structure 142 extending through the blocking region 108 (which may be referred to as a bypass word line) may induce conductive carriers (e.g., electrons or holes) in the active region 104 adjacent thereto (or on the sidewalls of the isolation structure 110) to form a channel layer. This channel layer is undesirable and may provide various leakage paths, such as contact plugs from source/drain regions 148 to source/drain regions 150, and/or other conductive features, resulting in degradation or loss of stored data in the semiconductor memory device.

In accordance with an embodiment of the present invention, since the dopant in doped region 134 provides a conductive carrier (e.g., a hole or electron) opposite to the conductive carrier induced by bypass word line 142C, doped region 134 balances the conductive carrier induced by bypass word line 142C, thereby reducing the likelihood of leakage path formation. Therefore, the reliability and the manufacturing yield of the semiconductor memory device are improved.

In addition, source/drain regions 148 may be formed to overlap portions of doped region 134 (the overlap portions are shown in phantom). Doped region 134 has a width A1 along a first direction D1 and source/drain regions 148 have a dimension A2 along the first direction D1. The ratio of the dimension A1 of the doped region 134 to the dimension A2 of the source/drain region 148 ranges from about 0.01 to about 0.05. If the ratio of width A1 to width A2 is too large, the doped region 134 may negatively affect the electrical properties (e.g., on-current) of the resulting semiconductor memory device. If the ratio of width A1 to width A2 is too small, doped region 134 may not be sufficient to balance the conductive carriers induced by the bypass word line.

Doped region 134 and gate structure 142 have a distance A3 between (gate dielectric 136 of) portion 142C in the intercepting region 108, while doped region 134 and gate structure 142 have a distance A4 between (gate dielectric 136 of) portion 142A of active region 104, and distance A3 is less than distance A4. The ratio of distance A3 to distance A4 ranges from about 0.01 to about 0.05. If the ratio of distance A3 to distance A4 is too large, the doped region 134 may negatively affect the electrical properties (e.g., on-current) of the resulting semiconductor memory device. If the ratio of distance A3 to distance A4 is too small, doped region 134 may not be sufficient to balance the conductive carriers induced by the bypass word line.

The top surface of doped region 134 is coplanar with the top surface of cap layer 146. The bottom surface of doped region 134 is at a lower level than the bottom surface of source/drain region 148. That is, the depth A5 of the doped region 134 is greater than the depth A6 of the source/drain region 148. The ratio of the depth A5 of the doped region 134 to the depth A6 of the source/drain region 148 ranges from about 1.25 to about 1.5. If the ratio of depth A5 to depth A6 is too large, dopants may undesirably implant into other regions of semiconductor substrate 102, such as peripheral circuit regions, during the ion implantation process that forms doped region 134. If the ratio of depth A5 to depth A6 is too small, doped region 134 may not be sufficient to balance the conductive carriers induced by the bypass word line.

Additional components may be formed over semiconductor memory structure 100, thereby producing a semiconductor memory device. For example, a capacitor structure (not shown) may be formed over the dielectric structure 158 and electrically coupled to the source/drain regions 148 through the contact plugs 160. In some embodiments, the semiconductor memory device is a Dynamic Random Access Memory (DRAM).

According to the embodiment of the invention, the doped region is formed at the side edge of the active region facing the bypass word line, and the doped region can balance the conductive carriers induced by the bypass word line, so that the possibility of forming a leakage path is reduced. Therefore, the reliability and the manufacturing yield of the semiconductor memory device are improved.

Although the present invention has been described in terms of the foregoing embodiments, it is not limited thereto. The present invention can be modified and modified to be slightly more than necessary without departing from the scope of the present invention.

Claims

1. A semiconductor memory structure, comprising:

A semiconductor substrate including an active region and a truncation region;

an isolation structure disposed in the cut-off region;

a first gate structure extending at least through the isolation structure in the truncation region;

a second gate structure extending at least through the active region;

a doped region disposed in the active region, wherein a first distance between the doped region and the first gate structure is smaller than a second distance between the doped region and the second gate structure; and

A capping layer is disposed on the first gate structure, wherein a portion of the isolation structure is between the capping layer and the doped region.

2. The semiconductor memory structure according to claim 1, further comprising:

A source/drain region is disposed in the active region and between the second gate structure and the isolation structure, wherein the doped region is between the source/drain region and the isolation structure.

3 . The semiconductor memory structure according to claim 2 , wherein the doped region has a first conductivity type, and the source/drain region has a second conductivity type opposite to the first conductivity type.

4 . The semiconductor memory structure according to claim 2 , wherein a bottom surface of the doped region is lower than a bottom surface of the source/drain region.

5. The semiconductor memory structure according to claim 2, further comprising:

A contact plug is disposed on the source/drain region and the doped region.

6 . The semiconductor memory structure according to claim 2 , wherein the doping concentration of the source/drain region is greater than the doping concentration of the doping region.

7. The semiconductor memory structure according to claim 1 is characterized in that the isolation structure comprises: a liner and an insulating material arranged on the liner, wherein the liner of the isolation structure is between the first gate structure and the doped region, and the liner of the isolation structure is between the cap layer and the doped region.

8 . The semiconductor memory structure according to claim 7 , wherein a top surface of the doped region is coplanar with a top surface of the cap layer.

9 . The semiconductor memory structure according to claim 1 , wherein a bottom surface of the doped region is lower than an upper surface of a gate electrode layer of the first gate structure.

10. A method for forming a semiconductor memory structure, comprising:

Providing a semiconductor substrate, the semiconductor substrate comprising a truncation region and an active region;

forming a first trench through the cut-off region and forming a second trench through the active region;

Forming a patterned mask layer to cover a portion of the second trench passing through the active region, wherein the patterned mask layer has an opening exposing a portion of the first trench passing through the cut-off region;

Performing an ion implantation process using the patterned mask layer to form a doped region in the active region; and

A first gate structure is formed in the first trench and a second gate structure is formed in the second trench.

11. The method for forming a semiconductor memory structure according to claim 10, further comprising:

An isolation structure is formed in the cut-off region, wherein the first gate structure extends through the isolation structure in the cut-off region.

12. The method for forming a semiconductor memory structure according to claim 10, further comprising:

A source/drain region is formed in the active region, wherein the doped region has a first conductivity type, and the source/drain region has a second conductivity type opposite to the first conductivity type.

13. The method for forming a semiconductor memory structure according to claim 10, further comprising:

forming a filling material to seal the first trench and the second trench, wherein the patterned mask layer is formed on the filling material; and

The filling material is etched using the patterned mask layer so that a portion of the first trench passing through the cut-off region is exposed from the filling material.