CN114792622A - Silicon wafer processing method and silicon wafer - Google Patents
Silicon wafer processing method and silicon wafer Download PDFInfo
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- CN114792622A CN114792622A CN202210733112.2A CN202210733112A CN114792622A CN 114792622 A CN114792622 A CN 114792622A CN 202210733112 A CN202210733112 A CN 202210733112A CN 114792622 A CN114792622 A CN 114792622A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 164
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 164
- 239000010703 silicon Substances 0.000 title claims abstract description 164
- 238000003672 processing method Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 52
- 238000005498 polishing Methods 0.000 claims abstract description 34
- 238000000227 grinding Methods 0.000 claims abstract description 21
- 239000007888 film coating Substances 0.000 claims abstract description 12
- 238000009501 film coating Methods 0.000 claims abstract description 12
- 238000007517 polishing process Methods 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 124
- 238000005520 cutting process Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 5
- 238000005070 sampling Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000007665 sagging Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004570 mortar (masonry) Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011221 initial treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B29/00—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents
- B24B29/02—Machines or devices for polishing surfaces on work by means of tools made of soft or flexible material with or without the application of solid or liquid polishing agents designed for particular workpieces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
- B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
- B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
- B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The embodiment of the invention discloses a silicon wafer processing method, which comprises the following steps: performing film coating processing on the silicon wafer subjected to the first chamfering processing and grinding processing; carrying out double-sided polishing processing on the silicon wafer after the film coating processing; and carrying out secondary chamfering processing on the silicon wafer subjected to double-side polishing processing. The embodiment of the invention provides a method for processing a silicon wafer; the silicon wafer processing method improves the problem of silicon wafer edge collapse through two aspects: on one hand, the silicon wafer processing method comprises the steps of carrying out film coating processing on a silicon wafer, so that a layer of oxidation film can be deposited on the surface and the edge of the silicon wafer, and the oxidation film can play a role in protecting the silicon wafer, particularly the edge part of the silicon wafer; on the other hand, according to the silicon wafer processing method, the second chamfering processing is performed after the double-side polishing processing is performed on the silicon wafer, so that the edge collapse part of the silicon wafer caused in the double-side polishing processing process of the previous working procedure can be removed through the chamfering process, and the problem of edge collapse of the silicon wafer is solved.
Description
Technical Field
The invention relates to the technical field of semiconductor production, in particular to a silicon wafer processing method and a silicon wafer.
Background
The silicon chip is a material for manufacturing semiconductor elements, and generally, after remelting, pulling, slicing, chamfering, grinding, polishing, cleaning and other processes are carried out on polycrystalline silicon, the chip-level silicon chip with a smooth and flat surface and regular edges can be obtained. With the increasing diameter of silicon wafers and the decreasing feature size of integrated circuits, higher requirements are put forward on the flatness of the surfaces of the wafers, the cleanness of the surfaces and the degree of damage. In semiconductor processing technology, surface planarization is an important technique for high density lithography because scattering during exposure can be avoided without a planar surface with undulations.
However, during the processing of the silicon wafer, the peripheral edge of the silicon wafer may collapse after being ground and polished, and especially during the double-side polishing, the peripheral edge of the silicon wafer is ground more by the mechanical action of the polishing pad and the chemical action of the polishing solution, and finally the peripheral edge of the silicon wafer collapses.
Disclosure of Invention
In order to solve the technical problem, embodiments of the present invention are expected to provide a silicon wafer processing method and a silicon wafer, which can improve the edge collapse phenomenon of the silicon wafer during the processing process, thereby improving the planarization quality of the silicon wafer.
The technical scheme of the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a silicon wafer processing method, where the silicon wafer processing method includes: performing film coating processing on the silicon wafer subjected to the first chamfering processing and grinding processing; carrying out double-sided polishing processing on the silicon wafer after the film coating processing; and carrying out secondary chamfering processing on the silicon wafer subjected to double-side polishing processing.
In a second aspect, embodiments of the present invention provide a silicon wafer obtained by using the silicon wafer processing method according to the first aspect.
The embodiment of the invention provides a silicon wafer processing method and a silicon wafer; the silicon wafer processing method improves the problem of silicon wafer edge collapse through two aspects: on one hand, the silicon wafer processing method comprises the steps of carrying out film coating processing on a silicon wafer, so that a layer of oxidation film can be deposited on the surface and the edge of the silicon wafer, and the oxidation film can play a role in protecting the silicon wafer, particularly the edge part of the silicon wafer; on the other hand, according to the silicon wafer processing method, the second chamfering processing is performed after the double-side polishing processing is performed on the silicon wafer, so that the edge collapse part of the silicon wafer caused in the double-side polishing processing process of the previous working procedure can be removed through the chamfering process, and the problem of edge collapse of the silicon wafer is solved.
Drawings
FIG. 1 shows a graph of thickness variation for a silicon wafer processed using a conventional silicon wafer processing method;
FIG. 2 is a schematic diagram showing an ERO index for evaluating the amount of sag of the edge of a silicon wafer;
FIG. 3 is a flow chart of a method for processing a silicon wafer according to an embodiment of the present invention;
FIG. 4 is a schematic view showing a chamfered shape of a silicon wafer subjected to a second chamfering process;
FIG. 5 is a schematic view showing another chamfering shape of a silicon wafer subjected to the second chamfering process;
FIG. 6 is a flow chart illustrating a method for processing a silicon wafer according to another embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
In the conventional silicon wafer processing process, firstly, a silicon rod is cut into silicon wafers with certain thickness by using a linear cutting process, specifically, the silicon wafers with certain thickness are cut by using the linear cutting process, namely, a cutting line is wound on a guide wheel, the guide wheel drives the cutting line to move, mortar is sprayed to the cutting line while cutting, the mortar is tightly pressed on the silicon rod by the cutting line, and unidirectional or reciprocating cutting movement is carried out relative to the silicon rod, so that grinding type cutting is completed, and the silicon rod is cut into pieces. However, the silicon wafer obtained by wire cutting has large surface roughness and generally has the problems of bending, warping and the like, and the thickness of different silicon wafers is often different greatly and the thickness consistency is poor. Based on the above problems, the silicon wafer needs to be processed by multiple processes in the following process to improve the quality of the silicon wafer.
However, if the process sequence is not properly arranged during the subsequent processing, the flatness of the wafer after further processing, particularly the flatness of the edge of the wafer, may be reduced, and even the outer circumference of the wafer may be sagged.
As shown in fig. 1, taking 3 silicon wafers processed by the current processing method as an example, sampling points are selected in a range from a position 100mm away from the center of a circle on the surface of the silicon wafer to the outer circumference of the silicon wafer, the thickness of the silicon wafer at the sampling points is measured, and finally a silicon wafer thickness change curve graph is drawn according to the measurement result, so that the trend of the silicon wafer thickness change can be seen from fig. 1, and obvious edge collapse can be seen at the outer circumferential edge of the silicon wafer, which means that the flatness of the edge of the silicon wafer is not good. Fig. 2 is a schematic diagram showing a graph of a calculation method of an indicator ERO (Edge roll-off) for evaluating the sag amount of the Edge of the silicon wafer, in which the abscissa of the graph is the distance of the sampling point from the Edge of the silicon wafer and the ordinate is the displacement amount of the sampling point from the reference plane.
In order to solve the problem of poor flatness, especially edge sag, of the edge of the silicon wafer, referring to fig. 3, an embodiment of the present invention provides a silicon wafer processing method, which may include:
s101: carrying out film coating processing on the silicon wafer subjected to the first chamfering processing and grinding processing;
s102: carrying out double-sided polishing processing on the silicon wafer after the film coating processing;
s103: and carrying out secondary chamfering processing on the silicon wafer subjected to double-side polishing processing.
According to the silicon wafer processing method provided by the embodiment of the invention, the silicon wafer cut from the silicon rod is firstly subjected to the first chamfering processing, specifically, the edge of the silicon wafer is subjected to primary treatment by grinding processing by utilizing the relative rotation motion of the grinding wheel and the silicon wafer, so that the edge breakage or chipping in the rough grinding process is prevented. The silicon wafer after the first chamfering process is then subjected to a rough grinding and fine grinding process, wherein the rough grinding process and the fine grinding process can remove a difference in thickness of the silicon wafer, and preferably, a re-etching process is additionally performed on the silicon wafer after the rough grinding process and a light etching process is additionally performed on the silicon wafer after the fine grinding process, wherein the re-etching process and the light etching process can remove processing deformation or contaminants caused by the first chamfering process and grinding as described above.
In order to protect the surface and the edge of the silicon wafer so that the silicon wafer can continue to undergo subsequent processing, the silicon wafer which undergoes grinding processing and etching processing is subjected to film coating processing, namely, an oxide film is formed on the surface and the edge of the silicon wafer in a deposition mode.
The silicon wafer after the plating process is then subjected to a double-side polishing process to make the surface of the silicon wafer a mirror surface. Specifically, the silicon wafer is supported by a double-side polishing apparatus, a polishing cloth is attached to an upper surface plate and a lower surface plate of the double-side polishing apparatus, the silicon wafer is sandwiched therebetween, and then, a polishing liquid is supplied to a polishing surface, and the surface plates of the silicon wafer are mirror-polished by rotating the surface plates.
However, the above-mentioned double-side polishing process may cause edge roll off of the silicon wafer edge because the polishing pad and the polishing solution may generate mechanical friction and chemical action on the silicon wafer edge, and specifically, the polishing pad, which is made of a flexible material, may cover the silicon wafer edge after receiving pressure, and the polishing solution is easily accumulated at the silicon wafer edge, which all results in more edge grinding.
In order to remove the sagging, the embodiment of the present invention proposes to perform the second chamfering process after the first chamfering, grinding, plating, and double-side polishing processes, and since the removal amount of the second chamfering process is large and the influence on the diameter is large, it is possible to remove the sagging portion by removing the outer circumference of the silicon wafer of a certain width through the second chamfering process, thereby improving the sagging situation.
According to the embodiment of the present invention, after the silicon wafer is subjected to the second chamfering process, the edge of the silicon wafer can take two forms, specifically, referring to fig. 4 and 5, wherein the silicon wafer shown in fig. 4 has an R-shaped chamfer and the silicon wafer shown in fig. 5 has a T-shaped chamfer, which can be selected according to the requirements of customers in actual operation.
In summary, the embodiment of the invention provides a silicon wafer processing method; the silicon wafer processing method improves the problem of silicon wafer edge collapse through two aspects: on one hand, the silicon wafer processing method comprises the steps of carrying out film coating processing on a silicon wafer, so that a layer of oxidation film can be deposited on the surface and the edge of the silicon wafer, and the oxidation film can play a role in protecting the silicon wafer, particularly the edge part of the silicon wafer; on the other hand, according to the silicon wafer processing method, the second chamfering processing is performed after the double-side polishing processing is performed on the silicon wafer, so that the edge collapse part of the silicon wafer caused in the double-side polishing processing process of the previous working procedure can be removed through the chamfering process, and the problem of edge collapse of the silicon wafer is solved.
Referring to fig. 6, in order to clean impurities and processing traces formed on the edge of the silicon wafer by the second chamfering process and make the chamfered portion mirror-finished, according to a preferred embodiment of the present invention, the silicon wafer processing method further comprises:
s104: and carrying out edge polishing processing on the silicon wafer subjected to the second chamfering processing.
If the silicon wafer subjected to the above processing still does not satisfy the requirements due to flatness and roughness, preferably, referring to fig. 6, the silicon wafer processing method further comprises:
s105: and finally polishing the surface of the silicon wafer after the edge polishing.
According to the preferred embodiment of the invention, the plating process for the silicon wafer after the first chamfering process and the grinding process comprises the following steps: 900 to 1000 angstroms of silicon oxide is formed on the surface and edges of the silicon wafer.
More preferably, the plating process of the silicon wafer after the first chamfering process and the polishing process is to form 1000 angstrom of silicon oxide on the surface of the silicon wafer.
According to the silicon wafer processing method provided by the embodiment of the invention, the edge collapse phenomenon of the silicon wafer in the processing process is mainly removed through the second chamfering processing, so that the removal amount of the second chamfering processing is reasonably set.
Based on this, preferably, the second chamfering process of the silicon wafer after the double-side polishing process includes: and removing the circumferential edge of the silicon wafer by 0.5-1 mm along the radius direction.
More preferably, the second chamfering of the silicon wafer after double-side polishing is performed by removing the circumferential edge of the silicon wafer by 1mm in the radial direction.
According to the preferred embodiment of the present invention, the performing the edge polishing process on the silicon wafer after the second chamfering process includes: and removing 5 um-10 um on the circumferential edge of the silicon wafer along the radius direction.
The embodiment of the invention also provides a silicon wafer, which is obtained by using the silicon wafer processing method.
It should be noted that: the technical schemes described in the embodiments of the present invention can be combined arbitrarily without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A silicon wafer processing method is characterized by comprising the following steps:
carrying out film coating processing on the silicon wafer subjected to the first chamfering processing and grinding processing;
carrying out double-sided polishing processing on the silicon wafer after the film coating processing;
and carrying out secondary chamfering processing on the silicon wafer subjected to double-side polishing processing.
2. The silicon wafer processing method according to claim 1, further comprising: and carrying out edge polishing processing on the silicon wafer subjected to the second chamfering processing.
3. The silicon wafer processing method according to claim 2, further comprising: and finally polishing the surface of the silicon wafer subjected to edge polishing.
4. The silicon wafer processing method according to any one of claims 1 to 3, wherein the plating process of the silicon wafer subjected to the first chamfering process and the grinding process comprises: 900 to 1000 angstroms of silicon oxide is formed on the surface and edges of the silicon wafer.
5. The silicon wafer processing method according to any one of claims 1 to 3, wherein the second chamfering process for the silicon wafer after the double-side polishing process comprises: and removing the circumferential edge of the silicon wafer by 0.5-1 mm along the radius direction.
6. The silicon wafer processing method according to claim 2, wherein the edge polishing process for the silicon wafer after the second chamfering process comprises: and removing 5 um-10 um at the circumferential edge of the silicon wafer along the radius direction.
7. A silicon wafer characterized by being obtained by using the silicon wafer processing method according to any one of claims 1 to 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210733112.2A CN114792622A (en) | 2022-06-27 | 2022-06-27 | Silicon wafer processing method and silicon wafer |
| TW111137848A TWI852112B (en) | 2022-06-27 | 2022-10-05 | Silicon wafer processing method and silicon wafer |
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| CN202210733112.2A CN114792622A (en) | 2022-06-27 | 2022-06-27 | Silicon wafer processing method and silicon wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI844233B (en) * | 2022-11-30 | 2024-06-01 | 大陸商西安奕斯偉材料科技股份有限公司 | Method for monitoring bulk metal in semiconductor process |
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| JP2001345291A (en) * | 2000-05-31 | 2001-12-14 | Mitsubishi Materials Silicon Corp | Method for producing wafer having one mirror finished surface |
| JP2004087522A (en) * | 2002-08-22 | 2004-03-18 | Sumitomo Mitsubishi Silicon Corp | Process for producing semiconductor wafer |
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| US5230747A (en) * | 1982-07-30 | 1993-07-27 | Hitachi, Ltd. | Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer |
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| TWI582892B (en) * | 2015-09-17 | 2017-05-11 | 精曜科技股份有限公司 | Method for wafer alignment |
| CN106738360B (en) * | 2017-01-19 | 2018-04-10 | 中国建筑材料科学研究总院 | Quartz pendulous reed substrate and preparation method thereof |
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- 2022-06-27 CN CN202210733112.2A patent/CN114792622A/en active Pending
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| JP2001345291A (en) * | 2000-05-31 | 2001-12-14 | Mitsubishi Materials Silicon Corp | Method for producing wafer having one mirror finished surface |
| JP2004087522A (en) * | 2002-08-22 | 2004-03-18 | Sumitomo Mitsubishi Silicon Corp | Process for producing semiconductor wafer |
| JP2006100406A (en) * | 2004-09-28 | 2006-04-13 | Toshiba Ceramics Co Ltd | Manufacturing method of SOI wafer |
| CN102528597A (en) * | 2010-12-08 | 2012-07-04 | 有研半导体材料股份有限公司 | Manufacturing process of large-diameter silicon wafer |
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| TW202302270A (en) | 2023-01-16 |
| TWI852112B (en) | 2024-08-11 |
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Address after: Room 1-3-029, No. 1888, Xifeng South Road, high tech Zone, Xi'an, Shaanxi 710065 Applicant after: Xi'an Yisiwei Material Technology Co.,Ltd. Applicant after: XI'AN ESWIN SILICON WAFER TECHNOLOGY Co.,Ltd. Address before: Room 1-3-029, No. 1888, Xifeng South Road, high tech Zone, Xi'an, Shaanxi 710065 Applicant before: Xi'an yisiwei Material Technology Co.,Ltd. Applicant before: XI'AN ESWIN SILICON WAFER TECHNOLOGY Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220726 |