Electronic detonator delay system and method
Technical Field
The application relates to the technical field of electronic detonators, in particular to an electronic detonator delay system and method.
Background
In order to ensure the reliability of connection of the networked electronic detonators, in general, the detonators perform roll-call operation on the electronic detonators at the detonation sites. Before leaving the factory, the electronic detonator module can be subjected to independent function test through a module tester. However, in actual use, networking actual explosion of hundreds of detonator modules is performed on site, and problems of some modules are only exposed in networking stage. Therefore, how to simulate the field real explosion environment in a laboratory and perform large-scale networking test on the module is an engineering problem with practical significance.
The electronic detonator chip is applied to the blasting industry, the chip is powered through a power supply bus when in normal communication, and when the chip enters a final delay blasting process, the power supply wire for power supply can be blasted by the detonator blasted first, so that the electronic detonator module cannot be powered. Therefore, the electronic detonator modules all have special energy storage capacitors. The independent energy storage capacitor not only can meet the requirement that the electronic detonator chip normally works in the initiation delay stage, but also can release enough energy to ensure reliable ignition of the powder head when the delay is finished, so that the electronic detonator chip is required to support the functions of low power consumption and long delay. The higher the power consumption of the chip is, the larger the capacitance is needed, the higher the capacitance cost is, and the large-scale popularization of the electronic detonator module is limited; there are also individual manufacturers that use small capacity capacitors to save cost, but use sensitive ignition tips to reduce the firing energy requirements of the tips, which can create significant safety hazards to the finished detonator during production and transportation.
The electronic detonator delay refers to a countdown function of the electronic detonator chip before initiation, and is generally realized through a timer. The power consumption of this electronic detonator delay can directly impact the cost and safety of the final electronic detonator finished product.
Disclosed in patent document with publication number CN105509581a is an electronic detonator, a programmer and a delay time setting method of the electronic detonator, wherein the delay time setting method comprises: connecting a programmer to the bus; sequentially connecting each electronic detonator to the bus; determining whether a new electronic detonator is connected to the bus by detecting a current pulse on the bus, and informing a microprocessor if the new electronic detonator is determined to be connected to the bus; the microprocessor broadcasts and sends out a delay time through the bus when a new electronic detonator is connected to the bus; and when the electronic detonator control circuit in the delay identification unit receives the delay time from the bus, writing the delay time into the delay storage unit in the electronic detonator control circuit, setting the delay identification in the delay identification unit to be full, and then responding delay setting confirmation information to the processor through the bus.
Therefore, a new technical solution needs to be proposed.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide an electronic detonator delay system and method.
The application provides an electronic detonator delay system, which comprises: the system comprises a high-voltage power supply switching circuit, a low-dropout linear voltage stabilizer, an oscillator, a power supply management module, a delay timer, a first power supply gating unit, a second power supply gating unit, a third power supply gating unit, other analog circuits and other digital logic circuits;
the high-voltage power supply switching circuit is respectively connected with a low-dropout linear voltage regulator and a first power supply gating unit, the low-dropout linear voltage regulator is respectively connected with an oscillator and a second power supply gating unit, the first power supply gating unit is connected with other analog circuits, the oscillator is connected with a power supply management module, the second power supply gating power supply is connected with other analog circuits, the power supply management module is respectively connected with a delay timer and a third power supply gating unit, the delay timer is connected with a firing switch Q, and the third power supply gating unit is connected with other digital logic circuits; the emitter of the firing switch Q is grounded, and the collector is connected with a firing element R; the ignition element R is connected with an energy storage capacitor C and a high-voltage power supply switching circuit, and the energy storage capacitor C is grounded.
Preferably, the high-voltage power supply switching circuit switches between a normal bus power supply and an energy storage capacitor power supply after a delay, and outputs a high-voltage power supply;
the low dropout linear regulator converts a high-voltage power supply into a low-voltage power supply;
the high-voltage power supply is above 5V; the low voltage power output is 1.8V-4V.
Preferably, the oscillator provides a stable clock1 for the digital logic circuit, the clock frequency being above 100K.
Preferably, the power management module dynamically switches a power supply and a clock in a normal working mode and a delay mode, and after the delay is entered, the power off control signal Poweroff outputs a high level to control the first power gating unit, the second power gating unit and the third power gating unit to be turned off; the dynamic switching clock output clock2 switches from a high frequency clock to a low frequency clock; the low frequency clock frequency is below 10K.
Preferably, the delay timer counts down after entering a delay state, outputs an ignition control signal when the count reaches zero, and detonates the ignition powder head;
the first power gating unit and the second power gating unit control the high voltage and the low voltage of other analog circuits to be closed in a delay state; the third power gating unit turns off the low-voltage power supply of other digital logic circuits.
Preferably, the other analog circuits are collectively called other analog circuits inside the detonator chip except the analog circuit module explicitly described above;
the other digital logic circuits are collectively called as other digital logic circuits inside the detonator chip except the digital circuit module which is explicitly described above.
The application also provides an electronic detonator delay method, which is applied to the electronic detonator delay system and comprises the following steps:
step S1: after the electronic detonator chip is normally electrified, a power off control signal Poweroff output by the power management module outputs a low level, the first power gating unit, the second power gating unit and the third power gating unit are conducted, and power supplies of the chip analog circuit and the digital circuit are turned on; the Clock2 output to the delay timer by the power management module works on a high-frequency Clock;
step S2: the detonating device sends a detonating command after normal communication, chip configuration, high-voltage power charging and delay time setting are completed;
step S3: after the electronic detonator chip receives the detonation command, a control state machine in the power management module switches the working mode of the system, and enters a delay mode from a normal mode;
step S4: after entering the delay mode, the power management module switches the power off control signal Poweroff to a high level;
step S5: the power supply management module switches the output clock2 from a high-frequency clock to a low-frequency clock through the clock switching circuit;
step S6: after the clock switching is completed, starting a delay timer and starting to count down;
step S7: after the timer counts down to zero, an ignition control signal is output to detonate the medicine head.
Preferably, the power supply of the chip in the step S1 is from a bus power supply, and the bus power supply is 6V-40V.
Preferably, the initiator in step S2 controls the electronic detonator module.
Preferably, the high level in step S4 turns off the power supply of other analog circuits and other digital logic circuits.
Compared with the prior art, the application has the following beneficial effects:
1. according to the application, through an ultra-low power consumption design method, delay power consumption of the electronic detonator can be reduced to below 10uA, small-size low-cost capacitance can be supported, meanwhile, the inert ignition powder head can be reliably ignited, and the cost of a finished detonator product is lower and the safety is higher;
2. the application adopts a single oscillator mode, avoids the complex clock calibration process of two oscillators, realizes the complete synchronization of high-frequency clocks and low-frequency clocks before and after switching through special circuit design, and can ensure the normal operation of the circuit when switching to low frequency;
3. according to the application, only one oscillation source is needed in the clock switching, the other low-frequency clock is obtained through simple clock frequency division, and then the switching is performed between the two clocks, so that the design is simpler and the cost is lower;
4. the application further provides a method for obtaining the lowest power consumption by closing the power supply besides clock switching.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a circuit configuration of the present application;
fig. 2 is a flow diagram of the present application.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
According to the method, an electronic detonator chip is realized in an ASIC (Application Specific Integrated Circuit application specific integrated circuit) mode, after delay is entered, a special power management module is used for realizing the switching of the chip working mode through a state machine, and meanwhile, the ultralow power consumption delay is realized through a power off control signal Poweroff and a clock dynamic switching method. Specifically, the power supply of the analog circuit inside the chip is completely shut down except for the low-voltage power supply and the oscillator; the digital circuit part is powered off except the power management module and the delay timer, and the clocks of the power management module and the delay timer are switched to the low-frequency clock, so that the delay power consumption of the electronic detonator chip is minimized.
The application provides an electronic detonator delay system which comprises a high-voltage power supply switching circuit, a low-dropout linear voltage stabilizer, an oscillator, a power supply management module, a delay timer, a first power supply gating unit, a second power supply gating unit, a third power supply gating unit, other analog circuits and other digital logic circuits, wherein the first power supply gating unit is connected with the first power supply gating unit; the high-voltage power supply switching circuit is respectively connected with a low-dropout linear voltage stabilizer and a first power supply gating unit, the low-dropout linear voltage stabilizer is respectively connected with an oscillator and a second power supply gating unit, the first power supply gating unit is connected with other analog circuits, the oscillator is connected with a power supply management module, the second power supply gating power supply is connected with other analog circuits, the power supply management module is respectively connected with a delay timer and a third power supply gating unit, the delay timer is connected with a firing switch Q, the third power supply gating unit is connected with other digital logic circuits, the emitter of the firing switch Q is grounded, the collector of the firing switch Q is connected with a firing element R, the firing element R is connected with an energy storage capacitor C and the high-voltage power supply switching circuit, and the energy storage capacitor C is grounded.
High voltage power supply switching circuit: the switching between the normal bus power supply and the energy storage capacitor power supply after the delay is realized, and the output is a high-voltage power supply, which is generally more than 5V.
Low dropout linear regulator (LDO): the conversion from a high-voltage power supply to a low-voltage power supply is realized, and the output of the low-voltage power supply is generally 1.8V-4V.
An oscillator: a stable clock1 is provided for the digital logic circuit, with clock frequencies typically above 100K.
And a power management module: the digital logic is realized, the dynamic switching of the power supply and the clock is realized in a normal working mode and a delay mode, after the delay is carried out, the power supply closing control signal Poweroff outputs a high level, and the turning-off of the first power supply gating unit, the second power supply gating unit and the third power supply gating unit in the diagram is controlled; while the dynamic switching clock output clock2 switches from a high frequency clock to a low frequency clock. The low frequency clock frequency is typically below 10K.
Delay timer: and (3) realizing digital logic, counting down after entering a delay state, and outputting an ignition control signal when the count reaches zero so as to realize the detonation of the gunpowder head.
The first power gating unit, the second power gating unit and the third power gating unit: the first power gating unit and the second power gating unit are used for controlling the high voltage and the low voltage of the other analog circuits to be turned off in a delay state; the third power gating unit is used for turning off the low-voltage power supply of the other digital logic circuits.
Other analog circuits: the other analog circuits inside the detonator chip, in addition to the analog circuit modules explicitly described above, are collectively referred to.
Other digital logic circuits: other digital logic circuits inside the detonator chip besides the digital circuit modules explicitly described above are collectively referred to.
The application also provides an electronic detonator delay method, which is applied to the electronic detonator delay system and comprises the following steps:
step S1: after the electronic detonator chip is normally electrified, the power supply of the chip is powered by a bus, the power supply on the bus is generally 6V-40V, at the moment, a power supply closing control signal PowerOff output by a power management module outputs a low level, a first power gating unit, a second power gating unit and a third power gating unit are realized by PMOS (P-channel metal oxide semiconductor) tubes, a grid electrode is connected with the PowerOff signal, the PowerOff is pulled down, the PMOS tubes are conducted, and all high-voltage and low-voltage power supply on all parts of the chip are opened; the dynamic switching Clock2 operates at a high frequency Clock. The exploder outputs 6-40V voltage to supply power to the electronic detonator chip through the bus, a high-voltage power supply is output by a high-voltage power supply switching circuit in the electronic detonator chip, and meanwhile, a low dropout linear regulator (LDO) is started to output a stable low-voltage power supply, so that the chip is powered on.
Step S2: the electronic detonator module is used for controlling the exploder of the electronic detonator module to send an explosion command after completing normal communication, chip configuration, high-voltage electric charge, delay time setting and other necessary operations.
Step S3: after the electronic detonator chip receives the detonation command, a control state machine in the power management module realizes the switching of the working mode of the system, and the electronic detonator chip enters a delay mode from a normal mode.
Step S4: after entering the deferred mode, the power management module first switches the power off control signal PowerOff to a high level for powering off other analog circuits and other digital logic circuits.
Step S5: the power management module then switches the output clock2 from the high frequency clock to the low frequency clock through the clock switching circuit.
Step S6: after the clock switching is completed, a delay timer is started, and the countdown is started.
Step S7: after the timer counts down to zero, an ignition control signal is output to detonate the medicine head.
Those skilled in the art will appreciate that the application provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the application can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.