CN114784112A - Thin film transistor and preparation method thereof - Google Patents

Abstract

Embodiments of the present application disclose a thin film transistor and a method for fabricating a thin film transistor. The thin film transistor includes a substrate, a gate electrode, a gate insulating layer, an active layer, and a source and drain layer, and the active layer is disposed on the gate insulating layer. , the preparation material of the active layer includes aluminum, the source electrode and the drain electrode are arranged above the active layer, wherein the active layer includes a first part close to the gate insulating layer, a second part close to the source and drain layers, and the first part of the aluminum The content is higher than the aluminum content of the second part; by making the aluminum content of the first part of the active layer close to the gate insulating layer higher than the aluminum content of the second part close to the source and drain layers, the mobility of the thin film transistor is improved.

Description

Thin film transistor and method of making the same

technical field

The present application relates to the field of display technology, in particular to a thin film transistor and a method for preparing a thin film transistor.

Background technique

The mobility of oxide thin film transistors is as high as 10 to 100 times that of amorphous silicon thin film transistors, which can meet the needs of new high-end display products. Therefore, metal oxide thin film transistors and their display panels are increasingly valued by the industry. However, compared with low temperature polysilicon, oxide thin film transistors have poor stability and low mobility.

Therefore, the existing oxide thin film transistor has a technical problem of low mobility.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a thin film transistor and a method for fabricating a thin film transistor, which can alleviate the technical problem of low mobility of the existing oxide thin film transistor.

Embodiments of the present application provide a thin film transistor, including:

substrate;

a gate, the gate is disposed above the substrate;

a gate insulating layer, the gate insulating layer is disposed above the gate electrode and the substrate;

an active layer, the active layer is disposed on the gate insulating layer, and the preparation materials of the active layer include aluminum, gallium, and zinc;

a source-drain layer, the source-drain layer is disposed above the active layer, the source-drain layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer ;

Wherein, the active layer includes a first part close to the gate insulating layer and a second part close to the source and drain layers, and the aluminum content of the first part is higher than that of the second part.

Optionally, in some embodiments of the present application, the gallium/zinc content of the second part is higher than the gallium/zinc content of the first part.

Optionally, in some embodiments of the present application, the active layer includes a first part, a second part, and a third part located between the first part and the second part, the first part/the The ratio of the thickness of the second portion to the thickness of the active layer ranges from 8% to 12%.

Optionally, in some embodiments of the present application, the thickness of the first portion is equal to the thickness of the second portion.

Optionally, in some embodiments of the present application, the active layer includes a first active sublayer and a second active sublayer, the first active sublayer is disposed close to the gate insulating layer, so The second active sublayer is disposed close to the source and drain layers, and the aluminum content of the first active sublayer is higher than that of the second active sublayer.

Optionally, in some embodiments of the present application, the gallium/zinc content of the second active sublayer is higher than the gallium/zinc content of the first active sublayer.

Optionally, in some embodiments of the present application, a material for preparing the gate insulating layer includes aluminum oxide.

Optionally, in some embodiments of the present application, the aluminum content of the first active sublayer ranges from 30% to 50%, and the gallium content of the first active sublayer ranges from 20% to 50%. 30%, the zinc content of the first active sublayer ranges from 30% to 40%.

Optionally, in some embodiments of the present application, the aluminum content of the second active sublayer ranges from 10% to 30%, and the gallium content of the second active sublayer ranges from 30% to 30%. 40%, the zinc content of the second active sublayer ranges from 40% to 50%.

An embodiment of the present application provides a method for fabricating a thin film transistor, including:

providing a substrate;

A gate electrode and a gate insulating layer are prepared on the substrate;

A first active sublayer is prepared by sputtering a first target on the gate insulating layer;

A second active sublayer is prepared by sputtering a second target on the first active sublayer, wherein the gallium/zinc content of the second target is higher than the gallium/zinc content of the first target Zinc content, the aluminum content of the first target is higher than the aluminum content of the second target;

A source and drain layer is prepared over the second active sublayer.

Beneficial effects: the thin film transistor provided by the embodiment of the present application includes a gate insulating layer, an active layer, and a source and drain layer arranged in sequence, and the preparation material of the active layer includes aluminum; by making the active layer close to the gate insulating layer The aluminum content of the first part is higher than the aluminum content of the second part close to the source and drain layers, thereby improving the mobility of the thin film transistor.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a first schematic cross-sectional view of a thin film transistor provided by an embodiment of the present application;

2 is a second schematic cross-sectional view of a thin film transistor provided by an embodiment of the present application;

FIG. 3 is a flowchart of a method for fabricating a thin film transistor provided by an embodiment of the present application.

Description of reference numbers:

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present application, but not to limit the present application. In this application, unless otherwise stated, the directional words used such as "upper" and "lower" generally refer to the upper and lower sides of the device in actual use or working state, specifically the drawing direction in the accompanying drawings ; while "inside" and "outside" refer to the outline of the device.

Referring to FIG. 1 , the thin film transistor 1 provided by the present application includes a substrate 10 , a gate electrode 20 , a gate insulating layer 30 , an active layer 40 , and a source and drain layer 50 , and the gate electrode 20 is disposed above the substrate 10 . , the gate insulating layer 30 is arranged on the gate 20 and the substrate 10, the active layer 40 is arranged on the gate insulating layer 30, and the preparation material of the active layer 40 includes aluminum, Gallium and zinc, the source-drain layer 50 is disposed above the active layer 40, the source-drain layer 50 includes a source electrode 501 and a drain electrode 502, and the source electrode 501 and the drain electrode 502 are respectively connected with The active layer 40 is connected, wherein the active layer 40 includes a first part 401 close to the gate insulating layer 30 , a second part 402 close to the source and drain layers 50 , and the first part 401 is made of aluminum. The content of aluminum is higher than that of the second portion 402; by making the active layer 40 close to the gate insulating layer 30, the aluminum content of the first portion 401 is higher than that of the second portion 402 close to the source and drain layers 50. aluminum content, thereby improving the mobility of the thin film transistor 1 .

In the present application, the aluminum content of the first part 401 of the active layer 40 close to the gate insulating layer 30 is higher than the aluminum content of the second part 402 of the source and drain layers 50 , thereby improving the performance of the thin film transistor 1 The mobility solves the technical problem of low mobility in the existing oxide thin film transistor 1 .

The technical solutions of the present application will now be described with reference to specific embodiments.

In one embodiment, referring to FIG. 1 , the gallium/zinc content of the second portion 402 is higher than the gallium/zinc content of the first portion 401 .

Wherein, the range of the gallium content of the first part 401 is: 0.2≤Ga/(Al+Ga+Zn)≤0.3.

Wherein, the zinc content range of the first part 401 is: 0.3≤Zn/(Al+Ga+Zn)≤0.4.

Wherein, the range of the gallium content of the second part 402 is: 0.3≤Ga/(Al+Ga+Zn)≤0.4.

Wherein, the zinc content range of the second part 402 is: 0.4≤Zn/(Al+Ga+Zn)≤0.5.

It can be understood that the film layer with high gallium/zinc content in the second part 402 has low carrier concentration and few defect states, which can improve the stability of the thin film transistor 1 .

In this embodiment, by making the gallium/zinc content of the second part 402 close to the source-drain layer 50 higher than the gallium/zinc content of the first part 401 close to the gate insulating layer 30 , the defect state of the second part 402 is reduced , to improve the stability of the thin film transistor 1 .

In one embodiment, the active layer 40 includes a first part 401 , a second part 402 and a third part 403 located between the first part 401 and the second part 402 , the first part 401 / The ratio of the thickness of the second portion 402 to the thickness of the active layer 40 ranges from 8% to 12%.

Wherein, the thickness of the first portion 401/the second portion 402 may range from 4 nm to 6 nm.

The first portion 401 is disposed in contact with the gate insulating layer 30 .

The second portion 402 is disposed in contact with the source electrode 501 and the drain electrode 502 .

Further, the ratio of the thickness of the first part 401/the second part 402 to the thickness of the active layer 40 is 10%.

It can be understood that the first portion 401 is close to the gate insulating layer 30 , which has a great influence on the mobility of the thin film transistor 1 .

It can be understood that the second portion 402 is close to the source and drain layers 50 , which has a great influence on the stability of the thin film transistor 1 .

In this embodiment, by defining the thickness of the first portion 401 that has a greater impact on the mobility and the thickness of the second portion 402 that has a greater impact on the stability, the impact of the first portion 401 on the mobility of the thin film transistor 1 is improved, and at the same time The influence of the second part 402 on the stability of the thin film transistor 1 is improved.

In an embodiment, the source electrode 501 and the drain electrode 502 are directly disposed on the active layer 40 and the gate insulating layer 30 .

In an embodiment, a passivation layer is further provided above the active layer 40 and the gate insulating layer 30 , the passivation layer is provided with a first via hole and a second via hole, and the source electrode 501 The drain 502 is connected to the active layer 40 through the first via hole, and the drain electrode 502 is connected to the active layer 40 through the second via hole.

The source electrode 501 and the drain electrode 502 are connected to the second portion 402 of the active layer 40 .

In one embodiment, the thickness of the first portion 401 is equal to the thickness of the second portion 402 .

The thickness of the first portion 401 and the thickness of the second portion 402 are both 5 nm.

In this embodiment, by making the thicknesses of the first portion 401 and the second portion 402 equal, the effects of simplifying the manufacturing process and reducing the cost can be achieved.

In one embodiment, referring to FIG. 2 , the active layer 40 includes a first active sublayer 404 and a second active sublayer 405 , and the first active sublayer 404 is close to the gate insulating layer 30 setting, the second active sub-layer 405 is disposed close to the source and drain layers 50 , and the aluminum content of the first active sub-layer 404 is higher than that of the second active sub-layer 405 .

Wherein, the aluminum content range of the first active sub-layer 404 is: 0.3≤Al/(Al+Ga+Zn)≤0.5.

Wherein, the aluminum content range of the second active sub-layer 405 is: 0.1≤Al/(Al+Ga+Zn)≤0.3.

It can be understood that the atomic radius of aluminum is close to that of zinc. By increasing the content of aluminum in the first active sub-layer 404, aluminum is a group III element and has one more valence electron than zinc, and the valence electron is less bound and less bound. It is easily excited to generate free electrons, thereby improving the electron mobility of semiconductor materials.

In this embodiment, by increasing the aluminum content of the first active sub-layer 404 , the first active sub-layer 404 has a greater influence on the mobility than the second active sub-layer 405 , thereby improving the mobility of the thin film transistor 1 .

In one embodiment, the gallium/zinc content of the second active sub-layer 405 is higher than the gallium/zinc content of the first active sub-layer 404 .

Wherein, the gallium content range of the first active sub-layer 404 is: 0.2≤Ga/(Al+Ga+Zn)≤0.3.

Wherein, the zinc content range of the first active sub-layer 404 is: 0.3≤Zn/(Al+Ga+Zn)≤0.4.

Wherein, the range of the gallium content of the second active sub-layer 405 is: 0.3≤Ga/(Al+Ga+Zn)≤0.4.

Wherein, the zinc content range of the second active sub-layer 405 is: 0.4≤Zn/(Al+Ga+Zn)≤0.5.

It can be understood that, the film layer with high gallium/zinc content of the second active sublayer 405 has low carrier concentration and few defect states, which can improve the stability of the thin film transistor 1 .

In this embodiment, by making the gallium/zinc content of the second part 402 close to the source-drain layer 50 higher than the gallium/zinc content of the first part 401 close to the gate insulating layer 30 , the defect state of the second part 402 is reduced , to improve the stability of the thin film transistor 1 .

In one embodiment, the material for preparing the insulating layer of the gate electrode 20 includes aluminum oxide.

The active layer 40 of aluminum gallium zinc oxide is prepared by PVD magnetron sputtering, and the insulating layer of aluminum oxide gate 20 is prepared by atomic layer deposition.

It can be understood that the crystal lattice of the aluminum oxide will induce the crystallization behavior of the aluminum gallium zinc oxide, so that the obtained aluminum gallium zinc oxide exhibits a slight crystallization phenomenon, thereby reducing the defect state of the active layer 40 .

It can be understood that a part of the gate insulating layer 30 that is in direct contact with the active layer 40 is aluminum oxide. Since both the gate insulating layer 30 and the active layer 40 include aluminum oxide materials, the transition interface between the two is in a defect state. reduce.

In this embodiment, the gate insulating layer 30 is made of aluminum oxide to further reduce defect states at the transition interface between the gate insulating layer 30 and the active layer 40 , thereby further improving the stability of the thin film transistor 1 .

In one embodiment, the aluminum content of the first active sublayer 404 ranges from 30% to 50%, and the gallium content of the first active sublayer 404 ranges from 20% to 30%, so The zinc content of the first active sublayer 404 ranges from 30% to 40%.

In one embodiment, the aluminum content of the second active sublayer 405 ranges from 10% to 30%, and the gallium content of the second active sublayer 405 ranges from 30% to 40%, so The zinc content of the second active sublayer 405 ranges from 40% to 50%.

In one embodiment, the thickness of the first active sub-layer 404 is 25 nanometers, and the thickness of the second active sub-layer 405 is 25 nanometers.

Wherein, the annealing temperature is 350° C., the annealing time is 60 minutes, and the atmosphere is clean air.

Wherein, the thin film transistor 1 is of a back channel etch type.

Wherein, the preparation material of the gate insulating layer 30 is aluminum oxide.

Wherein, the preparation materials of the source electrode 501 and the drain electrode 502 are molybdenum and copper.

Wherein, the preparation material of the passivation layer is silicon oxide.

Specifically, when Al/(Al+Ga+Zn)=0.3, Ga/(Al+Ga+Zn)=0.3, and Zn/(Al+Ga+Zn)=0.4 of the first active sublayer 404, the When Al/(Al+Ga+Zn)=0.4, Ga/(Al+Ga+Zn)=0.3, and Zn/(Al+Ga+Zn)=0.3 of the second active sublayer 405, the threshold voltage is 1.4V, the mobility is 10.8cm ² /V, and the threshold voltage shift is -1.8V.

Specifically, when Al/(Al+Ga+Zn)=0.4, Ga/(Al+Ga+Zn)=0.3, and Zn/(Al+Ga+Zn)=0.3 of the active sublayer, the When Al/(Al+Ga+Zn)=0.3, Ga/(Al+Ga+Zn)=0.3, and Zn/(Al+Ga+Zn)=0.4 of the second active sublayer 405, the threshold voltage is 1.3V, the mobility is 14.8cm ² /V, and the threshold voltage shift is -1.9V.

Specifically, when Al/(Al+Ga+Zn)=0.5, Ga/(Al+Ga+Zn)=0.2, and Zn/(Al+Ga+Zn)=0.3 of the active sublayer, the When Al/(Al+Ga+Zn)=0.1, Ga/(Al+Ga+Zn)=0.4, and Zn/(Al+Ga+Zn)=0.5 of the second active sublayer 405, the threshold voltage is 0.6V, the mobility is 22cm ² /V, and the threshold voltage shift is -1.2V.

Specifically, when Al/(Al+Ga+Zn)=0.1, Ga/(Al+Ga+Zn)=0.4, and Zn/(Al+Ga+Zn)=0.5 of the active sublayer, the When Al/(Al+Ga+Zn)=0.5, Ga/(Al+Ga+Zn)=0.2, and Zn/(Al+Ga+Zn)=0.3 of the second active sublayer 405, the threshold voltage is 2.3V, the mobility is 3.5cm ² /V, and the threshold voltage shift is -1.3V.

It can be understood that the range of the threshold voltage is 0V to 3V; the higher the mobility, the better, and the smaller the absolute value of the threshold voltage drift, the better; it can be seen that the higher the aluminum content of the first active sublayer 404 is , the higher the mobility, the higher the gallium/zinc content of the second active sub-layer 405, the better the stability.

It should be noted that there is an error of ±0.3V in the above-mentioned threshold voltage value and the threshold voltage drift value.

In this embodiment, through the definition of the first active sublayer 404 and the second active sublayer 405 , when the active sublayers have Al/(Al+Ga+Zn)=0.5, Ga/(Al +Ga+Zn)=0.2, Zn/(Al+Ga+Zn)=0.3, Al/(Al+Ga+Zn)=0.1, Ga/(Al+Ga+ When Zn)=0.4 and Zn/(Al+Ga+Zn)=0.5, the mobility of the active layer 40 is 22 cm ² /V, and the threshold voltage shift is -1.2 V. At this time, the active layer 40 is Layer 40 has high mobility and good stability.

Referring to FIG. 3, an embodiment of the present application provides a method for fabricating a thin film transistor 1, including:

S1: providing a substrate 10;

S2: preparing the gate electrode 20 and the gate insulating layer 30 on the substrate 10;

S3: preparing the first active sub-layer 404 on the gate insulating layer 30 by sputtering the first target material;

S4: preparing a second active sub-layer 405 by sputtering a second target material on the first active sub-layer 404, wherein the content of gallium/zinc of the second target material is higher than that of the first target The gallium/zinc content of the material, the aluminum content of the first target is higher than the aluminum content of the second target;

S5: A source-drain layer 50 is prepared on the second active sub-layer 405 .

Wherein, the preparation materials and components of the first active sub-layer 404 are the same as the preparation materials and components of the first target material.

Wherein, the preparation materials and components of the second active sub-layer 405 are the same as the preparation materials and components of the second target material.

The present application also proposes a display panel, a display module, and a display device, wherein the display panel includes an array layer, a light-emitting functional layer, and an encapsulation layer, and the array layer includes the above-mentioned thin film transistors. Both the display module and the display device include the above-mentioned thin film transistors, which will not be repeated here.

The thin film transistor provided in this embodiment includes a substrate, a gate, a gate insulating layer, an active layer, and a source and drain layer, the active layer is disposed on the gate insulating layer, and the preparation material of the active layer includes aluminum, gallium, and zinc, the source electrode and the drain electrode are disposed above the active layer, wherein the active layer includes a first portion close to the gate insulating layer, a first portion close to the source and drain electrode layers In the second part, the aluminum content of the first part is higher than that of the second part; by making the active layer close to the gate insulating layer, the aluminum content of the first part is higher than that of the source and drain layers. The aluminum content of the second part increases the mobility of the thin film transistor.

In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

A thin film transistor and a method for fabricating a thin film transistor provided by the embodiments of the present application have been described in detail above. The principles and implementations of the present application are described with specific examples. The descriptions of the above embodiments are only used for Help to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation and application scope. In summary, the content of this specification does not It should be understood as a limitation of this application.

Claims (10)

1. a thin film transistor, is characterized in that, comprises: substrate; a gate, the gate is disposed above the substrate; a gate insulating layer, the gate insulating layer is disposed above the gate electrode and the substrate; an active layer, the active layer is disposed on the gate insulating layer, and the preparation materials of the active layer include aluminum, gallium, and zinc; a source-drain layer, the source-drain layer is disposed above the active layer, the source-drain layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to the active layer ; Wherein, the active layer includes a first part close to the gate insulating layer and a second part close to the source and drain layers, and the aluminum content of the first part is higher than that of the second part. 2 . The thin film transistor of claim 1 , wherein the gallium/zinc content of the second portion is higher than the gallium/zinc content of the first portion. 3 . 3. The thin film transistor of claim 2, wherein the active layer comprises a first part, a second part, and a third part located between the first part and the second part, the first part The ratio of the thickness of the part/the second part to the thickness of the active layer ranges from 8% to 12%. 4. The thin film transistor of claim 3, wherein the thickness of the first portion is equal to the thickness of the second portion. 5 . The thin film transistor of claim 1 , wherein the active layer comprises a first active sublayer and a second active sublayer, and the first active sublayer is close to the gate insulating layer. 6 . The second active sub-layer is disposed close to the source and drain layers, and the aluminum content of the first active sub-layer is higher than that of the second active sub-layer. 6 . The thin film transistor of claim 5 , wherein the gallium/zinc content of the second active sublayer is higher than the gallium/zinc content of the first active sublayer. 7 . 7 . The thin film transistor of claim 5 , wherein a material for preparing the gate insulating layer comprises aluminum oxide. 8 . 8 . The thin film transistor of claim 7 , wherein the aluminum content of the first active sublayer ranges from 30% to 50%, and the gallium content of the first active sublayer ranges from 20% to 30%, the zinc content of the first active sublayer ranges from 30% to 40%. 9 . The thin film transistor of claim 8 , wherein the aluminum content of the second active sublayer ranges from 10% to 30%, and the gallium content of the second active sublayer ranges from 30% to 40%, the zinc content of the second active sublayer ranges from 40% to 50%. 10. A method for preparing a thin film transistor, comprising: providing a substrate; A gate electrode and a gate insulating layer are prepared on the substrate; A first active sublayer is prepared by sputtering a first target on the gate insulating layer; A second active sublayer is prepared by sputtering a second target on the first active sublayer, wherein the gallium/zinc content of the second target is higher than the gallium/zinc content of the first target Zinc content, the aluminum content of the first target is higher than the aluminum content of the second target; A source and drain layer is prepared over the second active sublayer.

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