CN114783492A - Nonvolatile memory device, program method thereof, and nonvolatile memory system - Google Patents

Abstract

Provided are a nonvolatile memory device, a program method thereof, and a nonvolatile memory system. The programming method of the nonvolatile memory device includes: performing a write operation and a verify operation on at least one first memory cell of a plurality of memory cells connected to a first word line during a first program time; and performing a write operation on memory cells other than the first memory cell among the plurality of memory cells connected to the first word line. The non-volatile memory device, the programming method thereof and the non-volatile memory system are beneficial to shortening programming time (such as continuous programming) and improving transmission speed of the non-volatile memory device on the premise of improving integrity of programmed data.

Description

Nonvolatile memory device, program method thereof, and nonvolatile memory system

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a nonvolatile memory device, a programming method thereof, and a nonvolatile memory system.

Background

Non-volatile memory systems are capable of retaining data stored therein after a power failure and are widely used in computers, cellular phones, smart phones, personal digital assistants and other electronic device systems. A nonvolatile memory system generally includes a nonvolatile memory device as a storage medium and a control device for controlling the nonvolatile memory device.

As the demand for write and read performance (e.g., bandwidth) of non-volatile memory systems continues to increase, higher requirements are placed on, for example, programming speed and program data integrity of the non-volatile memory devices and their control devices.

Disclosure of Invention

An aspect of the present application provides a method of programming a nonvolatile memory device. The programming method of the nonvolatile memory device includes: performing a write operation and a verify operation on at least one first memory cell among a plurality of memory cells connected to a first word line during a first program time; and performing a write operation on memory cells other than the first memory cell among the plurality of memory cells connected to the first word line.

In some embodiments, the programming method may further include: and performing a write operation on a plurality of memory cells connected to a second word line in a second programming time, wherein the second word line is different from the first word line.

In some embodiments, the programming method may further include: and determining a second word line according to the defect probability of each word line being smaller than a preset threshold value.

In some embodiments, a plurality of memory cells connected to a first wordline are located in a memory string having a sequence number, and the first memory cell may include a memory cell on the memory string having the last sequence number.

In some embodiments, the programming method may further include: a write operation and a verify operation are performed on at least one first memory cell among a plurality of memory cells connected to a first word line according to the received enable verify command.

In some embodiments, the memory cell may comprise a SLC.

Another aspect of the present application provides a non-volatile memory device. The nonvolatile memory device includes: a first word line connected to the plurality of memory cells; and peripheral circuitry configured to: performing a write operation and a verify operation on at least one first memory cell of a plurality of memory cells connected to a first word line during a first program time; and performing a write operation on memory cells other than the first memory cell among the plurality of memory cells connected to the first word line.

In some embodiments, the non-volatile storage device further includes a second word line different from the first word line, the peripheral circuitry may be further configured to: in a second programming time, a write operation is performed on a plurality of memory cells connected to a second word line.

In some embodiments, the peripheral circuitry may be further configured to: and determining a second word line according to the defect probability of each word line being less than a preset threshold value.

In some embodiments, the plurality of memory cells connected to the first word line are located in a memory string having a sequence number, and the first memory cell may include a memory cell on a memory string having a last sequence number.

In some embodiments, the memory cell may comprise a SLC.

The application further provides a nonvolatile storage system. The nonvolatile memory system includes: a non-volatile storage device as described in any of the embodiments above; and a control device configured to and controlling the non-volatile storage device to perform the programming method as described in any of the embodiments above.

In some embodiments, the control device may be further configured to send an enable-verify command.

In some implementations, the non-volatile storage system may include a solid state disk.

According to the nonvolatile memory device, the programming method thereof and the nonvolatile memory system provided by some embodiments of the present application, the write operation and the verification operation are performed on a portion of the memory cells connected to the same word line, so that the determination process of the programming state of the portion of the memory cells is performed within the programming time, which is beneficial to shortening the programming time (for example, continuous programming) and improving the transmission speed of the nonvolatile memory device on the premise of improving the integrity of the programmed data.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a functional block diagram of a non-volatile storage device according to an embodiment of the present application;

FIG. 2A is a timing diagram of a program operation of a non-volatile memory device according to an embodiment of the present application;

FIG. 2B is a timing diagram of a read operation of a non-volatile memory device according to an embodiment of the present application;

FIG. 3 is an equivalent circuit diagram of a memory block according to an embodiment of the present application;

FIG. 4 is a flowchart of a programming method of a non-volatile memory device according to an embodiment of the present application; and

FIG. 5 is a functional block diagram of a non-volatile storage system according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a functional block diagram of a nonvolatile memory device 100 according to an embodiment of the present application. As shown in fig. 1, a non-volatile memory device 100 may include a memory cell array 110 and peripheral circuitry 120. The peripheral circuits 120 may include, but are not limited to, an address decoder 121, a page buffer 122, control logic circuitry 123, and I/O circuitry 124.

In an exemplary embodiment, the memory cell array 110 may be connected to the address decoder 121 through, for example, Word Lines (WLs) and Bit Lines (BLs). Illustratively, memory cell array 110 may include several DIEs (DIE, or LUNs), each of which may include several planes (planes), each of which may include several memory blocks, e.g., blocks 1-Block z, each of which may include several pages (pages). Illustratively, the nonvolatile memory device 100 performs an erase operation in units of memory blocks, and performs a program operation or a read operation in units of pages.

In an exemplary embodiment, the address decoder 121 may control the bit lines BL, the select lines TSL/BSL, and the word lines WL connected to the memory cell array in response to the control logic circuit 123 (refer to fig. 3). In other words, the address decoder 121 may receive and decode an address ADDR from the control logic circuit 123 and select one of the plurality of memory blocks 1 to Block z in the memory cell array 110 according to the decoded address ADDR (e.g., a column address ADDR-C and a row address ADDR-R). Optionally, one of the pages in the selected memory Block may be selected.

In an exemplary embodiment, the page buffer 122 may be, for example, a cache register. Illustratively, the page buffer 122 may temporarily store data during a program operation and/or a read operation in response to control of the control logic circuit 123 in order to reduce a data transfer time.

The control logic circuit 123 may control the address decoder 121 and the page buffer 122 in response to commands CMD (e.g., program commands and read commands) and addresses ADDR from the I/O circuit 124. Alternatively, the control logic circuit 123 may control the nonvolatile memory device 100 to perform a program operation by, for example, a multi-step method. The multi-step method may perform a program operation multiple times to configure a desired program state, and may include, but is not limited to, a pre/main program method, a re-program method, a shadow program method.

It will be understood by those skilled in the art that the operations performed by the address decoder 121, the page buffer 122, the control logic circuit 123, and the I/O circuit 124 described herein may be performed by processing circuitry. Alternatively, the processing circuitry may include, but is not limited to, hardware of logic circuitry or a hardware/software combination of a processor executing software.

In example embodiments, the nonvolatile memory device 100 may perform a program operation according to a received program command or a read operation according to a received read command. Fig. 2A is a timing diagram of a program operation performed by the nonvolatile memory device 100 according to an embodiment of the present application. Fig. 2B is a timing diagram of the nonvolatile memory device 100 according to the embodiment of the present application performing a read operation. DQx may be represented as a data bus signal, Cycle Type may further represent the Type of data bus signal, and SR [6] may represent a state of the non-volatile memory device 100, such as a program operation or a read operation.

As shown in FIG. 2A, a program command may include, for example, two subcommands (e.g., 80h and 10 h). In an exemplary embodiment, the nonvolatile memory device 100 receives an address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of data on which a program operation is to be performed after receiving the sub-command 80 h. After receiving the address ADDR, the nonvolatile memory device 100 may receive DATA DATA (e.g., D0-Dn) to be programmed and buffer the DATA DATA in the page memory 122. After receiving the sub-command 10h, the nonvolatile memory device 100 writes the DATA in the page buffer 122 to the memory cell array 110 within the programming time tPROG.

As shown in FIG. 2B, the read command may include, for example, two sub-commands (e.g., 00h and 30 h). In an exemplary embodiment, the nonvolatile memory device 100 transfers an address ADDR (e.g., two column addresses C1 through C2 and three row addresses R1 through R3) of data to be read between the received sub commands 00h and 30 h. After the nonvolatile memory device 100 receives the sub-command 30h, the corresponding DATA DATA (e.g., D0-Dn) in the page of the received row address may be buffered in the page buffer 122 for the read time tR, and then the DATA DATA may be read as needed. Alternatively, a corresponding portion of data in a page may be read from the page buffer 122.

Fig. 3 is an equivalent circuit diagram of a memory Block1 according to an embodiment of the present application. The memory Block1 may be the same as or similar to the other memory blocks 2-Blockz in the memory cell array 110, and thus, the memory Block1 is used as an example for further description.

In an exemplary embodiment, as shown in FIG. 3, memory Block1 may comprise a plurality of memory strings, such as MS1 MS 4. The memory strings MS1 through MS4 may be arranged in a two-dimensional array on the xy plane. Each of the memory strings MS1 through MS4 may extend in the z-axis direction and may include, in turn, a top select transistor, e.g., TSTs 1 through TST4, memory cells MC, and a bottom select transistor BST, whose source and drain terminals are connected in series with each other. Alternatively, the memory cell MC may be a charge trap type memory cell, which can change its threshold voltage by using tunneling effect, thereby putting the memory cell MC in different memory states. Alternatively, memory cell MC may include an SLC capable of storing 1bit of data. For an SLC, one memory cell MC has two memory states, for example, according to the number of carriers (e.g., electrons) in a charge trapping layer.

It should be noted that the number of the select transistors TST/BST and/or the memory cells MC in each of the memory strings M1-M4 is only exemplary, and the specific number of the above structures is not specifically limited in the present application.

In an exemplary embodiment, the memory strings MS1 to MS4 in the memory Block1 may be connected to a common source line CSL. For example, the source terminal of the bottom select transistor BST at the end of each memory string MS 1-MS 4 may be connected to a common source line CSL.

In an exemplary embodiment, the gate terminals of the memory cells, e.g., MC 11-MC 14, in the memory strings MS 1-MS 4, located at the same height or a similar height from the common source line CSL may be connected to the same word line, e.g., first word line WL 1. Alternatively, it is possible for the SLC to constitute one page of memory cells MC, e.g., MC11 to MC14, which are connected to the same word line, e.g., the first WL1, and can perform a program operation after receiving a program command. It is to be understood that the memory Block1 may include a plurality of word lines WL, which may correspond to a plurality of pages.

In an exemplary embodiment, gate terminals of top select transistors, e.g., TST1 and TST2, located at the same height or a similar height from the common source line CSL in the memory strings MS1 and MS2 arranged in the y-axis direction may be connected to the same top select line TSL 1. Similarly, the gate terminals of the top select transistors, e.g., TST3 and TST4, located at the same height or a similar height from the common source line CSL in the memory strings MS3 and MS4 arranged in the y-axis direction may be connected to the same top select line TSL 2.

In an exemplary embodiment, the gate terminals of the bottom transistors BST located at the same height or a similar height from the common source line CSL in the memory strings MS1 through MS4 may be connected to the same bottom select line BSL. In other embodiments, similar to the top select lines TSL1 and TSL2, the gate terminals of the bottom select transistors BST in the memory strings arranged in the y-axis direction, e.g., MS1 and MS2, located at the same height or at a similar height from the common source line CSL, may be connected to the same bottom select line BSL1 (not shown). The gate terminals of the bottom select transistors BST located at the same height or a similar height from the common source line CSL in the memory strings arranged in the y-axis direction, for example, MS3 and MS4, may be connected to the same bottom select line BSL2 (not shown).

In an exemplary embodiment, the drain terminals of the top select transistors TST1 and TST3 positioned at the end may be connected to the same bit line BL1 in the memory strings MS1 and MS3 arranged in the x-axis direction, which are positioned at the same height or a similar height from the common source line CSL. The memory strings MS2 and MS4 arranged in the x-axis direction are located at the same height or a similar height from the common source line CSL, and the drain terminals of the top select transistors TST2 and TST4 located at the ends may be connected to the same bit line BL 2.

In an exemplary embodiment, according to the structure as described above, the extension direction of the bit line BL and the extension direction of the top select line TSL may be perpendicular to each other.

It should be noted that the numbers of the memory strings, the word lines, the bit lines, and the select lines in the memory Block1 shown in fig. 2 are merely exemplary, and the number of the above structures is not specifically limited in the present application.

Fig. 4 is a flowchart of a programming method 1000 of a non-volatile memory device according to an embodiment of the present application. As shown in fig. 4, the programming method 1000 may include the steps of:

s110, performing a write operation and a verify operation on at least one first memory cell of a plurality of memory cells connected to a first word line in a first programming time;

and S120, performing writing operation on other memory cells except the first memory cell in the plurality of memory cells connected with the first word line.

It should be understood that the steps shown in the programming method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 4. Steps S110 to S120 will be further described below in conjunction with the hardware structure of the nonvolatile memory device 100 shown in fig. 1 and 3 and the timing chart of the program operation of the nonvolatile memory device 100 shown in fig. 2A.

In example embodiments, the program time tPROG may include several program cycles, each of which may be used to perform a write operation or a write operation and a verify operation on each of a plurality of memory cells connected to the same word line WL.

In an exemplary embodiment, in one programming cycle, as shown in fig. 3, when a write operation is performed on, for example, the memory cell MC11 to which the first word line WL1 is connected, a program voltage (e.g., 15 to 20V) may be applied to the first word line WL1, and the bottom select transistor BST and the top select transistor TST1 on the memory string MS1 to which the memory cell MC11 is located may be turned on, and, for example, a ground voltage may be applied to the bit line BL1 connected to the memory string MS1 to which the memory cell MC11 is located. Under the action of the high voltage of the first word line WL1, carriers (e.g., electrons) tunnel to charge, for example, the charge trapping layer to reach a predetermined threshold voltage range. Alternatively, the top select transistor TST3 and the bottom select transistor BST in MS3 are turned off to inhibit memory cell M13 writing in the memory string MS 3. Optionally, a program-inhibit voltage (e.g., 2V) may be applied to the bit line BL2 to prevent carriers (e.g., electrons) from tunneling to inhibit writing of the memory cell M12 in the memory string MS 2. Alternatively, the program voltage may include a pulse voltage, such as a multi-step pulse voltage. Alternatively, the above-described programming method may be adopted to perform a write operation on the memory cells MC11 to MC14 on the first word line WL1 in units of a program cycle within the program time tPRPG.

In an exemplary embodiment, the memory cells MC11 through MC14 connected to the first word line WL1 may be located in the memory strings MS11 through MS14 having the ordinal numbers, respectively. During the time tPROG, the memory cells MC 11-MC 14 can perform write operations in units of programming cycles according to the serial numbers of the memory strings MS 11-MS 14.

Note that before the write operation is performed on the memory cells MC11 to MC14 connected to the first word line WL1, the memory cells MC1 to MC4 may be in an erased state. Alternatively, for SLC, the erased state may be represented by data of "1", for example. In other words, the data of "1" may be represented before the write operation is not performed on the memory cells MC 11-MC 14. According to an embodiment of the present application, in the process of performing the write operation, the write operation may be performed on the memory cells MC11 to MC14, so that the memory cells MC11 to MC14 after the write operation is performed represent data of "0".

In an exemplary embodiment, a verify operation may be performed on memory cell MC14 after a write operation in one programming cycle. For example, the bit line BL2 may be floated after charging the bit line BL2 connected to the memory string MS4 in which the memory cell MC14 is located to a threshold value, then a conducting voltage (e.g., 5V) may be applied to the word lines WL other than the first word line WL1, the bottom select transistor BST and the top select transistor TST4 on the memory string MS4 in which the memory cell MC14 is located are turned on, the top select transistor TST2 and the bottom select transistor BST of the memory string MS2 in which the memory cell MC12 is located are turned off, and a verifying voltage is applied to the first word line WL1 to sense a current value at the end of the bit line BL2 to obtain a data value of the memory cell MC14, so as to determine whether the threshold voltage of the memory cell M14 after the write operation is in a predetermined threshold voltage interval, so as to determine integrity of the data in the memory cell MC 14.

Note that, the verifying operation may be performed after the writing operation is performed on the memory cell MC in the programming cycle of at least one memory cell MC of the memory cells MC11 to MC14 connected to the first word line WL 1. The verifying operation may be used, for example, to verify whether the memory cell MC reaches a predetermined threshold voltage range after the writing operation, so as to improve data integrity after the programming operation is performed on a plurality of memory cells connected to the same word line.

In the exemplary embodiment, as described above, in the case where the write operation and the verify operation are performed in the program cycle for the memory cell MC14 among the memory cells MC11 to MC14 connected to the first word line WL1, since the memory cells MC11 to MC14 connected to the first word line WL1 sequentially perform, for example, the write operation or the write operation and the verify operation in accordance with the sequence numbers of the located memory strings MS1 to MS4, write disturbance may be caused to M14 during the write operation for the memory cells MC11 to MC13, and the probability of a write error occurring in the memory cell MC14 is high. Therefore, in the process of performing the programming operation on the plurality of memory cells connected to the same word line and located in the memory strings with different sequence numbers, the writing operation and the verifying operation are performed on the memory cell on the memory string with the last sequence number, and the data integrity after the programming operation is performed on the plurality of memory cells connected to the same word line can be further improved.

In an exemplary embodiment, the second word line WL2 may be determined, for example, by a lookup table (lookup table) according to the probability of the defects (e.g., physical defects) of the plurality of word lines being less than a predetermined threshold. As shown in fig. 3, in another programming time (e.g., the second programming time), in each programming cycle, a write operation is performed on the memory cells MC21 to MC24 connected to the second word line WL2 using the above-described write operation method. It can be understood that, in a case where, for example, the defect probability of the second word line WL2 is smaller than a predetermined threshold, the probability of a program error after the program operation is performed on the plurality of memory cells MC21 to MC24 which can be connected to the second word line WL2 is smaller, and therefore, only the write operation is performed on each of the memory cells MC21 to MC24 connected to the second word line WL2, which is advantageous in shortening the program operation time of the plurality of memory cells MC21 to MC24 connected to the second word line WL2 and in increasing the speed of the program operation.

In an exemplary embodiment, the operation of performing step S110 may be performed according to an enable verification command received from, for example, the control device 200 (refer to fig. 5). In other words, the nonvolatile memory device 100 may perform the operation in step S110 after the authentication command is enabled. In other embodiments, the non-volatile memory device 100 may be driven to execute the step S110 according to firmware burned in the non-volatile memory device 100, which is not specifically limited in this application.

Through the research of the inventors, one of the reasons why a memory cell (e.g., an SLC memory cell) fails to write is that a word line connected thereto leaks electricity. Since a plurality of memory cells can be physically connected to the same word line and can perform a program operation within the same program time (i.e., receiving the same program command), in some related art, after performing a program operation on a plurality of memory cells connected to the same word line, a read operation is performed on at least a portion of the plurality of memory cells to determine whether the memory cells are in a correct program state.

In some exemplary embodiments, the method of performing a read operation on at least some memory cells connected to the same word line is similar to the method of performing a program verify operation on, for example, the memory cell MC14 connected to the first word line WL1, which is described above and is not repeated herein.

As described above, after the program operation is performed on a plurality of memory cells connected to the same word line, the read operation may be performed on at least some of the memory cells connected to the word line in accordance with the read operation timing illustrated in fig. 2B. However, for some processes requiring continuous programming, the reading operation may interrupt, for example, the page buffer 122, and may increase the time for, for example, address transmission, data transmission, and data reading during the reading command, which is disadvantageous to shorten the time for the programming process (e.g., continuous programming process) and to increase the programming speed of the non-volatile memory device.

According to some embodiments of the present disclosure, a write operation and a verification operation are performed on a portion of memory cells connected to a same word line, so that a determination process of a program state of the portion of memory cells is performed within a program time, which is beneficial to shortening the program time (e.g., continuous programming) and improving a transmission speed of the nonvolatile memory device on the premise of improving integrity of program data.

Fig. 5 is a functional block diagram of a non-volatile storage system 2000 according to an embodiment of the present application. As shown in fig. 5, the nonvolatile memory system 2000 includes a nonvolatile memory apparatus 100 and a control apparatus 200. Alternatively, the non-volatile storage system 2000 may comprise, for example, a solid state disk.

The memory device 100 may be the same as the non-volatile memory device 100 described in any of the above embodiments, and the description thereof is omitted here.

The control device 200 may control the storage device 100 through, for example, a channel CH, and the storage device 100 may perform an operation based on the control of the control device 200 in response to, for example, a request from the host 300. The memory device 100 may receive a command CMD and an address ADDR from the controller 200 through a channel CH and access a region selected from the memory cell array 110 (refer to fig. 1) in response to the address. In other words, the memory device 100 may perform an internal operation corresponding to the command on the area selected by the address. More specifically, the control device 200 transmits a command to execute the programming method 1000 described in any of the above embodiments and an address ADDR through the channel CH, so that the memory device 100 executes the programming method 1000.

In an exemplary embodiment, the control device 200 may transmit an enable verification command, for example, through the channel CH, to enable the nonvolatile memory device 100 to perform the operation of step S120 as described above after the enable verification command.

The above description is meant as an illustration of preferred embodiments of the application and of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (14)

1. A method of programming a non-volatile memory device, comprising:

performing a write operation and a verify operation on at least one first memory cell among a plurality of memory cells connected to a first word line during a first program time; and

and performing a write operation on memory cells other than the first memory cell among the plurality of memory cells connected to the first word line.

2. The programming method of claim 1, wherein the programming method further comprises:

in a second programming time, a write operation is performed on a plurality of memory cells connected to a second word line, wherein the second word line is different from the first word line.

3. The programming method of claim 2, wherein the programming method further comprises:

and determining the second word line according to the defect probability of each word line being smaller than a preset threshold value.

4. The programming method of claim 1, wherein a plurality of memory cells connected to the first word line are in a memory string having a sequence number, the first memory cell including a memory cell on a memory string having a last sequence number.

5. The programming method of claim 1, wherein the programming method further comprises:

and performing a write operation and a verify operation on at least one first memory cell of a plurality of memory cells connected to the first word line according to the received enable verify command.

6. The programming method of any of claims 1 to 5, wherein the memory cell comprises an SLC.

7. A non-volatile storage device, comprising:

a first word line connected to the plurality of memory cells; and

a peripheral circuit configured to:

performing a write operation and a verify operation on at least one first memory cell among a plurality of memory cells connected to the first word line during a first program time; and

and performing a write operation on memory cells other than the first memory cell among the plurality of memory cells connected to the first word line.

8. The non-volatile storage device of claim 7, wherein the non-volatile storage device further comprises a second word line different from the first word line, the peripheral circuitry further configured to:

and in a second programming time, performing a write operation on a plurality of memory cells connected to the second word line.

9. The non-volatile storage device of claim 8, wherein the peripheral circuitry is further configured to:

and determining the second word line according to the defect probability of each word line being smaller than a preset threshold value.

10. The non-volatile memory device of claim 7, wherein a plurality of memory cells connected to the first word line are in a memory string having a sequence number, the first memory cell comprising a memory cell on the memory string having the last sequence number.

11. The non-volatile storage device of any of claims 7 to 10, wherein the memory cell comprises an SLC.

12. A non-volatile storage system, comprising:

the non-volatile storage device of any of claims 7 to 11; and

a control device configured to and controlling the non-volatile storage device to perform the programming method of any one of claims 1 to 6.

13. The non-volatile storage system of claim 12, wherein the control device is further configured to send an enable-verify command.

14. The non-volatile storage system of claim 12, wherein the non-volatile storage system comprises a solid state disk.

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