CN114765199A - Semiconductor device and method of forming the same - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor device and a method of forming the same, the semiconductor device including a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through the conductive via. The spacer layer is located at the side of the memory structure and covers the sidewall of the memory structure. The first dielectric layer is located on the spacer layer and located at the side of the memory structure. The second dielectric layer is located on the memory structure, the spacer layer and the first dielectric layer. The second conductive line passes through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple with the memory structure. The second conductive line includes a body portion at least partially embedded in the second dielectric layer and an extension portion located below the body portion and laterally protruding from a sidewall of the body portion. The extension portion is electrically connected to the upper electrode of the memory structure and is surrounded and coated by the spacer layer.

Description

Semiconductor device and method of forming the same

technical field

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a memory device and a method for forming the same.

Background technique

Memory devices are widely used in various electronic devices. Among various memory devices, resistive random access memory (RRAM) device has become a kind of non-volatile memory widely studied in recent years due to its advantages of fast operation speed and low power consumption. Generally, an RRAM device has a transistor and a memory structure electrically coupled to the transistor. A conductive via and a conductive line are typically provided over the memory structure, the conductive line being electrically coupled to the memory structure through the conductive via.

In conventional memory device formation processes, after the memory structure is formed, an etching process (eg, reactive ion etching (RIE)) is typically used to pattern the dielectric material over the memory stack structure to form a dielectric material that exposes the memory stack structure. A via hole is formed, and a conductive through hole is formed in the via hole, and then a dielectric layer and a conductive line embedded in the dielectric layer are formed over the conductive through hole. However, in the conventional process, during the process of etching the via hole, the upper portion (eg, the upper electrode) of the memory structure may be exposed to the etching plasma and thus be damaged by the etching process, thereby affecting the reliability of the memory device .

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a semiconductor device including a memory and a method for forming the same, which can improve the durability and reliability of the memory device.

Embodiments of the present invention provide a semiconductor device including a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through the conductive via. The spacer layer flanks the memory structure and covers the sidewalls of the memory structure. A first dielectric layer is on the spacer layer and flanks the memory structure. A second dielectric layer is on the memory structure, the spacer layer, and the first dielectric layer. A second conductive line passes through the second dielectric layer, the first dielectric layer, and the spacer layer to electrically couple with the memory structure. The second conductive line includes a body portion at least partially embedded in the second dielectric layer and an extension portion located below the body portion and laterally protruding from the sidewall of the body portion. The extension portion is electrically connected to the upper electrode of the memory structure and surrounded by the spacer layer.

An embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming a first conductive line over a substrate; forming a memory structure over the first conductive line, the memory structure being electrically connected to a via hole forming a sacrificial layer on the memory structure; forming a spacer layer to cover sidewalls of the memory structure and sidewalls and top surfaces of the sacrificial layer; forming a first dielectric layer, to cover the spacer layer; perform a planarization process to remove at least a portion of the first dielectric layer above the topmost surface of the spacer layer; between the spacer layer and the first dielectric layer forming a second dielectric layer on the electrical layer; performing a patterning process to form an opening at least through the second dielectric layer, the opening exposing a portion of the top surface of the sacrificial layer; removing all the forming the sacrificial layer to form a groove; forming a second conductive line in the opening and the groove to be electrically coupled to the memory structure.

To sum up, the embodiments of the present invention form conductive trenches above the memory structure by forming a sacrificial layer on the memory structure and then performing an etching process. The sacrificial layer acts as an etch stop layer and protects the underlying memory structure from damage during the etch process, thereby improving the durability and reliability of the formed memory device.

Description of drawings

Aspects of the present invention are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1A to 1K illustrate cross-sectional views of a method of forming a semiconductor device according to some embodiments of the present invention;

2A-2C illustrate enlarged views of region R1 in FIG. 1K according to some embodiments of the present invention;

3A to 3D illustrate cross-sectional views of methods of forming semiconductor devices according to other embodiments of the present invention.

Detailed ways

The present invention will be more fully explained with reference to the accompanying drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the figures may be exaggerated for clarity. The same or similar component numbers refer to the same or similar components, and the following paragraphs will not describe them one by one.

1A-1K illustrate methods of forming semiconductor devices according to some embodiments of the present invention. 2A-2C illustrate enlarged views of region R1 in FIG. 1K according to some embodiments of the present invention.

1A, a substrate 100 is provided. The substrate 100 is, for example, a semiconductor substrate. For example, the semiconductor substrate may include a silicon substrate. The silicon substrate may be an undoped silicon substrate or a doped silicon substrate. The doped silicon substrate may be an N-type doped silicon substrate or a P-type doped silicon substrate.

In some embodiments, the substrate 100 includes a first region 100a and a second region 100b. The first area 100a is, for example, a memory area for forming a memory device. The second area 100b is a peripheral area, such as a logic circuit area. A plurality of devices (not shown), such as active devices, passive devices, or combinations thereof, may be formed in and/or on substrate 100 . In some embodiments, the device includes a transistor, such as a metal oxide field effect transistor (MOSFET). The transistor may include a gate disposed on the substrate 100, a gate dielectric layer disposed between the gate and the substrate 100, and source/drain regions disposed in the substrate 100 and on both sides of the gate.

A dielectric layer 101 is formed over the substrate 100 . The dielectric layer 101 may be a single-layer or multi-layer structure. The dielectric layer 101 may comprise a suitable dielectric material such as silicon oxide, and may be formed by a suitable deposition process such as chemical vapor deposition (CVD). Dielectric layer 101 is formed over substrate 100 and covers devices (e.g., transistors) on substrate 100.

Continuing to refer to FIG. 1A , a plurality of conductive lines M1 are formed in the dielectric layer 101 . The conductive lines M1 each include a barrier layer 102 and a conductive layer 103 . The material of the barrier layer 102 may include titanium, tantalum, titanium nitride, tantalum nitride, the like, or a combination thereof. The material of the conductive layer 103 includes metals or metal alloys, such as copper, tungsten, aluminum, alloys thereof, the like, or combinations thereof. In some embodiments, the barrier layer 102 is located between the dielectric layer 101 and the conductive layer 103, and surrounds the sidewalls and the bottom surface of the clad conductive layer 103.

In some embodiments, the method for forming the conductive line M1 includes the following processes: patterning the dielectric layer 101 by, for example, photolithography and etching to form a plurality of conductive trenches in the dielectric layer 101 ; then, using a deposition process (such as , CVD, physical vapor deposition (PVD) or electroplating and other suitable processes to form barrier materials and conductive materials on the top surface of the dielectric layer 101 and in the trenches; perform a planarization process (eg, chemical mechanical polishing (CMP)) ) to remove excess barrier material and conductive material on the top surface of the dielectric layer 101 , and the remaining barrier material and conductive material in the trench form a conductive line M1 . In some embodiments, the top surfaces of barrier layer 102 and conductive layer 103 of conductive line M1 are substantially flush with the top surface of dielectric layer 101.

In some embodiments, a plurality of conductive features (not shown), such as conductive contacts, conductive vias, and/or conductive lines, are also included in the dielectric layer 101 . The conductive features are located under the conductive line M1 and electrically connect the conductive line M1 to the devices formed on the substrate 100. For example, in the first region 100a, the conductive line M1 may be electrically connected to the transistors on the substrate 100 through the conductive contacts below it. In some embodiments, the conductive contact lands on the drain region of the transistor.

Continuing to refer to FIG. 1A , an etch stop layer 105 is formed on the dielectric layer 101 and the conductive line M1 . The material of the etch stop layer 105 is different from the material of the dielectric layer 101 . In some examples, the etch stop layer 105 may include silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. The formation method of the etch stop layer 105 may include a suitable deposition process such as CVD.

Referring to FIG. 1B , a dielectric layer 106 is formed on the etch stop layer 105 . The material of dielectric layer 106 may be similar to that of dielectric layer 101, such as being or including silicon oxide, silane, the like, or combinations thereof. The method of forming the dielectric layer 106 may include CVD. A patterned mask layer 107 is formed on the dielectric layer 106 . The patterned mask layer 107 includes a plurality of mask openings 107a to expose portions of the top surface of the dielectric layer 106 . The patterned mask layer 107 is used to define a plurality of vias in the dielectric layer 106 and the etch stop layer 105 . In some embodiments, the patterned mask layer 107 may be or may include a patterned photoresist, and may be formed by a photolithography process.

Referring to FIG. 1C , an etching process is performed using the patterned mask layer 107 as an etch mask to remove portions of the dielectric layer 106 and the etch stop layer 105 exposed by the mask openings 107 a , and the dielectric layer 106 and the etch stop layer 105 are removed. A plurality of openings 108 are formed in the etch stop layer 105 . The opening 108 penetrates the dielectric layer 106 and the etch stop layer 105 to expose a portion of the top surface of the conductive line M1. In some embodiments, the openings 108 may be vias.

Referring to FIGS. 1C and 1D , the patterned mask layer 107 is removed, for example, using ashing or stripping. Next, a conductive via V2 is formed in the via hole 108 to be electrically connected to the conductive line M1. In some embodiments, the conductive via V2 includes the barrier layer 109 and the conductive pillar 110 . The materials of the barrier layer 109 and the conductive pillars 110 may be selected from the same candidate materials as the barrier layer 102 and the conductive layer 103, respectively, and may be the same or different from the materials of the barrier layer 102 and the conductive layer 103, respectively. In some embodiments, conductive pillars 110 and conductive layer 103 use different metal materials. For example, conductive layer 103 includes copper, and conductive pillar 110 includes tungsten. However, the present invention is not limited thereto.

In some embodiments, the method of forming conductive via V2 includes forming (eg, depositing) a barrier material and a conductive material on the top surface of dielectric layer 106 and via 108 . Next, a planarization process (eg, CMP) is used to remove excess barrier material and conductive material on the top surface of the dielectric layer 106 , and the remaining barrier layer 109 and conductive pillars 110 in the via holes 108 form conductive vias v2. In some embodiments, the top surface of the barrier layer 109 of the conductive via V2 and the top surface of the conductive pillar 110 are substantially flush with the top surface of the dielectric layer 106.

1E , a plurality of stacked structures 120 are formed on the dielectric layer 106 and the conductive vias V2 in the first region 100a. The stacked structures 120 include a memory structure MS and a sacrificial layer 115 formed on the memory structure MS. In some embodiments, the memory structure MS is, for example, a data storage structure for resistive random access memory (RRAM). That is, the memory structure MS may be a resistor structure. The memory structure MS is electrically coupled to the source/drain regions of the transistors on the substrate 100 through conductive vias V2 and conductive lines M1. Each memory structure MS and the corresponding transistor constitute a memory cell. In some embodiments, the memory cells are in a 1-transistor-1-resistor (1-transistor-1-resistor, 1T1R) configuration and form an RRAM cell. However, the present invention is not limited thereto.

In some embodiments, the memory structure MS is a stacked structure including a plurality of electrode layers 112 and dielectric layers 113 that are alternately stacked. For example, the memory structure MS may include, from bottom to top, a first electrode layer 112a, a first dielectric layer 113a, a second electrode layer 112b, a second dielectric layer 113b, and a third electrode layer 112c (the electrode layers 112a, 112b). , 112c may be collectively referred to as the electrode layer 112, and the dielectric layers 113a, 113b may be collectively referred to as the dielectric layer 113). The dielectric layers 113 are sandwiched between the corresponding two electrode layers, respectively. In some embodiments, the bottom electrode layer 112a may be referred to as a lower electrode or a bottom electrode, and the top electrode layer 112c may be referred to as an upper electrode or a top electrode.

Although FIG. 1E uses three electrode layers 112 and two dielectric layers 113 as an example to illustrate the memory structure MS, the number of electrode layers and dielectric layers included in the memory structure MS is not limited thereto. The memory structure MS includes at least two electrode layers and a dielectric layer sandwiched between the two electrode layers. For example, the second dielectric layer 113b and the third electrode layer 112c may be selectively formed, and may be omitted in some embodiments. In such embodiments, the memory structure MS may include only the first electrode layer 112a, the first dielectric layer 113a, and the second electrode layer 112b from bottom to top. In still other embodiments, the memory structure MS may include more alternately stacked dielectric layers and electrode layers stacked over the third electrode layer 112c.

The material of the electrode layer 112 may include metal, metal nitride, the like, or a combination thereof. For example, the electrode layer 112 may include titanium, titanium nitride, tantalum, tantalum nitride, platinum, tungsten, ruthenium, or combinations thereof, or other suitable metal materials. The materials of the different electrode layers 112 may be the same or different from each other. In some embodiments, the first electrode layer 112a and the third electrode layer 112c include titanium, and the second electrode layer 112b includes titanium nitride. However, the present invention is not limited to this.

In some embodiments, the material of the dielectric layer 113 includes a variable resistance dielectric material, and may be referred to as a variable resistance layer. The variable resistance dielectric material includes, for example, metal oxides such as hafnium oxide (HfO _x ), tungsten oxide (WO _x ), the like, or combinations thereof.

The sacrificial layer 115 is formed on the topmost layer (eg, the third electrode layer 112c) of the memory structure MS to cover the top surface of the electrode layer 112c on top of the memory structure MS. In some embodiments, the sacrificial layer 115 may also be referred to as a protective layer or a capping layer. The material of the sacrificial layer 115 may include suitable materials different from those of the electrode layer 112 and the subsequently formed spacer and dielectric layers. In some embodiments, the sacrificial layer 115 includes a semiconductor material, such as polysilicon. However, the present invention is not limited to this.

Continuing to refer to FIG. 1E , in some embodiments, the method for forming the memory structure MS and the sacrificial layer 115 includes: sequentially forming a dielectric layer 106 and a conductive via V2 through a suitable deposition process (eg, CVD, PVD), respectively. each electrode material layer, dielectric material layer, and sacrificial material layer in the memory structure MS; then the sacrificial material layer, electrode material layer and dielectric material layer are patterned by photolithography and etching to form the first region Stacked structure 120 including memory structure MS and sacrificial layer 115 in 100a. In some embodiments, the sidewalls of the respective electrode layers 112 and the dielectric layers 113 and the sidewalls of the sacrificial layer 115 of the memory structure MS are substantially aligned in a direction perpendicular to the top surface of the substrate 100 . However, the present invention is not limited to this.

Referring to FIG. 1F , a spacer layer 122 and a dielectric layer 123 are formed over the substrate 100 . The spacer layer 122 covers the top surface of the dielectric layer 106 and the top surfaces and sidewalls of the plurality of stacked structures 120. In some embodiments, spacer layer 122 is conformally formed on dielectric layer 106 and stack structure 120. The spacer layer 122 includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof, and may be deposited by a suitable method such as CVD, atomic layer deposition (ALD), or the like Process formed. Spacer layer 122 may also be referred to as a layer of spacer material.

The dielectric layer 123 is formed on the spacer layer 122 and covers the surface of the spacer layer 122 . The dielectric layer 123 may include, for example, a dielectric material such as silicon oxide, and may be formed by a deposition process such as CVD, high density plasma (HDP) CVD, or the like. The material of the dielectric layer 123 may be similar to or different from the material of the spacer layer 122 . In some embodiments, the spacer layer 122 may serve as a stop layer in subsequent processes, such as a CMP stop layer or an etch stop layer.

1F-1G, in some embodiments, a planarization process (eg, CMP) is performed to remove at least a portion of the dielectric layer 123 and form a dielectric layer 123a. In some embodiments, a planarization process is performed to remove the portion of the dielectric layer 123 over the topmost surface of the spacer layer 122 until the topmost surface of the spacer layer 122 is exposed. That is, the spacer layer 122 acts as a CMP stop layer. In some embodiments, after the planarization process, the dielectric layer 123a is located on the spacer layer 122 and its sides, and the top surface of the dielectric layer 123a is substantially flush with the top surface of the spacer layer 122. However, the present invention is not limited to this.

Referring to FIG. 1H, a dielectric layer 125 is formed over the dielectric layer 123a, eg, by a deposition process (eg, CVD). The dielectric layer 125 may include silicon oxide. A patterned mask layer 126 is then formed on the dielectric layer 125 . The patterned mask layer 126 may include patterned photoresist and has a plurality of mask openings 126a and 126b to expose portions of the top surface of the dielectric layer 125 . In some embodiments, the mask opening 126a is located in the first region 100a and at least a portion of the mask opening 126a is located directly above the stack structure 120 . The mask opening 126b is located in the second region 100b, and at least a portion of the mask opening 126b is located directly above the conductive via V2. In some embodiments, the mask openings 126a and 126b are trenches extending in a direction perpendicular to the page and are used to define conductive trenches.

1H and FIG. 1I, an etching process, such as reactive ion etching (RIE), is performed using the patterned mask layer 126 as an etching mask to form openings 127a and 127b. In some embodiments, the spacer layer 122 acts as an etch stop layer, and the etch process proceeds until the spacer layer 122 exposed by the mask openings 127a/127b is removed and the spacer layer 122a is formed. In the first region 100a, the etch process removes a portion of the dielectric layer 125 and a portion of the spacer layer 122 exposed by the mask opening 126a and forms an opening 127a. In the second region 100b, the etching process removes a portion of the dielectric layer 125, a portion of the dielectric layer 123a, and a portion of the spacer layer 122 exposed by the mask opening 126b, and an opening 127b is formed. In some embodiments, openings 127a and 127b are conductive trenches and extend at least partially in a direction perpendicular to the page. The opening 127a is located in the first region 100a through the dielectric layer 125 and the spacer layer 122a to expose a portion of the top surface of the sacrificial layer 115 of the stack structure 120. Opening 127b is located in second region 100b through dielectric layer 125, dielectric layer 123a, and spacer layer 122a to expose the top surface of conductive via V2 and a portion of the top surface of dielectric layer 106.

In some embodiments, the width of the mask opening 126a is smaller than the width of the stack structure 120 such that the width W1 of the opening 127a formed is smaller than the width W2 of the stack structure 120 . After the etching process, a portion of the top surface of the sacrificial layer 115 is exposed by the opening 127a, while another portion (e.g., an edge portion) of the top surface of the sacrificial layer 115 is covered by the spacer layer 122a and the dielectric layer 125 over it. In some embodiments, the width of the mask opening 126b and the width of the opening 127b it defines may be greater than the width of the corresponding conductive via V2.

In the above etching process, since the sacrificial layer 115 is disposed on the memory structure MS, exposure of the memory structure MS to etching plasma can be avoided, and thus the sacrificial layer 115 can protect the memory structure MS under it from the damage of the etching process. After the etching process, the patterned mask layer 126 is removed, eg, using ashing or stripping. In some embodiments, a cleaning process may be further performed to remove by-products and/or residues that may be generated during the etching process and/or removal of the patterned mask layer 126.

Referring to FIGS. 1I and 1J , the sacrificial layer 115 is removed to form recesses 128 at locations previously occupied by the sacrificial layer 115 to expose the memory structure MS. In some embodiments, the sacrificial layer 115 is removed by an etching process, such as a wet etching process. The etch process has a high etch selectivity ratio of the sacrificial layer 115 to the memory structure MS (eg, electrode layer 112 ), and may have a high etch selectivity ratio of the sacrificial layer 115 to other adjacent layers (eg, dielectric layer 125 , spacer layer 122 a ) High etch selectivity. For example, the etchant used in the wet etching process may include Rezi-38, but the invention is not limited thereto. In some embodiments, the entire layer of sacrificial layer 115 (including the portion covered by the spacer layer) is completely removed, while other layers adjacent to it are substantially not removed. Since the wet etching process does not use etching plasma and has a high etching selectivity ratio of the sacrificial layer 115 to the memory structure MS, the etching process does not cause damage to the memory structure MS. In some embodiments, the spacer layer 122a may be slightly damaged during removal of the sacrificial layer 115 to remove a small portion. In other embodiments, the spacer layer 122a is not substantially removed. In some embodiments, after removing the sacrificial layer 115, a cleaning process may be further performed to remove by-products and/or residues that may be generated by the etching process. The cleaning process may, for example, use Sc1 cleaning fluid.

1J, in some embodiments, after removal of sacrificial layer 115, portions of spacer layer 122a overhang memory structure MS, recess 128 is formed under opening 127a and between memory structure MS and spacer layer 122a between. The recess 128 or a portion of the recess 128 may also be referred to as the gap between the memory structure MS and the spacer layer 122a above it. Recess 128 is in spatial communication with opening 127a and is defined by the top surface of memory structure MS and a portion of the sidewall and bottom surface of spacer layer 122a. In some embodiments, the width of the groove 128 is substantially equal to the width of the memory structure MS and is greater than the width of the opening 127a. In other embodiments where some of the spacer layer 122a may be partially removed by an etch process, the width of the recess 128 may be slightly larger than the width of the memory structure MS.

Referring to FIG. 1K , a conductive line M2 is formed in the openings 127 a , 127 b and the groove 128 . The conductive line M2 includes the conductive line M2a located in the opening 127a and the groove 128 and the conductive line M2b located in the opening 127b. Conductive line M2a is in electrical connection and physical contact with top electrode 112c of memory structure MS. The conductive line M2b is electrically connected to and in physical contact with the conductive via V2. In some embodiments, the conductive lines M2 each include a barrier layer 129 and a conductive layer 130 . The material and formation method of the conductive line M2 are similar to those of the conductive line M1. For example, the formation of the conductive line M2 may include the following process: after forming the groove 128, forming a barrier material and a conductive material over the substrate 100 to cover the surface of the dielectric layer 125 and fill the openings 127a, 127b and Groove 128 . A planarization process (eg, CMP) is then performed to remove excess barrier material and conductive material above the top surface of the dielectric layer 125 , the barrier layer 129 and the conductive layer 130 remaining in the openings 127 a and the recesses 128 The conductive layer M2a is constituted, and the barrier layer 129 and the conductive layer 130 remaining in the opening 127b constitute the conductive line M2b. In some embodiments, the top surface of barrier layer 129 of conductive line M2 and the top surface of conductive layer 130 are substantially flush with the top surface of dielectric layer 125.

Continuing to refer to FIG. 1K , so far, the semiconductor device 500A has been formed. In some embodiments, semiconductor device 500A includes substrate 100, conductive lines M1 embedded in dielectric layer 101, conductive vias V2, memory structures MS, and conductive lines M2a and M2b. The conductive via V2 is embedded in and through the dielectric layer 101 and the etch stop layer 105, and is electrically connected to the conductive line M1. The memory structure MS and the conductive line M2a are located in the first region 100a and are electrically coupled to the conductive line M1 through the conductive via V2. The conductive line M2b is located in the second region 100b and passes through the dielectric layers 125, 123a and the spacer layer 122a to be electrically connected to the conductive via V2.

The memory structure MS is located on the dielectric layer 106 and the conductive via V2, and is surrounded by the spacer layer 122a. In some embodiments, a portion FP of the spacer layer 122a overlies the topmost surface of the memory structure MS (eg, the top surface of the electrode layer 112c ) and is spaced a non-zero distance from the topmost surface of the memory structure MS . The portion FP of the spacer layer 122a may also be referred to as an overlying portion FP. In other words, there is a gap between the overlying portion FP of the spacer layer 122a and the topmost surface of the memory structure MS. In some embodiments, the cross-sectional shape of the overlying portion FP of the spacer layer 122a is a square, a rectangle, or the like, as shown in enlarged FIG. 2A , but the present invention is not limited thereto. In other embodiments, the overlying portion FP of the spacer layer 122a may be partially removed during the process of removing the sacrificial layer 115, and thus the cross-sectional shape of the overlying portion FP may be a trapezoid, a triangle, or the like. Other suitable shapes, and the surface of the overlying portion FP contacting the conductive line M2a may be inclined or arc-shaped, as shown in enlarged FIG. 2B .

In some embodiments, the conductive line M2a passes through the dielectric layer 125, the dielectric layer 123a, and the spacer layer 122a, and fills the gap between the spacer layer 122a and the memory structure MS to connect with the electrode layer of the memory structure MS 112c is in physical contact and electrically connected. In other words, the conductive wire M2a has a main body portion P1 and an extension portion P2 located below the main body portion P1. In some embodiments, the body portion P1 is embedded in the overlying portion FP of the dielectric layer 125, the dielectric layer 123a, and the spacer layer 122a. The extension portion P2 is located between the main body portion P1 and the memory structure MS, protrudes laterally from the sidewall of the main body portion P1 and extends between the overlying portion FP of the spacer layer 122a and the memory structure MS. That is, the overlying portion FP of the spacer layer 122a and the topmost surface of the memory structure MS are spaced apart by the extension P2 of the conductive line M2a located therebetween. In this embodiment, the top surface of the extension portion P2 is covered by the overlying portion FP of the spacer layer 122a, and is lower than the top surface of the spacer layer 122a and the top surface of the dielectric layer 123a.

In some embodiments, the main body portion P1 is, for example, line-shaped, and extends at least partially in a direction perpendicular to the paper surface, and is connected to the upper portion of the dielectric layer 125 , the dielectric layer 123 a and the spacer layer 122 a The sidewalls of the cladding portion FP are in physical contact. The extension portion P2 is located on the memory structure MS, and is in physical contact with and electrically connected to the electrode layer 112c. In some embodiments, the stack including the memory structure MS and the extension P2 has a pillar structure and is surrounded by the spacer layer 122a. A portion (eg, an edge portion) of a sidewall and a top surface of the extension P2 is in physical contact with the spacer layer 122a. In some embodiments, from a top view (not shown), the memory structure MS and extension P2 may, for example, be circular, oval, similar, or other suitable shapes, and the vertical extension of the spacer layer 122a The portion of , for example, may be annular, surrounding and contacting the memory structure MS and the sidewalls of the extension P2. Rings may include circular rings, elliptical rings, or other types of rings.

The width W1' of the main body portion P1 is smaller than the width W2' of the extension portion P2. Herein, the widths of the main body part P1 and the extension part P2 refer to their widths in a direction perpendicular to the extending direction of the main body part P1 (eg, a direction parallel to the paper surface and parallel to the top surface of the substrate 100 ). In some embodiments, the width W2 ′ of the extension P2 of the conductive line M2 a is substantially equal to the width of the memory structure MS, and the sidewall of the extension P2 and the sidewall of the memory structure MS are perpendicular to the top surface of the substrate 100 . The directions may be substantially aligned, but the present invention is not limited thereto. In some embodiments where a portion of the spacer layer 122a is also removed during the removal of the sacrificial layer 115, the width of the groove 128 may be greater than the width of the memory structure MS, such that an extension of the conductive line M2a formed therein The width of P2 is also greater than the width of the memory structure MS, as shown in enlarged Figure 2C. In other words, the extension P2 may protrude laterally from the sidewall of the memory structure MS, and the portion of the extension P2 protruding from the memory structure MS may be embedded in the spacer layer 122a.

3A to 3D are cross-sectional views of methods of forming semiconductor devices according to other embodiments of the present invention. This embodiment is similar to the previous embodiment, except that in this embodiment, the planarization process of FIGS. 1F to 1G is stopped at the sacrificial layer 115 .

Referring to FIGS. 1F and 3A , in some embodiments, after the dielectric layer 123 is formed, a planarization process (eg, CMP) is performed to remove a portion of the dielectric layer 123 over the top surface of the stacked structure 120 and A portion of the spacer layer 122 and form the spacer layer 122b and the dielectric layer 123b on the sides of the stack structure 120 . After the planarization process, the top surface of the sacrificial layer 115 is exposed, and the top surface of the dielectric layer 123b and the top surface of the spacer layer 122b are substantially flush with the top surface of the sacrificial layer 115.

Referring to FIG. 3B, a dielectric layer 125 is formed on the stack structure 120, the dielectric layer 123b and the spacer layer 122b. Next, an opening 127a is formed in the dielectric layer 125 of the first region 100a to expose part of the top surface of the sacrificial layer 115, for example, by photolithography and etching; and the dielectric layers 125, 123b and the spacer layer in the second region 100b An opening 127b is formed in 122b to expose the top surface of the conductive via V2 and a portion of the top surface of the dielectric layer 106 . The openings 127a and 127b are, for example, trenches. In some embodiments, openings 127a and 127b may be formed simultaneously or separately.

Referring to FIGS. 3B and 3C , the sacrificial layer 115 is removed, eg, using wet etching, to form grooves 128 under the openings 127a. The groove 128 is in spatial communication with the opening 127a, is located between the memory structure MS and the dielectric layer 125, and is defined by the top surface of the memory structure MS, the sidewalls of the spacer layer 122b, and the bottom surface of the dielectric layer 125. After removing the sacrificial layer 115, a cleaning process may be performed to remove by-products and/or residues that may result from the etching process.

3D, a conductive line M2a is formed in the opening 127a and the groove 128, and a conductive line M2b is formed in the opening 127b. So far, the semiconductor device 500B is completed. In the semiconductor device 500B, the spacer layer 122b does not have the overlying portion of the foregoing embodiment. The conductive lines M2a are filled in the grooves 128 and are in contact with the bottom surface of the dielectric layer 125 .

The conductive wire M2a has a main body portion P1' and an extension portion P2' located below the main body portion P1' and laterally protruding from the sidewall of the main body portion P1'. In this embodiment, the body portion P1' is embedded in the dielectric layer 125. The extension P2' is located between the memory structure MS and the body portion P1', and between the memory structure MS and the dielectric layer 125. The portion of the extension portion P2' protruding from the main body portion P1' is in contact with the sidewall of the spacer layer 122b and the bottom surface of the dielectric layer 125. In some embodiments, the top surface of the extension P2' is substantially flush with the top surface of the spacer layer 122b and the top surface of the dielectric layer 123b. Other features of the semiconductor device 500B are similar to those of the semiconductor device 500A of FIG. 1K , and are not repeated here.

In the above embodiments, the concept of the present invention is described by taking the memory structure MS as an example of the memory structure of the RRAM device, but the present invention is not limited thereto. The present invention can also be applied to other types of memory devices, such as dynamic random access memory (DRAM) and the like. For example, in some embodiments, the material of the variable resistance layer of the memory structure MS may be replaced with a dielectric material (eg, a high-k dielectric material), such that the memory structure forms a capacitor and is connected to the liner The transistors on the bottom are electrically coupled to form memory cells of the DRAM device.

In an embodiment of the present invention, after the sacrificial layer is formed on the memory structure, an etch process (e.g., RIE) is performed to form wire trenches over the memory structure, and the etch process stops at the sacrificial layer. In this way, the RIE process for forming conductive vias exposing the memory structure in the conventional method is omitted, and in the etching process for forming the wire trenches of the present invention, the sacrificial layer can prevent the underlying memory structure from being exposed to etching plasma, and thus protect the memory structure from damage by the etching plasma. In turn, the performance of the formed memory device, such as the endurance reliability, can be improved, and the product yield can be improved.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the appended claims.

Claims (11)

1. A semiconductor device, comprising:

a first conductive line disposed over a substrate;

a memory structure located over the first conductive line and electrically coupled to the first conductive line through a conductive via;

a spacer layer located at a side of the memory structure and covering a sidewall of the memory structure;

a first dielectric layer on the spacer layer and on a side of the memory structure;

a second dielectric layer over the memory structure, the spacer layer, and the first dielectric layer; and

a second conductive line passing through the second dielectric layer, the first dielectric layer, and the spacer layer to electrically couple with the memory structure, the second conductive line comprising:

a body portion at least partially embedded in the second dielectric layer; and

and an extension portion located below the main body portion and electrically connected to the upper electrode of the memory structure, wherein the extension portion laterally protrudes from a sidewall of the main body portion and is surrounded and coated by the spacer layer.

2. The semiconductor device of claim 1, wherein a width of the extension portion is greater than a width of the body portion.

3. The semiconductor device of claim 1, wherein the spacer layer further comprises an overlying portion overlying the memory structure, and the overlying portion is spaced apart from the upper electrode of the memory structure by a portion of the extension portion therebetween.

4. The semiconductor device according to claim 1, wherein a portion of the extension portion protruding from the body portion is located between the memory structure and the second dielectric layer and is in contact with a bottom surface of the second dielectric layer.

5. The semiconductor device of claim 1, wherein a topmost surface of the spacer layer is flush with a top surface of the first dielectric layer and is in contact with a bottom surface of the second dielectric layer.

6. The semiconductor device of claim 5, wherein a top surface of the extension of the second conductive line is flush with or below the topmost surface of the spacer layer and the top surface of the first dielectric layer.

7. The semiconductor device of claim 1, wherein the memory structure comprises a resistive random access memory structure and comprises at least a lower electrode, an upper electrode, and a variable resistance layer disposed between the upper electrode and the lower electrode.

8. A method of forming a semiconductor device, comprising:

forming a first conductive line over a substrate;

forming a memory structure over the first conductive line, the memory structure being electrically connected to the first conductive line by a conductive via;

forming a sacrificial layer on the memory structure;

forming a spacer layer to cover sidewalls of the memory structure and sidewalls and a top surface of the sacrificial layer;

forming a first dielectric layer to cover the spacer layer;

performing a planarization process to remove at least a portion of the first dielectric layer over a topmost surface of the spacer layer;

forming a second dielectric layer on the spacer layer and the first dielectric layer;

performing a patterning process to form an opening through at least the second dielectric layer, the opening exposing a portion of the top surface of the sacrificial layer;

removing the sacrificial layer to form a groove;

forming a second conductive line in the opening and the recess to electrically couple to the memory structure.

9. The method of forming a semiconductor device according to claim 8, wherein the patterning process removes a portion of the second dielectric layer and a portion of the spacer layer, and the opening is formed in the second dielectric layer and the spacer layer.

10. The method of forming a semiconductor device according to claim 8, wherein the planarization process further comprises removing a portion of the spacer layer on the top surface of the sacrificial layer to expose the top surface of the sacrificial layer.

11. The method for forming a semiconductor device according to claim 8, wherein a width of the opening is formed to be smaller than a width of the sacrificial layer so that the width of the opening is smaller than a width of the groove formed by removing the sacrificial layer, wherein the second conductive layer has a main portion located in the opening and an extension portion located in the groove, and wherein the extension portion protrudes laterally beyond a sidewall of the main portion.

Images