CN114758954B - Method for preparing trench gate field effect transistor - Google Patents
Method for preparing trench gate field effect transistorInfo
- Publication number
- CN114758954B CN114758954B CN202210350829.9A CN202210350829A CN114758954B CN 114758954 B CN114758954 B CN 114758954B CN 202210350829 A CN202210350829 A CN 202210350829A CN 114758954 B CN114758954 B CN 114758954B
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- gate
- trench
- oxide layer
- substrate
- effect transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
- H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明提供了一种沟槽栅场效应晶体管的制备方法。通过刻蚀栅极沟槽的顶角以形成平缓的过渡段，降低了刻蚀过程中在沟槽顶角位置的刻蚀速率，从而使得沟槽顶角上的氧化层不会被快速消耗而能够被保留，有效避免了栅电极和阱区之间发生离子扩散的问题。
This invention provides a method for fabricating a trench gate field-effect transistor. By etching the apex of the gate trench to form a gentle transition section, the etching rate at the trench apex is reduced during the etching process. This prevents the oxide layer at the trench apex from being rapidly consumed and allows it to be retained, effectively avoiding the problem of ion diffusion between the gate electrode and the well region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a trench gate field effect transistor.
Background
In a trench gate field effect transistor, a gate structure is disposed within a gate trench of a substrate and a well region and a source region are formed in the substrate at a side of the gate trench. Currently, a method for manufacturing a trench gate field effect transistor generally includes first forming a gate electrode in a gate trench of a substrate, and then forming a well region in the substrate at a side of the gate trench. However, in the trench gate field effect transistor formed according to the current manufacturing process, the problem of ion interdiffusion easily occurs between the gate electrode and the well region, so that the electrical performance of the device is drifted.
Disclosure of Invention
The invention aims to provide a preparation method of a trench gate field effect transistor, which aims to solve the problem that ion interdiffusion easily occurs between a gate electrode and a well region in the conventional trench gate field effect transistor.
In order to solve the technical problems, the invention provides a preparation method of a trench gate field effect transistor, which comprises the steps of forming a gate trench in a substrate, forming a gate oxide layer and a gate electrode, wherein the gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, the gate electrode is filled in the gate trench, etching the gate oxide layer on the top surface of the substrate until the top angle of the gate trench is exposed, and etching the top angle of the gate trench to form a transition section, forming an oxide layer at least on the transition section, and performing an ion implantation process to form a well region in the substrate on the side edge of the gate trench.
Optionally, during the etching back of the gate oxide layer on the top surface of the substrate, the etching rate at the top corner position of the gate trench is higher than the etching rate at the top surface of the substrate, so that when the top corner of the gate trench is exposed, a part of the gate oxide layer remains on the top surface of the substrate.
Optionally, isotropically etching the exposed top corners of the gate trench to form the transition section.
Optionally, after forming the transition section, a first thermal annealing process is performed, and the transition section is oxidized to form the oxide layer during the thermal annealing process.
Optionally, the first thermal annealing process includes performing a thermal annealing process in an oxygen atmosphere.
Optionally, in the first thermal annealing process, the top surface of the substrate is oxidized to form an oxide layer, and before the ion implantation process is performed, an etching back process is performed to reduce the thickness of the oxide layer on the top surface of the substrate.
Optionally, the oxide layer on the top surface of the substrate is thinned to a thickness of less than 300 angstroms.
Optionally, after performing the ion implantation process, a second thermal annealing process is performed.
Optionally, the inclination angle of the side wall of the grid groove relative to the height direction is less than or equal to 5 DEG
Optionally, the trench gate field effect transistor is a shielded gate field effect transistor. And forming a shielding electrode in the gate trench before forming the gate electrode.
In the preparation method of the trench gate field effect transistor provided by the invention, the apex angle of the gate trench is etched to convert the apex angle position of the gate trench from a convex sharp angle structure into a flatter transition section (for example, an arc-shaped structure), so that the etching rate at the apex angle position of the trench in the etching process is reduced, the oxide layer on the apex angle of the trench cannot be rapidly consumed and can be reserved, and the problem of ion diffusion between the gate electrode and the well region is effectively avoided.
Further, the oxide layer at the top corner position of the gate trench (i.e., the oxide layer formed on the transition section) can be formed while the thermal annealing treatment is performed on the gate electrode, which is beneficial to reducing the preparation steps and simplifying the process.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a trench gate field effect transistor according to an embodiment of the invention.
Fig. 2-9 are schematic structural diagrams of a trench gate field effect transistor according to an embodiment of the present invention during the fabrication process.
Wherein, the reference numerals are as follows:
100-a substrate;
110-gate trenches;
210-an insulating dielectric layer;
220-gate oxide;
310-shielding the electrode;
320-gate electrode;
400-oxide layer;
500-well region.
Detailed Description
As described in the background, the conventional trench gate field effect transistor often has an offset electrical performance due to ion diffusion between the gate electrode and the well region. In this regard, the inventors of the present invention have found through studies that one diffusion channel in which ion diffusion occurs between the gate electrode in the gate trench and the well region on the side of the gate trench is mainly the top corner position of the gate trench.
In particular, it is often desirable to thin a film layer on the top surface of the substrate before performing an ion implantation process to form the well region, so that ions can be implanted into the substrate. However, when an etching process is performed to thin a film layer on the top surface of the substrate, an etching rate to the top corner position of the gate trench is large, so that the film layer at the top corner of the trench is consumed to expose the top corner of the gate trench. In this way, when the high temperature thermal annealing process is performed to activate the doped ions in the well region, the ions in the gate electrode and the ions in the well region are caused to diffuse into each other through the top corners of the trench.
In view of this, the present invention provides a method for manufacturing a trench gate field effect transistor, specifically referring to fig. 1, the method includes the following steps.
In step S100, a gate trench is formed in a substrate, and a gate oxide layer covering an inner wall of the gate trench and a top surface of the substrate and a gate electrode filled in the gate trench are formed.
Step S200, etching back the gate oxide layer on the top surface of the substrate until the top corners of the gate trench are exposed, and etching the top corners of the gate trench to form a transition section.
And step S300, forming an oxide layer at least on the transition section.
In step S400, an ion implantation process is performed to form a well region in the substrate beside the gate trench.
In the preparation method of the trench gate field effect transistor, the apex angle of the gate trench is converted into the gentle transition section, so that the etching rate at the apex angle position of the gate trench is reduced, the oxide layer on the apex angle of the trench can be well reserved, and the problem of ion diffusion between the gate electrode and the well region is avoided. Particularly, an oxide layer at the top corner position of the gate trench can be formed at the same time of carrying out thermal annealing treatment on the gate electrode, which is beneficial to reducing preparation steps and simplifying the process.
The method for manufacturing the trench gate field effect transistor according to the present invention is described in further detail below with reference to fig. 2 to 9 and the specific embodiment, wherein fig. 2 to 9 are schematic structural diagrams of the trench gate field effect transistor according to an embodiment of the present invention during the manufacturing process. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It will be appreciated that relative terms such as "above," "below," "top," "bottom," "above," and "below" as illustrated in the figures may be used to describe various element relationships to one another. These relative terms are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element, for example, will now be below the element.
In step S100, referring specifically to fig. 2-4, a gate trench 110 is formed in a substrate 100 (e.g., a silicon substrate), and a gate oxide layer 220 and a gate electrode 320 are formed, wherein the gate oxide layer 220 covers the inner wall of the gate trench 110 and the top surface of the substrate 100, and the gate electrode 320 is filled in the gate trench 110.
Specifically, the method for forming the gate trench 110 includes, for example, first, forming a mask layer on the top surface of the substrate 100 to define the pattern of the gate trench by using the mask layer, and then, etching the substrate 100 by using the mask layer as a mask to form the gate trench 110. In this embodiment, the sidewall of the gate trench 110 may be a vertical sidewall or a sidewall close to vertical. That is, the sidewall of the gate trench 110 has a small inclination angle with respect to the height direction, for example, an inclination angle of 5 ° or less, and even further, an inclination angle of 1 ° or less may be used. It should be noted that, the "inclination angle of the sidewall of the gate trench 110 with respect to the height direction" as described herein is an included angle between the sidewall of the gate trench 110 and the height direction.
After forming the gate trench 110, a gate structure may be formed within the gate trench 110. In this embodiment, the trench gate field effect transistor is specifically a shielded gate field effect transistor (SHIELDED GATE TRENCH, SGT), based on which a shielding electrode 310 is further formed in the gate trench 110 before the gate electrode 320 is formed, and the gate electrode 320 is isolated and disposed above the shielding electrode 310.
Referring with emphasis to fig. 3, after forming the gate trench 110 and before forming the shielding electrode 310, an insulating dielectric layer 210 is formed in the gate trench 110, and the insulating dielectric layer 210 covers the sidewalls and the bottom wall of the gate trench 110. The insulating dielectric layer 210 may be formed by a thermal oxidation process, for example, and the material of the insulating dielectric layer 210 includes silicon oxide (SiO), for example. And, after the insulating dielectric layer 210 is formed, that is, the shielding electrode 310 is filled in the gate trench 110, the shielding electrode 310 is correspondingly formed on the insulating dielectric layer 210. In this embodiment, after the shielding electrode 310 is formed, an isolation layer is further formed on the shielding electrode 310 for isolating the shielding electrode 310 from a gate electrode 320 formed later.
Further, a gate oxide layer 220 is formed, the gate oxide layer 220 covering the sidewalls of the gate trench and also covering the top surface of the substrate 100. Wherein the thickness of the gate oxide layer 220 is set to be greater than 500 angstroms, for example, 500-800 angstroms, and the material of the gate oxide layer 220 includes silicon oxide.
Next, as shown in fig. 4, a gate electrode 320 is formed. In one example, the method of forming the gate electrode 320 includes, for example, first, depositing a layer of electrode material that fills the gate trench 110 and covers the top surface of the substrate 100, the material of the layer of electrode material may include polysilicon, and then, performing an etch-back process to remove the electrode material on the top surface of the substrate such that the remaining electrode material remains within the gate trench 110 to form the gate electrode 320. The gate electrode 320 may be an N-doped gate electrode, or a P-doped gate electrode. Alternatively, the doped gate electrode 320 may be formed by in-situ doping, or an ion implantation process may be performed after the formation of the gate electrode to form the doped gate electrode 320.
In step S200, referring specifically to fig. 5-6, the gate oxide layer 220 on the top surface of the substrate is etched back to expose the top corners of the gate trench 110 and the top corners of the gate trench are etched to form a transition section.
Specifically, the top corners of the gate trench 110 have a sharp corner structure, so that during the process of etching the gate oxide layer 220 on the top surface of the substrate, the etching rate for the top corner of the gate trench 110 will be higher than the etching rate for the gate oxide layer on the top surface of the substrate, so that when the top corners of the gate trench 110 are exposed, a portion of the gate oxide layer 220 remains on the top surface of the substrate.
With continued reference to fig. 6, the exposed top corners of the gate trench 110 are etched to form a gentle transition, so that the sharp corner structure of the top corners of the gate trench can be relieved. In a specific scheme, an isotropic etching process may be performed on the exposed top corners of the gate trench 110 to remove the top corners, and further the top corners of the gate trench 110 may be formed as an undercut structure. That is, after the top corners of the gate trench 110 are etched, the surface at the etched top corner position is made to appear as a concave cambered surface to constitute a gentle transition section.
It should be noted that, when the top corner of the gate trench 110 is etched, since the top surface of the substrate is still covered with a portion of the gate oxide layer 220, the top surface of the substrate 100 is not entirely consumed when the top corner of the gate trench 110 is etched, and the protruding sharp corner portion of the trench can be precisely removed.
In step S300, with specific reference to fig. 7, an oxide layer is formed at least on the transition section. In this embodiment, the oxide layer 400 may be formed in a first thermal annealing process that may be used to repair crystal damage in the gate electrode 320 and activate doping ions in the gate electrode 320. That is, in the course of performing the first thermal annealing process, the transition sections of the top corners of the gate trench 110 may be simultaneously oxidized to form an oxide layer.
In a specific scheme, the first thermal annealing process may be performed in an oxygen atmosphere, so that the top corners of the gate trench 110 may be oxidized at the same time, for example, oxygen may be introduced into the annealing furnace to perform the thermal annealing process. Further, through the first thermal annealing process, the top surface of the substrate is oxidized to form an oxide layer, and as shown in fig. 7, an oxide layer 400 may be formed on the top surface of the substrate and the top corners of the trench through the first thermal annealing process.
In this embodiment, the thickness of the oxide layer 400 on the top surface of the substrate is thickened to at least 800 a by the first thermal annealing process, for example, the thickness of the oxide layer 400 is 800 a-1200 a.
In this embodiment, the oxide layer 400 is formed on both the top surface of the substrate and the top corner of the trench by the first thermal annealing process, so that the thickness of the oxide layer 400 on the top surface of the substrate is larger. For this, the method further includes, before performing the ion implantation process, thinning the thickness of the oxide layer 400 to facilitate the subsequent ion implantation process. Referring specifically to fig. 8, in this embodiment, the thickness of the oxide layer 400 may be thinned to be less than 400 a by an etching back process, for example, the thickness of the oxide layer 400 may be thinned to be 300 a-200 a.
It should be noted that, in the process of etching the oxide layer 400 to thin the thickness of the oxide layer 400, since the top angle of the gate trench 110 is a gentle transition section and no sharp angle structure exists, the etching rate at the top angle position of the trench can be reduced, so that the oxide layer on the top surface of the substrate and the top angle position of the trench can be uniformly consumed, and the oxide layer at the top angle position of the trench is prevented from being completely removed and exposed.
In step S400, referring specifically to fig. 9, an ion implantation process is performed to form a well region 500 in the substrate at the side of the gate trench. The ion doping type of the well region 500 is opposite to the ion doping type of the gate electrode 320, for example, the gate electrode 320 is N-doped, and the well region 500 is P-doped.
Further, after the ion implantation process is performed, a second thermal annealing process is also used to repair crystal damage in the ion doped region and activate the dopant ions. It should be noted that, in the second thermal annealing process, the gate electrode 320 and the well region 500 are isolated from each other by an oxide layer, and the top corner position of the gate trench 110 is still covered with the oxide layer 400, so that the problem of ion interdiffusion between the gate electrode 320 and the well region 500 in the second thermal annealing process is effectively avoided.
In summary, in the method for manufacturing the trench gate field effect transistor provided in this embodiment, the top corner of the gate trench is exposed by etching the gate oxide layer on the top surface of the substrate, and the top corner of the gate trench is further etched to form a gentle transition section, for example, the top corner position of the gate trench is changed from a convex sharp corner structure to a concave arc structure. And when the first thermal annealing process is used for carrying out crystal repair and ion activation on the gate electrode, the top angle of the gate trench can be oxidized to form an oxide layer, and the oxide layer at the top angle position of the trench is not easy to be rapidly consumed and can be reserved because the top angle of the gate trench is smoother, so that the problem of ion diffusion between the gate electrode and the well region through the top angle of the trench can be avoided.
Further, in the process of etching the gate oxide layer on the top surface of the substrate to expose the top angle of the gate trench, the difference of etching rates of the top surface of the substrate and the top angle position of the trench can be specifically utilized, so that under the condition that the top angle of the gate trench is exposed, a part of the gate oxide layer remains on the top surface of the substrate, and the top angle of the gate trench can be better rounded under the coverage of the gate oxide layer.
It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary.
Claims (11)
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| CN202210350829.9A CN114758954B (en) | 2022-04-02 | 2022-04-02 | Method for preparing trench gate field effect transistor |
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| CN202210350829.9A CN114758954B (en) | 2022-04-02 | 2022-04-02 | Method for preparing trench gate field effect transistor |
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| CN114758954A CN114758954A (en) | 2022-07-15 |
| CN114758954B true CN114758954B (en) | 2026-02-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench power MOSFET with planarized gate bus |
| CN104576340A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming top fillets of deep trenches |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100518054B1 (en) * | 2003-06-26 | 2005-09-28 | 주식회사 케이이씨 | Transistor and its manufacturing method |
| US8785278B2 (en) * | 2012-02-02 | 2014-07-22 | Alpha And Omega Semiconductor Incorporated | Nano MOSFET with trench bottom oxide shielded and third dimensional P-body contact |
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- 2022-04-02 CN CN202210350829.9A patent/CN114758954B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1757117A (en) * | 2003-03-05 | 2006-04-05 | 先进模拟科技公司 | Trench power MOSFET with planarized gate bus |
| CN104576340A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming top fillets of deep trenches |
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| CN114758954A (en) | 2022-07-15 |
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