CN114756496B - Data reading method and system of EEPROM chip, air conditioner and storage medium - Google Patents
Data reading method and system of EEPROM chip, air conditioner and storage medium Download PDFInfo
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- CN114756496B CN114756496B CN202210238205.8A CN202210238205A CN114756496B CN 114756496 B CN114756496 B CN 114756496B CN 202210238205 A CN202210238205 A CN 202210238205A CN 114756496 B CN114756496 B CN 114756496B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F24—HEATING; RANGES; VENTILATING
- F24F—AIR-CONDITIONING; AIR-HUMIDIFICATION; VENTILATION; USE OF AIR CURRENTS FOR SCREENING
- F24F11/00—Control or safety arrangements
- F24F11/88—Electrical aspects, e.g. circuits
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application provides a data reading method and system of an EEPROM chip, an air conditioner and a storage medium, wherein the method comprises the following steps: controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data; judging whether the first data is correct or not; and if the data is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate. By the method, the reading accuracy of the data of the EEPROM chip can be improved.
Description
Technical Field
The application relates to the technical field of IIC (Inter-INTEGRATED CIRCUIT, interconnection integrated circuit) communication, in particular to a data reading method and system of an EEPROM chip, an air conditioner and a storage medium.
Background
EEPROM (ElectricallyErasableProgrammable read only memory) chips are used in a variety of fields, such as the field of electronic products, e.g., air conditioning, automobiles, and other fields, e.g., storage, transportation, etc. At present, most variable frequency air conditioners are provided with EEPROM chips, and the EEPROM chips (called as E side for short) store operation parameter data of an air conditioner controller.
The EEPROM chip is generally electrically connected with an IIC main device (such as MCU) by adopting an IIC bus, and the IIC main device establishes communication with the EEPROM chip through the IIC bus to read the data of the EEPROM chip, but the data of the EEPROM chip read by the IIC main device is wrong when the IIC bus communication is abnormal.
Disclosure of Invention
The embodiment of the application provides a data reading method and system of an EEPROM chip, an air conditioner and a storage medium, which can improve the reading accuracy of the data of the EEPROM chip.
The embodiment of the application provides a data reading method of an EEPROM chip, which comprises the following steps:
controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data;
Judging whether the first data is correct or not;
And if the data is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate.
Optionally, the step of determining whether the first data is correct includes:
Processing the first data to obtain a first check code;
comparing the first check code with a target check code stored in the EEPROM chip in advance;
if the first check code is the same as the target check code, judging that the first data is correct;
And if the first check code is different from the target check code, judging that the first data is wrong.
Optionally, if the error occurs, controlling the IIC bus to read the data of the EEPROM chip by using a second transmission rate to obtain second data, where after the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, the method includes:
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the ratio of the high level to the low level of the serial clock line in the IIC bus to be Tlow/huge=2, wherein Tlow represents the duration of the low level, and huge represents the duration of the high level;
And reading the data of the EEPROM chip through the set IIC bus to obtain third data.
Optionally, after reading the data of the EEPROM chip through the set IIC bus to obtain third data, the method further includes:
judging whether the third data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/align=16/9;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
Optionally, after reading the data of the EEPROM chip through the set IIC bus to obtain fourth data, the method includes:
judging whether the fourth data is correct or not;
And if the fourth data is wrong, determining that the IIC bus communication is faulty.
Optionally, if the error occurs, reading the data of the EEPROM chip by using a second transmission rate through the IIC bus to obtain second data, where after the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, the method includes:
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/align=2;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
Optionally, if the error occurs, controlling the IIC bus to read the data of the EEPROM chip by using a second transmission rate to obtain second data, where after the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, the method includes:
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/align=16/9;
reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
judging whether the fourth data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be Tlow/align=2;
And reading the data of the EEPROM chip through the set IIC bus to obtain third data.
Optionally, the transmission rate of the first transmission rate is equal to or less than 100Kbit/s, and the transmission rate of the second transmission rate is equal to or greater than 3.4Mbit/s.
The embodiment of the application provides a data reading system of an EEPROM chip, which comprises:
an IIC bus including a serial clock line and a serial data line;
The IIC main equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line;
the EEPROM chip comprises a second serial clock interface and a second serial data interface, wherein the second serial clock interface is connected with the other end of the serial clock wire, and the second serial data interface is connected with one end of the serial data wire;
And the IIC main equipment reads the data of the EEPROM chip according to the data reading method of the EEPROM chip.
The embodiment of the application provides an air conditioner, which comprises a data reading system of an EEPROM chip.
An embodiment of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data reading method of an EEPROM chip as described in any one of the above.
When the data reading of the EEPROM chip is abnormal, the data reading of the EEPROM chip is carried out again in a mode of switching the transmission rate of the IIC bus, and the accuracy of the data reading of the EEPROM chip is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the application and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a first method for reading data from an EEPROM chip according to an embodiment of the present application.
Fig. 2 is a data reading system of an EEPROM chip according to an embodiment of the present application.
Fig. 3 is a flowchart illustrating a data reading method of an EEPROM chip according to an embodiment of the present application.
Fig. 4 is a third flowchart of a data reading method of an EEPROM chip according to an embodiment of the present application.
Fig. 5 is a fourth flowchart of a data reading method of an EEPROM chip according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In general, an outdoor unit control unit of an air conditioner generally adopts a mode of combining an IIC main device and an EEPROM chip, wherein a general control code is stored in the IIC main device, and differentiated control parameters are stored in the EEPROM chip, so as to realize compatibility of a main control logic to various system models. However, in the practical application process, the IIC bus has a long circuit in the circuit board layout, which may cause waveform distortion of transmission, such as long time of front and back edges, and error of the read data, thereby causing data reading failure of the EEPROM chip, and causing that the air conditioner cannot operate normally.
Based on this, an embodiment of the present application provides a data reading method of an EEPROM chip, as shown in fig. 1, fig. 1 is a first flowchart of the data reading method of the EEPROM chip provided in the embodiment of the present application. The method comprises the following steps:
110, controlling the IIC bus to read the data of the EEPROM chip by adopting the first transmission rate so as to obtain first data.
The execution main body of the embodiment of the application can be IIC main equipment, the IIC main equipment is a micro control unit (MicrocontrollerUnit, MCU) with an IIC communication function, and the IIC main equipment and the EEPROM chip can be in communication connection by adopting an IIC bus. The IIC host device may have an IIC communication interface, such as shown in fig. 2, fig. 2 is a data reading system of an EEPROM chip provided in an embodiment of the present application, and the data reading system 20 includes an IIC bus, an IIC host device, and an EEPROM chip. The IIC main device and the EEPROM chip are connected with each other through an IIC bus. For example, the IIC master device may include a first serial clock interface and a first serial data interface. The IIC bus may include a serial clock line (System Clock Line, SCL) having one end connected to the first serial clock interface and a serial data line (SERIALDATAADDRESS, SDA) having one end connected to the first serial data interface. The EEPROM chip comprises a second serial clock interface and a second serial data interface, wherein the second serial clock interface is connected with the other end of the serial clock wire, and the second serial data interface is connected with the other end of the serial data wire. The IIC master may communicate data with the EEPROM chip through the SDA (SERIAL DATA ADDRESS, serial data line) of the IIC bus based on a clock signal generated by the SCL (Serial ClockLine ) of the IIC bus.
The IIC master device can control the IIC bus to read the data of the EEPROM chip by adopting the first transmission rate so as to obtain first data.
120, Determining whether the first data is correct.
After the IIC main equipment reads the first data from the EEPROM chip, judging the first data to see whether the first data read by the IIC main equipment is correct or not. Wherein, the judgment can be carried out by adopting the following method:
Processing the first data to obtain a first check code;
comparing the first check code with a target check code stored in the EEPROM chip in advance;
if the first check code is the same as the target check code, judging that the first data is correct;
And if the first check code is different from the target check code, judging that the first data is wrong.
The IIC master device may process the first data according to a preset rule to obtain a first check code, where the preset rule may be a preset rule, for example, perform addition operation, or multiplication operation on parameters of the first data. The EEPROM chip can calculate the stored data in advance according to a preset rule to obtain a target check code, and the target check code can check the data read by the IIC main equipment. After the IIC master device calculates the first check code, the first check code is compared with the target check code, whether the first check code is identical to the target check code or not is determined, if the first check code is identical to the target check code, the first data is determined to be correct, and if the first check code is not identical to the target check code, the first data is determined to be incorrect.
130, If the error occurs, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain second data, where the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate.
When the first data error is judged, the IIC main equipment can control the IIC bus to switch the transmission mode, and the data of the EEPROM chip is read by adopting a second transmission rate so as to obtain the second data, wherein the second transmission rate is larger than the first transmission rate.
Illustratively, the first transmission rate may be 100Kbit/s and the second transmission rate may be 3.4Mbit/s, and the data of the EEPROM chip is re-read to obtain the second data. If the read second data is normal, the air conditioner may be operated normally. The first transmission rate is not limited to 100Kbit/s, but may be other rates lower than 100 Kbit/s. The second transmission rate is not limited to 3.4Mbit/s, but may be other rates higher than 3.4 Mbit/s.
It can be understood that when the data reading of the EEPROM chip is abnormal, the embodiment of the application adopts a mode of switching the transmission rate of the IIC bus to read the data of the EEPROM chip again, thereby improving the accuracy of reading the data of the EEPROM chip.
Fig. 3 is a flow chart of a data reading method of an EEPROM chip according to an embodiment of the present application. When the IIC bus still cannot correctly read the data of the EEPROM chip after adopting the second transmission rate, the following steps can be executed:
140, determining whether the second data is correct.
In the embodiment of the present application, the judgment manner of the second data is the same as that of the embodiment of the application. For example, the IIC master device may process the second data according to a preset rule to obtain the second check code, where the preset rule may be a preset rule, for example, perform an addition operation, or a multiplication operation on a parameter of the second data, etc. After the IIC main equipment calculates the second check code, comparing the second check code with the target check code of the EEPROM chip, determining whether the second check code is identical to the target check code, if so, judging that the second data is correct, and if not, judging that the second data is wrong.
150, If the error occurs, the transmission rate of the IIC bus is set to be greater than 100Kbit/s and less than or equal to 400Kbit/s, and the ratio of the high level to the low level of the serial clock line in the IIC bus is set to be T low/Thigh＝2,Tlow to represent the duration of the low level, and T high to represent the duration of the high level.
When the second data error is judged, the IIC master can change the transmission rate of the IIC bus and the ratio of the high level to the low level of the serial clock line in the IIC bus. By way of example, it is possible to set the transmission rate of the IIC bus to one of more than 100Kbit/s and less than or equal to 400Kbit/s, such as setting the transmission rate of the IIC bus to 400Kbit/s, and setting the high-low level ratio of the serial clock line in the IIC bus to T low/Thigh＝2,Tlow indicates the duration of the low level, and T high indicates the duration of the high level. When the serial clock line is at a high level, the IIC main device performs data acquisition based on the serial data line, and when the serial clock line is at a low level, the serial data line prepares the next data to be acquired, and at the moment, the IIC main device pauses data acquisition, so that the data acquisition interval of the IIC main device on the EEPROM chip can be modified by modifying the ratio of the high level to the low level of the serial clock line.
It can be appreciated that when the waveform transmitted by the IIC bus is distorted, the data reading error may occur when the data of the EEPROM chip is still read by using the originally set transmission rate and IIC communication interval. When the correct data still cannot be read after the second transmission rate is switched to read the data of the EEPROM chip, the transmission rate of the IIC bus and the duty ratio of the high level and the low level are changed to read the data of the EEPROM chip again.
160, Reading the data of the EEPROM chip through the set IIC bus to obtain third data.
And after the IIC bus is set, the IIC main equipment establishes communication with the EEPROM chip through the set IIC bus, and reads the data of the EEPROM chip to obtain third data. The IIC main equipment and the EEPROM chip establish communication through a serial clock line of an IIC bus. The EEPROM chip stores the optimal operation parameters of the air conditioner, and the air conditioner unit can be ensured to operate in an optimal state according to the optimal operation parameters. When the data of the EEPROM chip is successfully read, the operation of the air conditioning unit is directly controlled based on the read data, so that the IIC main equipment can finish the reading of the data of the EEPROM chip at the fastest speed under the normal state, and the operation can be started as soon as possible.
Fig. 4 is a schematic diagram of a third flow chart of a data reading method of an EEPROM chip according to an embodiment of the present application. Wherein, the step of reading the data of the EEPROM chip through the set IIC bus to obtain the third data "further includes:
170, determining whether the third data is correct.
In the embodiment of the present application, the judgment manner of the third data is the same as that of the embodiment of the application. For example, the IIC master device may process the third data according to a preset rule to obtain the third check code, where the preset rule may be a preset rule, for example, perform an addition operation, or a multiplication operation on a parameter of the third data, etc. After the IIC main equipment calculates the third check code, comparing the third check code with the target check code of the EEPROM chip, determining whether the third check code and the target check code are identical, if so, judging that the third data is correct, and if not, judging that the third data is wrong.
180, If the error occurs, the transmission rate of the IIC bus is set to be greater than 100Kbit/s and less than or equal to 400Kbit/s, and the high-low level ratio of the serial clock line is set to be T low/Thigh＝16/9,Tlow to indicate the duration of the low level, and T high to indicate the duration of the high level.
When the third data error is judged, the IIC master can change the transmission rate of the IIC bus and the ratio of the high level to the low level of the serial clock line in the IIC bus. By way of example, it is possible to set the transmission rate of the IIC bus to one of more than 100Kbit/s and less than or equal to 400Kbit/s, such as setting the transmission rate of the IIC bus to 400Kbit/s, and setting the high-low level ratio of the serial clock line in the IIC bus to T low/Thigh＝16/9,Tlow indicates the duration of the low level, and T high indicates the duration of the high level. When the serial clock line is at a high level, the IIC main device performs data acquisition based on the serial data line, and when the serial clock line is at a low level, the serial data line prepares the next data to be acquired, and at the moment, the IIC main device pauses data acquisition, so that the data acquisition interval of the IIC main device on the EEPROM chip can be modified by modifying the ratio of the high level to the low level of the serial clock line.
It can be appreciated that when the waveform transmitted by the IIC bus is distorted, the data reading error may occur when the data of the EEPROM chip is still read by using the originally set transmission rate and IIC communication interval. When correct data can not be read after the data of the EEPROM chip is read by modifying the transmission rate and the duty ratio of the high level and the low level, the data of the EEPROM chip is read again by changing the duty ratio of the high level and the low level.
And 190, reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
After the IIC bus is set, the IIC main equipment establishes communication with the EEPROM chip through the set IIC bus, and reads the data of the EEPROM chip to obtain fourth data.
Wherein, the step of "190" further includes, after reading the data of the EEPROM chip through the set IIC bus to obtain fourth data ":
judging whether the fourth data is correct or not;
And if the fourth data is wrong, determining that the IIC bus communication is faulty.
In the embodiment of the present application, the judgment manner of the fourth data is the same as that of the embodiment of the above application. For example, the IIC master device may process the fourth data according to a preset rule to obtain the third check code, where the preset rule may be a preset rule, for example, perform an addition operation, or a multiplication operation on a parameter of the fourth data, etc. After the IIC master device calculates the fourth check code, the fourth check code is compared with the target check code of the EEPROM chip, whether the fourth check code is identical with the target check code or not is determined, if the fourth check code is identical with the target check code, the fourth data is judged to be correct, and if the fourth check code is not identical with the target check code, the fourth data is judged to be incorrect. If the fourth data is correct, the transmission parameters of the IIC bus are modified to enable the communication of the IIC bus to be recovered to be normal, so that the data reading of the EEPROM chip is correct. If the fourth data is wrong, it indicates that the IIC communication cannot be recovered to be normal by modifying the transmission rate of the IIC bus and the duty ratio of the high level and the low level, and then the IIC bus communication fault can be determined.
It can be understood that the reason for the IIC bus communication fault may be due to waveform transmission distortion, and if the waveform transmission can be made normal by modifying the transmission rate and the duty ratio of the high level and the low level of the IIC bus, the problem of the IIC bus communication fault caused by the waveform transmission distortion can be solved.
It should be noted that, in the above-mentioned application embodiment, the third data acquisition process and the fourth data acquisition process may be exchanged. Fig. 5 is a schematic diagram of a fourth flow chart of a data reading method of an EEPROM chip according to an embodiment of the present application. At 130, if the error occurs, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain second data, where after the transmission rate of the second transmission rate is greater than the transmission rate of the first transmission rate, the method may include:
240, judging whether the second data is correct;
250, if the error occurs, setting the transmission rate of the IIC bus to be greater than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh＝16/9,Tlow to represent the duration of the low level and T high to represent the duration of the high level;
260, reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
270, determining whether the fourth data is correct;
280, if the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh＝2,Tlow to represent the duration of the low level and T high to represent the duration of the high level;
and 290, reading the data of the EEPROM chip through the set IIC bus to obtain third data.
The specific description of the above steps may be referred to the related description of the embodiments of the application, which is not repeated herein.
It can be understood that when the IIC master device uses the parameters set by the IIC bus to read data errors, another set parameter can be switched to until the reading is successful, and the data reading mode at that time is recorded as the default mode for reading data by the EEPROM chip next time.
With continued reference to fig. 2, an embodiment of the present application provides a data reading system for an EEPROM chip, which includes an IIC bus, an IIC main device, and an EEPROM chip. The IIC bus comprises a serial clock line and a serial data line; the IIC master device comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line; the EEPROM chip comprises a second serial clock interface and a second serial data interface, wherein the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line. And the IIC main equipment reads the data of the EEPROM chip according to the data reading method of the EEPROM chip. Such as: controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data; judging whether the first data is correct or not; and if the data is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate.
The EEPROM chip may further include a resistor R, a power supply interface VCC, a write protection interface WP, a device address output interface A0, a device address output interface A1, a device address output interface A2, and a power supply ground interface GND. One end of the resistor R is connected with the power interface VCC, the other end of the resistor R is connected with the write-protection interface WP, and one end of the resistor R connected with the power interface VCC is also connected with the power interface VCC. The device address output interface A0, the device address output interface A1, the device address output interface A2 and the power ground interface GND are connected to each other and then grounded.
The embodiment of the application also provides an air conditioner which comprises the data reading system of the EEPROM chip. Such as: the system comprises an IIC bus, an IIC main device and an EEPROM chip. The IIC bus comprises a serial clock line and a serial data line; the IIC master device comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line; the EEPROM chip comprises a second serial clock interface and a second serial data interface, wherein the second serial clock interface is connected with the other end of the serial clock line, and the second serial data interface is connected with one end of the serial data line; the IIC main device reads the data of the EEPROM chip according to the data reading method of the EEPROM chip of any of the application embodiments. Such as: controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data; judging whether the first data is correct or not; and if the data is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the data reading method of any one of the EEPROM chips. Such as: controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data; judging whether the first data is correct or not; and if the data is wrong, controlling the IIC bus to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate.
In an embodiment of the present application, the storage medium may be a magnetic disk, an optical disk, a Read Only Memory (ROM), or a random access Memory (Random Access Memory, RAM), etc.
The data reading method, the system, the air conditioner and the storage medium of the EEPROM chip provided by the embodiment of the application are described in detail. Specific examples are set forth herein to illustrate the principles and embodiments of the present application and are provided to aid in the understanding of the present application. Meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (11)
1. A data reading method of an EEPROM chip, comprising:
controlling the IIC bus to read the data of the EEPROM chip by adopting a first transmission rate so as to obtain first data;
Judging whether the first data is correct or not;
If the data is wrong, the IIC bus is controlled to read the data of the EEPROM chip by adopting a second transmission rate so as to obtain second data, wherein the second transmission rate is larger than the first transmission rate;
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the ratio of the high level to the low level of the serial clock line in the IIC bus;
and reading the data of the EEPROM chip through the set IIC bus.
2. The method of claim 1, wherein the step of determining whether the first data is correct comprises:
Processing the first data to obtain a first check code;
comparing the first check code with a target check code stored in the EEPROM chip in advance;
if the first check code is the same as the target check code, judging that the first data is correct;
And if the first check code is different from the target check code, judging that the first data is wrong.
3. The method for reading data of an EEPROM chip according to claim 1 or 2, wherein if the error occurs, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain second data, the second transmission rate being greater than the first transmission rate, and then comprising:
Judging whether the second data is correct or not;
if the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line in the IIC bus to be T low/Thigh=2,Tlow to represent the duration of low level and T high to represent the duration of high level;
And reading the data of the EEPROM chip through the set IIC bus to obtain third data.
4. The method for reading data of an EEPROM chip according to claim 3, further comprising, after reading the data of the EEPROM chip via the set IIC bus to obtain third data:
judging whether the third data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh=16/9,Tlow to represent the duration of low level and T high to represent the duration of high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
5. The method of reading data from an EEPROM chip of claim 4, wherein reading data from the EEPROM chip via the set IIC bus to obtain fourth data comprises:
judging whether the fourth data is correct or not;
And if the fourth data is wrong, determining that the IIC bus communication is faulty.
6. The method for reading data of an EEPROM chip according to claim 1 or 2, wherein if the data is erroneous, reading the data of the EEPROM chip by the IIC bus at a second transmission rate to obtain second data, the second transmission rate being greater than the first transmission rate, and then comprising:
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh=2,Tlow to represent the duration of low level and T high to represent the duration of high level;
and reading the data of the EEPROM chip through the set IIC bus to obtain fourth data.
7. The method for reading data of an EEPROM chip according to claim 1 or 2, wherein if the error occurs, controlling the IIC bus to read the data of the EEPROM chip at a second transmission rate to obtain second data, the second transmission rate being greater than the first transmission rate, and then comprising:
Judging whether the second data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh=16/9,Tlow to represent the duration of low level and T high to represent the duration of high level;
reading the data of the EEPROM chip through the set IIC bus to obtain fourth data;
judging whether the fourth data is correct or not;
If the error occurs, setting the transmission rate of the IIC bus to be more than 100Kbit/s and less than or equal to 400Kbit/s, and setting the high-low level ratio of the serial clock line to be T low/Thigh=2,Tlow to represent the duration of low level and T high to represent the duration of high level;
And reading the data of the EEPROM chip through the set IIC bus to obtain third data.
8. The method for reading data of an EEPROM chip according to claim 1, wherein the first transmission rate is equal to or less than 100Kbit/s and the second transmission rate is equal to or more than 3.4Mbit/s.
9. A data reading system of an EEPROM chip, comprising:
an IIC bus including a serial clock line and a serial data line;
The IIC main equipment comprises a first serial clock interface and a first serial data interface, wherein the first serial clock interface is connected with one end of the serial clock line, and the first serial data interface is connected with one end of the serial data line;
the EEPROM chip comprises a second serial clock interface and a second serial data interface, wherein the second serial clock interface is connected with the other end of the serial clock wire, and the second serial data interface is connected with one end of the serial data wire;
The IIC master reads data of the EEPROM chip according to the data reading method of the EEPROM chip of any one of claims 1 to 8.
10. An air conditioner comprising the data reading system of the EEPROM chip of claim 9.
11. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements a data reading method of the EEPROM chip as claimed in any one of claims 1 to 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109358981A (en) * | 2018-09-25 | 2019-02-19 | 珠海市杰理科技股份有限公司 | Memory read error correction method, system, computer device and storage medium |
| CN111578489A (en) * | 2020-05-12 | 2020-08-25 | 珠海拓芯科技有限公司 | EEPROM chip data reading method, control system, air conditioner and storage medium |
| CN113849355A (en) * | 2021-08-30 | 2021-12-28 | 苏州浪潮智能科技有限公司 | I2C rate self-adaptive adjusting method, system, terminal and storage medium |
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| US6675272B2 (en) * | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109358981A (en) * | 2018-09-25 | 2019-02-19 | 珠海市杰理科技股份有限公司 | Memory read error correction method, system, computer device and storage medium |
| CN111578489A (en) * | 2020-05-12 | 2020-08-25 | 珠海拓芯科技有限公司 | EEPROM chip data reading method, control system, air conditioner and storage medium |
| CN113849355A (en) * | 2021-08-30 | 2021-12-28 | 苏州浪潮智能科技有限公司 | I2C rate self-adaptive adjusting method, system, terminal and storage medium |
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