CN114743976A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The manufacturing method comprises the following steps: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form a gate stack; removing portions of the oxide layer over the first and second regions of the substrate; forming a first selective gate oxide structure and a second selective gate oxide structure on a first region and a second region of a substrate, respectively, and forming a tunneling oxide structure on both sides of a gate stack, respectively; forming a selection grid on one side of the tunneling oxide structure opposite to the grid stacked body; etching the gate stack to form a first opening; forming a source region in a portion of the substrate located below the first opening; and forming a drain region in the substrate on a side of the select gate opposite the first opening.

Description

Semiconductor device and method of manufacturing the same

technical field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

In electronic devices, data is read and stored by means of a memory. Therefore, as the demand for electronic devices continues to grow, so does the demand for memory technology.

Flash memory is an electrically erasable and reprogrammable electrical non-volatile computer storage medium that retains on-chip information even after power is turned off. Flash memory is easy to use, not only has the flexibility of reading and writing, fast access speed, but also has the characteristics of not losing information after power failure. Therefore, flash memory technology has developed very rapidly.

Flash memory includes an addressable array of memory cells, where each memory cell includes a floating gate transistor for storing corresponding information. Accordingly, it is desirable to improve methods of manufacturing flash memory, especially memory cells in flash memory.

SUMMARY OF THE INVENTION

According to some embodiments of the present disclosure, there is provided a method of fabricating a semiconductor device, comprising: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate; etching a hard mask layer, a control gate layer, a dielectric layer, and a floating gate layer to form a gate stack consisting of the hard mask layer, the control gate layer, the dielectric layer, and the remainder of the floating gate layer; removing portions of the oxide layer on the first and second regions of the substrate, wherein the first and second regions flank the gate stack; on the first and second regions of the substrate forming a first select gate oxide structure and a second select gate oxide structure respectively, and forming a first tunnel oxide structure and a second tunnel oxide structure on both sides of the gate stack, respectively; forming a first select gate on the opposite side of the tunnel oxide structure from the gate stack, and forming a second select gate on the opposite side of the second tunnel oxide structure from the gate stack; etching a gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remainder of the floating gate layer; forming a source region in the portion of the substrate below the first opening ; and forming a first drain region in the substrate on the side of the first select gate opposite the first opening, and forming a first drain region in the substrate on the side of the second select gate opposite the first opening the second drain region.

According to some embodiments of the present disclosure, there is provided a semiconductor device fabricated by a method as described in the present disclosure.

These and other aspects of the present disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Description of drawings

Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

1 is a schematic flowchart of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

2A-2H are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

3A-3O are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

4A-4B are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

5 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

6 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

7 is a schematic cross-sectional structure diagram of a semiconductor device according to some embodiments of the present disclosure;

8 is a schematic circuit diagram of a memory cell array according to some embodiments of the present disclosure;

9A-9B are top plan views of memory cell arrays in accordance with some embodiments of the present disclosure.

Detailed ways

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms such as "below", "below", "lower", "below", "above", "above", etc. may be used herein for convenience Description is used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "under the other elements or features" above the characteristics". Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. Terms such as "before" or "before" and "after" or "followed by" may similarly be used, for example, to indicate the order in which light travels through elements. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprising" and/or "comprising" when used in this specification designate the presence of stated features, integers, steps, operations, elements and/or parts, but do not exclude one or more The presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof, of other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" means A only, B only, or both A and B.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to another element or layer" When present, it may be directly on, directly connected to, directly coupled to, or directly adjacent to another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," "directly adjacent to" another element or layer , with no intervening elements or layers present. However, in no case should "on" or "directly on" be interpreted as requiring a layer to completely cover the layer below.

Embodiments of the disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. As such, variations to the shapes of the illustrations are to be expected, eg, as a result of manufacturing techniques and/or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, but are to include deviations in shapes due, for example, to manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the relevant art and/or the context of this specification, and will not be idealized or overly interpreted in a formal sense, unless expressly defined as such herein.

As used herein, the term "substrate" may refer to the substrate of a diced wafer, or may refer to the substrate of an un-diced wafer. Similarly, the terms chip and die are used interchangeably, unless such interchange would create a conflict.

In the prior art, common types of flash memory cells include stacked gate memory cells and split gate memory cells. Compared with stacked gate memory cells, split gate memory cells have technical advantages such as lower power consumption and higher injection efficiency. For a flash memory having a split gate memory cell, the present disclosure provides a method of fabricating a semiconductor device, comprising: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask on a substrate layer; etching the hardmask layer, control gate layer, dielectric layer, and floating gate layer to form a gate consisting of the hardmask layer, control gate layer, dielectric layer, and the remainder of the floating gate layer stack; removing portions of the oxide layer on first and second regions of the substrate, wherein the first and second regions are on either side of the gate stack; on the first and second regions of the substrate A first selection gate oxide structure and a second selection gate oxide structure are respectively formed on the two regions, and a first tunneling oxide structure and a second tunneling oxide structure are respectively formed on both sides of the gate stack; A first select gate is formed on the opposite side of the first tunnel oxide structure from the gate stack, and a second select gate is formed on the opposite side of the second tunnel oxide structure from the gate stack electrode; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remainder of the floating gate layer; forming in the portion of the substrate below the first opening a source region; and forming a first drain region in the substrate on the side of the first select gate opposite the first opening, and forming a liner on the side of the second select gate opposite the first opening A second drain region is formed in the bottom.

FIG. 1 is a schematic flowchart of a method 100 of fabricating a semiconductor device according to some embodiments of the present disclosure.

At step S101, an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate.

According to some embodiments, the manufacturing method 100 further includes forming shallow trench isolations in the substrate in advance before forming the oxide layer on the substrate. According to some embodiments, the manufacturing method 100 further includes: pre-implanting memory cell wells in the substrate before forming the oxide layer on the substrate.

According to some embodiments, the process of forming shallow trench isolation may include, but is not limited to, the following steps: forming pad oxide, depositing silicon nitride, exposing active area, shallow insulating trench etching, shallow insulating trench filling, shallow insulating Trench planarization, and removal of silicon nitride.

According to some embodiments, step S101 includes: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a dielectric layer on the floating gate layer; forming a control gate layer on the dielectric layer ; Form a hard mask layer on the control gate layer.

According to some embodiments, an oxide layer is grown on the upper surface of the substrate; floating gate polysilicon is deposited on the upper surface of the oxide layer, and the floating gate polysilicon is planarized to form a floating gate layer; depositing a dielectric material (eg, ONO (oxygen-nitrogen-oxygen) material) on the top surface of the floating gate polysilicon to form a dielectric layer; depositing control gate polysilicon on the top surface of the dielectric layer to form a control gate layer; depositing a hard mask material (eg, silicon nitride material) on the control gate layer to form a hard mask layer.

FIG. 2A shows a cross-sectional view of an exemplary structure formed after step S101. As shown in FIG. 2A , the semiconductor structure 200 includes, from bottom to top, a substrate 210 , an oxide layer 220 , a floating gate layer 230 , a dielectric layer 240 , a control gate layer 250 and a hard mask layer 260 .

At step S102, the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer are etched to form the remainder of the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer the gate stack.

According to some embodiments, first, a photolithography process is performed on the upper surface of the hard mask layer to form a photoresist pattern; then, using the formed photoresist pattern as a mask, the hard mask layer and the control gate layer are etched and dielectric layer; then, continue to etch the floating gate layer.

According to some embodiments, after etching the hard mask layer, the control gate layer, and the dielectric layer, control gate spacers are formed on both sides of the hard mask layer, the control gate layer, and the remainder of the dielectric layer, eg, at A control gate oxide (eg, silicon oxide) is deposited on both sides of the hardmask layer, the control gate layer, and the remainder of the dielectric layer, and the deposited control gate oxide is etched to form control gate spacers .

FIG. 2B shows a cross-sectional view of an exemplary structure formed after steps S101 to S102. As shown in FIG. 2B , the semiconductor structure 200 includes, from bottom to top, a substrate 210 , an oxide layer 220 and a gate stack 270 , wherein the gate stack 270 includes a floating gate layer 230 , a dielectric layer from bottom to top layer 240 , control gate layer 250 and the remainder of hard mask layer 260 .

At step S103, portions of the oxide layer on the first and second regions of the substrate are removed, wherein the first and second regions are on either side of the gate stack.

According to some embodiments, through the steps of cleaning, photolithography, and etching, portions of the oxide layer on the first and second regions of the substrate are removed, and a substrate oxide structure on the gate stack is formed .

FIG. 2C shows a cross-sectional view of an exemplary structure formed after steps S101 to S103. As shown in FIG. 2C , the semiconductor structure 200 includes, from bottom to top, a substrate 210 , a substrate oxide structure 221 and a gate stack 270 , wherein the gate stack 270 includes a floating gate layer 230 from bottom to top. , the remainder of the dielectric layer 240 , the control gate layer 250 and the hard mask layer 260 .

At step S104, a first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, and a first select gate oxide structure is respectively formed on both sides of the gate stack. A tunneling oxide structure and a second tunneling oxide structure.

According to some embodiments, a first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, and the first select gate oxide structure is respectively formed on both sides of the gate stack. The tunneling oxide structure and the second tunneling oxide structure include: depositing a second gate oxide film on the first region and the second region of the substrate, and on the side surface and the upper surface of the gate stack to form a first gate oxide film. a select gate oxide structure and a second select gate oxide structure; and removing portions of the first gate oxide film and the second gate oxide film on the upper surface of the gate stack to form a first gate oxide film A tunneling oxide structure and a second tunneling oxide structure.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes before depositing a second gate oxide film on the first region and the second region of the substrate and on the side and upper surface of the gate stack : depositing a first gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack; and removing the first gate oxide film on the substrate the first region, the second region, portions on the top and side surfaces of the gate stack, and, and on the first and second regions of the substrate, and on the side and top surfaces of the gate stack The second gate oxide film includes depositing a second gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack. In an embodiment as described in this disclosure, a high voltage tube oxide of a different thickness than the select gate oxide structure is formed on the high voltage tube region by two oxide film depositions and removal of excess oxide during the two depositions structure, so that the corresponding high-voltage logic device (for example, a high-voltage device powered by 11V) is subsequently formed on the high-voltage tube region.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes before depositing a second gate oxide film on the first region and the second region of the substrate and on the side and upper surface of the gate stack : depositing a first gate oxide film on the first and second regions of the substrate and on the side and upper surfaces of the gate stack; and removing the first gate oxide film on the first region of the substrate and a second region, a portion on the upper surface of the gate stack, and a portion of the first gate oxide film on the side surface of the gate stack is removed. According to some embodiments, a portion of the first gate oxide film on the sidewalls of the gate stack is retained by etching (eg, dry etching and wet etching) the first gate oxide film. According to some embodiments, after etching the first gate oxide film, a high temperature rapid thermal treatment is performed to enhance the quality of the oxide on the sidewalls.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes before depositing a second gate oxide film on the first region and the second region of the substrate and on the side and upper surface of the gate stack : depositing a first gate oxide film on the first and second regions of the substrate and on the side and upper surfaces of the gate stack; removing the first gate oxide film on the first and second regions of the substrate second regions, portions on the upper surface and side surfaces of the gate stack; and forming sidewall oxide structures on the side surfaces of the gate stack. According to some embodiments, sidewall oxide structures are formed on the sides of the gate stack by means of polysilicon oxidation.

According to the embodiments described above, by depositing the second gate oxide film on the first and second regions of the substrate, and on the side and upper surfaces of the gate stack, on the sides of the gate stack Retaining or additionally forming the oxide structure can make the select gate oxide structure different from the tunnel oxide structure thickness, for example, thicker tunnel oxide structure is beneficial for floating gate data storage, thinner select gate oxide structure The structure is beneficial for improving memory device performance (eg, providing greater read current).

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes removing the first gate oxide film on the first region and the second region of the substrate and on the upper surface of the gate stack Before the portion of : performing select gate channel ion (eg, boron or BF2) implants in the first and second regions of the substrate.

According to some embodiments, performing selective gate channel ion implantation in the first region and the second region of the substrate includes performing selective gate channel lithography to form a photoresist pattern to protect the ion implantation without performing the ion implantation. region; using the formed photoresist pattern as a mask, select gate channel ion implantation is performed.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes depositing a second gate on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surface of the gate stack After the oxide film: a logic well implant in the substrate; forming a logic IO gate oxide structure on the substrate; and forming a logic core gate oxide structure on the substrate.

FIG. 2D shows a cross-sectional view of an exemplary structure formed after steps S101 to S104. As shown in FIG. 2D , in addition to the substrate 210 , the substrate oxide structure 221 and the gate stack 270 , the semiconductor structure 200 further includes a first select gate oxide located on the first region on the left side of the gate stack 270 . material structure 222a, a first tunnel oxide structure 271a on the left side of the gate stack 270, a second select gate oxide structure 222b on the second region on the right side of the gate stack 270, and a gate The second tunnel oxide structure 271b on the right side of the stack 270 . It should be understood that while the first select gate oxide structure 222a and the first tunnel oxide structure 271a are shown as two separate parts, and the second select gate oxide structure 222b and the second tunnel oxide structure 271b is shown as two separate parts, however, the first select gate oxide structure 222a and the first tunnel oxide structure 271a may actually be continuous but different thicknesses of oxide, the second select gate oxide The oxide structure 222b and the second tunnel oxide structure 271b may actually be continuous oxides with different thicknesses, for example, formed by the above-mentioned two oxide film deposition steps.

At step S105, a first select gate is formed on a side of the first tunnel oxide structure opposite to the gate stack, and a side of the second tunnel oxide structure opposite to the gate stack is formed A second select gate is formed.

According to some embodiments, the first select gate is formed on the side of the first tunnel oxide structure opposite the gate stack, and the second tunnel oxide structure is formed on the side opposite the gate stack Forming the second select gate includes: depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack; and removing the deposited select gate polysilicon part to form the first select gate and the second select gate.

According to some embodiments, the deposited select gate polysilicon has the same coverage on the surfaces of the first select gate oxide structure and the second select gate oxide structure, and the gate stack, such that the deposited select gate polysilicon Very polysilicon exhibits a "convex" shape. For example, as described in detail below with reference to FIG. 3I.

According to some embodiments, removing the portion of the deposited select gate polysilicon to form the first select gate and the second select gate includes: planarizing the deposited select gate polysilicon; etching the planarized process select gate polysilicon to form a first polysilicon structure and a second polysilicon structure on the first and second regions of the substrate, respectively; and etching the first polysilicon structure and the second polysilicon structure to form a first select gate and a second select gate, respectively.

According to some embodiments, the deposited select gate polysilicon is subjected to a planarization process to remove select gate polysilicon deposited over the gate stack. According to some embodiments, during the planarization process of the deposited select gate polysilicon, oxide deposited over the gate stack in previous steps may also be removed.

According to some embodiments, etching the planarized select gate polysilicon to form first and second polysilicon structures on the first and second regions of the substrate, respectively, includes etching the gate shoulders of "L" shaped select gate poly on both sides of the stack to form rectangular first and second poly structures on first and second regions of the substrate, respectively structure so as to facilitate subsequent etching using photoresist or hard mask spacers as a mask to form the first select gate and the second select gate. For example, as described in detail below with reference to Figure 3J.

According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes: aligning the first polysilicon structure and the second polysilicon structure performing a first photolithography process; using the photoresist pattern formed by the first photolithography process as a mask, etching the first polysilicon structure and the second polysilicon structure to form the first selection gate and the second respectively selecting a gate; and removing the photoresist pattern formed by the first photolithography process. For example, as described in detail below with reference to Figures 3K-3L.

According to some embodiments, etching the first polysilicon structure and the second polysilicon structure to form the first select gate and the second select gate, respectively, includes forming a first hard mask on both sides of the gate stack, respectively. a mold spacer and a second hard mask spacer, wherein the first hard mask spacer is on the first polysilicon structure, and the second hard mask spacer is on the second polysilicon structure; and A hard mask spacer and a second hard mask spacer are used as masks to etch the first polysilicon structure and the second polysilicon structure to form a first select gate and a second select gate, respectively. For example, as described in detail below with reference to Figures 4A-4B.

According to some embodiments, removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate includes self-aligning etching the deposited select gate polysilicon to form the first select gates, respectively gate and second select gate. For example, as described in detail below with reference to FIG. 5 .

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes: depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack simultaneously depositing logic gate polysilicon on the logic gate region of the substrate; and removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate, removing portion of the logic gate polysilicon to form the logic gate.

According to further embodiments, depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack, is concurrently deposited on the logic gate region of the substrate logic gate polysilicon; and, in a different processing step than removing the portion of the deposited select gate polysilicon, removing the portion of the logic gate polysilicon to form the logic gate.

FIG. 2E shows a cross-sectional view of an exemplary structure formed after steps S101 to S105. As shown in FIG. 2E , the semiconductor structure 200 includes a substrate 210 , a substrate oxide structure 221 , a gate stack 270 , a first selection gate oxide structure 222 a , a first tunneling oxide structure 271 a , a second selection gate oxide structure 222 a The gate oxide structure 222b and the second tunnel oxide structure 271b further include a first select gate 280a on the opposite side of the first tunnel oxide structure 271a from the gate stack 270, and, on the first The opposite side of the two tunnel oxide structures 271b from the gate stack 270 forms a second select gate 280b.

At step S106, the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remainder of the floating gate layer.

According to some embodiments, etching the gate stack to form the first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remainder of the floating gate layer includes performing source lithography to form a lithography A glue pattern; using the formed photoresist pattern as a mask, the gate stack is etched to form a first opening.

FIG. 2F shows a cross-sectional view of an exemplary structure formed after steps S101 to S106. As shown in FIG. 2F, compared to FIG. 2E, the first opening 272 penetrates the hard mask layer, the control gate layer, the dielectric layer, and the remainder of the floating gate layer, wherein the hard mask layer, the control gate layer , the rest of the dielectric layer and the floating gate layer comprise the gate structures belonging to the memory cells on both sides respectively, ie the left side consists of the first floating gate 230a, the first dielectric structure 240a, the first control gate The gate structure formed by the electrode 250a and the first hard mask 260a and the gate formed by the second floating gate 230b, the second dielectric structure 240b, the second control gate 250b and the second hard mask 260b on the right side polar structure.

At step S107, a source region is formed in a portion of the substrate below the first opening.

According to some embodiments, the source region is formed by source ion implantation (eg, arsenic and phosphorous), thereby forming a graded junction in the substrate, ie, in the source region, from the substrate oxide structure to the substrate In the direction of , the source ion doping concentration is gradually reduced to improve the pressure-bearing capability of the semiconductor device. In the embodiments described in the present disclosure, since the gate structures and oxide structures of the memory cells on both sides are formed first, and then the source region implantation is performed, the thermal deposition step for forming the gate structures and the oxide structures is avoided. and affect the performance of the source region.

FIG. 2G shows a cross-sectional view of an exemplary structure formed after steps S101 to S107. As shown in FIG. 2G , in contrast to FIG. 2F , the semiconductor device 200 includes a source region 212 in the substrate 210 below the first opening 272 .

At step S108, a first drain region is formed in the substrate on the side of the first select gate opposite to the first opening, and a substrate on the side of the second select gate opposite to the first opening is formed A second drain region is formed in the bottom.

According to some embodiments, the first drain region is formed in the substrate on the side of the first select gate opposite the first opening, and the substrate on the side of the second select gate opposite the first opening The forming of the second drain region in the bottom includes performing a lightening process in the substrate on the side of the first select gate opposite to the first opening and in the substrate on the side of the second select gate opposite the first opening doped drain implantation to form a first lightly doped drain region on one side of the first select gate and a second lightly doped drain region on one side of the second select gate; A first drain spacer is formed on a side of the gate opposite to the first opening, and a second drain spacer is formed on a side of the second select gate opposite to the first opening; on the first select gate A first source spacer is formed on the side of the second select gate facing the first opening, and a second source spacer is formed on the side of the second select gate facing the first opening; and the first drain spacer is formed A heavily doped drain implant is performed in the substrate on the side opposite the first opening and in the substrate on the side opposite the first opening of the second drain spacer to form the first drain spacer A first heavily doped drain region on one side of the second drain spacer and a second heavily doped drain region on one side of the second drain spacer.

FIG. 2H shows a cross-sectional view of an exemplary structure formed after steps S101 to S108. As shown in FIG. 2H , compared to FIG. 2G , the semiconductor device 200 includes a first drain region 211 a formed in the substrate 210 on the side of the first select gate 280 a opposite to the first opening 272 and a second drain region 211 a A second drain region 211b formed in the substrate 210 on the side of the gate 280b opposite to the first opening 272 is selected.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further includes: forming silicide on the first select gate, the first drain region, the source region, the second select gate and the second drain region matter structure.

In the existing method of manufacturing a semiconductor device, an opening between two adjacent memory cells and a source region under the opening are first formed, and then a select gate located on one side of each memory cell is formed, which will When depositing the select gate material to form the select gate, excess select gate material is deposited in the opening between two adjacent memory cells. In the method for fabricating a semiconductor device according to the present disclosure, since the select gates on both sides of the gate stack are formed first, and then the opening through the gate stack and the source region under the opening are formed, there will be no Depositing excess select gate material in the openings as described above with reference to existing fabrication methods, thus reducing steps for removing excess select gate material, reducing production costs; and avoiding more trenches The conductive polysilicon is deposited in the area and the deposited polysilicon is removed by means of dry etching, for example, which reduces the process risk increased during the etching process and the probability of defects on the wafer surface after etching, and improves the chip yield.

In addition, in the existing manufacturing method of the semiconductor device, since the source region located under the opening between two adjacent memory cells is formed first, and then the deposition is performed to form the remaining structure of the memory cell, after the source region is formed The deposition process performed will affect the performance of the source region (eg, cause the source region to expand further), thereby making the process of forming the source region more demanding (ie, subject to subsequent multiple subsequent process steps (eg, deposition) maintains the desired properties after heat treatment). In the method for fabricating a semiconductor device according to the present disclosure, since each deposition process is performed before the source region is formed, the formed source region is prevented from being affected by the subsequent deposition process, thereby reducing the process for the source region Require.

3A-3O are schematic cross-sectional views of steps of a method of fabricating a semiconductor device 300 in accordance with some embodiments of the present disclosure.

According to some embodiments, as shown in FIG. 3A , and similar to that described with reference to FIG. 2A , the semiconductor structure 300 includes, from bottom to top, a substrate 210 , an oxide layer 220 , a floating gate layer 230 , a dielectric layer 240 , a control gate Pole layer 250 and hard mask layer 260 .

According to some embodiments, as shown in FIG. 3B , a photoresist is coated on the upper surface of the hard mask layer 260 , and a photolithography process is performed to form a photoresist pattern 290 , and the photoresist pattern 290 is used as a mask , the hard mask layer 260 , the control gate layer 250 and the dielectric layer 240 are etched.

According to some embodiments, as shown in FIG. 3C , the photoresist pattern shown in FIG. 3B is removed to form a first control on both sides of the hard mask layer 260 , the control gate layer 250 and the remaining portion of the dielectric layer 240 . The gate spacer 273a and the second control gate spacer 273b, eg, deposit a control gate oxide, and the deposited control gate oxide is etched to form the control gate spacer.

According to some embodiments, as shown in FIG. 3D , the floating gate layer 230 is etched to form a gate stack including the floating gate layer 230 , the dielectric layer 240 , the control gate layer 250 and the hard mask layer 260 .

According to some embodiments, as shown in FIG. 3E, first and second regions of the substrate 210 (ie, to be formed thereon) of the oxide layer are removed (eg, by cleaning, photolithography, etching, etc.) regions of the select gate), and portions of the high voltage transistor regions to form substrate oxide structures 221.

According to some embodiments, as shown in FIG. 3F , a first gate covering the semiconductor device 300 is formed on the first and second regions of the substrate 210 , and on the high voltage tube region and on the upper surface of the hard mask layer 280 . oxide film 291.

According to some embodiments, as shown in FIG. 3G, performing the selective gate channel ion implantation in the first region and the second region of the substrate 210 includes: performing selective gate channel lithography to form a photoresist pattern, Thereby protecting the area where ion implantation is not required; using the formed photoresist pattern as a mask, perform selective gate channel ion implantation; then, remove the first gate oxide film 291 located in the first area and the second area , and portions on the sidewalls and upper surface of the gate stack. It should be understood that, although not shown, the portion of the first gate oxide film 291 on the high voltage tube region of the substrate 210 is reserved for subsequent formation of an oxide structure corresponding to the high voltage tube region.

According to some embodiments, as shown in FIG. 3H , a second gate covering the semiconductor device 300 is formed on the first and second regions of the substrate 210 , and on the high voltage tube region and on the upper surface of the hard mask layer 280 . oxide film 292. According to some embodiments, although not shown in FIG. 3H, a logic well implant may be performed in substrate 210, a logic IO gate oxide structure may be formed on substrate 210, and a logic core gate may be formed on substrate 210 oxide structure.

According to some embodiments, as shown in FIG. 3I, a select gate suicide 280 is deposited on the second gate oxide film 292, wherein the select gate suicide 280 has substantially uniform coverage. According to some embodiments, logic gate polysilicon for subsequent formation of logic gates may be deposited along with select gate suicide 280 in FIG. 3I.

According to some embodiments, as shown in FIG. 3J, semiconductor structure 300 is planarized and poly-etched to remove portions of select gate suicide 280 to form first poly-structure 281a on the first region and The second polysilicon structure 281b on the second region, and the portions of the first gate oxide film 291 and the second gate oxide film 292 on the hard mask layer 260 are removed.

According to some embodiments, as shown in FIG. 3K, a photolithography process is performed on the first polysilicon structure 281a and the second polysilicon structure 281b; the photoresist pattern 293 formed by the photolithography process is used as a mask to etch the A polysilicon structure 281a and a second polysilicon structure 281b to form a first select gate 280a and a second select gate 280b, respectively. According to some embodiments, logic gates may be formed in conjunction with the steps shown in FIG. 3K.

According to some embodiments, as shown in FIG. 3L, photolithographic processing of the source region (eg, corresponding to the photoresist patterns 294a and 294b shown in FIG. 3L) and corresponding etching are performed to form the first opening 272 And, source ion implantation is performed in the portion of the substrate 210 under the first opening 272 to form the source region 212 . According to some embodiments, the source ion implantation may be an N-type ion implantation. According to other embodiments, in addition to N-type ion implantation, source ion implantation may also include appropriately increased P-type ion implantation to adjust the floating gate channel threshold voltage.

According to some embodiments, as shown in FIG. 3M, lightly doped drain (LDD) implant lithography (eg, corresponding to the photoresist pattern 295 shown in FIG. 3M) is performed, and in the first A lightly doped drain implant (eg , arsenic) to form a first lightly doped drain region 2111a on one side of the first select gate 280a and a second lightly doped drain region 2111b on one side of the second select gate 280b. According to some embodiments, after performing the lightly doped drain implant, related processes of forming the logic IO/core device may be performed. According to some embodiments, after performing the lightly doped drain implant, the photoresist pattern 295 may be removed.

According to some embodiments, as shown in FIG. 3N, first, a first drain spacer 273a is formed on a side of the first select gate 280a opposite to the first opening 272, and a first drain spacer 273a is formed on the side of the second select gate 280b opposite to the first opening 272. A second drain spacer 273b is formed on the side opposite to the first opening 272, a first source spacer 274a is formed on the side of the first select gate 280a facing the first opening 272, and a second select gate 274a is formed A second source spacer 274b is formed on the side of the electrode 280b facing the first opening 272; then, heavily doped drain implant photolithography is performed (for example, corresponding to the photoresist pattern 296 shown in FIG. 3N ), And in the substrate 210 on the side opposite to the first opening 272 of the first drain spacer 273a and in the substrate 210 on the side opposite to the first opening 272 of the second drain spacer 273b Doped drain implantation to form a first heavily doped drain region 2112a on one side of the first drain spacer 273a and a second heavily doped drain region on one side of the second drain spacer 273b 2112b. According to some embodiments, a baseline logic process may be performed after performing the heavily doped drain implant.

According to some embodiments, a suicide structure is formed on the first select gate, the first drain region, the source region, the second select gate and the second drain region. As shown in FIG. 30, a silicide structure is formed on the first select gate 280a, the first heavily doped drain region 2112a, the source region 223c, the second select gate 280b and the second heavily doped drain region 2112b 223a-223e. According to some embodiments, as shown in FIG. 3O, between the first source spacer 274a and the second source spacer 274b, and the first lightly doped drain region 2111a and the first heavily doped drain region are removed 2112a, the second lightly doped drain region 2111b, and the portion of the oxide layer 220 on the second heavily doped drain region 2112b, and a silicide structure is formed on the substrate 210 exposed by the removal of the oxide layer 220 223c.

According to some embodiments, in the semiconductor structure shown in FIG. 3O, since the gate stack is etched separately on the source side, asymmetric control gate spacers (ie, control gate spacers) may be formed only on one side of the control gate. , without the need to form a control gate spacer on the source side), increasing the coupling capacitance ratio of the control gate to the floating gate, thereby increasing the efficiency of electron injection during write operations, or reducing the control gate while maintaining the same efficiency Extreme voltage value to reduce the requirements for high-voltage tubes.

4A-4B are schematic cross-sectional views of the steps of a method of fabricating a semiconductor device 400 in accordance with some embodiments of the present disclosure.

According to some embodiments, after forming the first polysilicon structure 281a on the first region and the second polysilicon structure 281b on the second region as shown in FIG. 3J , as shown in FIG. 4A , in the semiconductor A first hard mask spacer 282a and a second hard mask spacer 282b are respectively formed on both sides of the device 200, wherein the first hard mask spacer 282a is located on the first polysilicon structure 281a, and the second hard mask spacer 282a is located on the first polysilicon structure 281a. Spacers 282b are located on the second polysilicon structures 281b, eg, by depositing a hardmask material, and etching the hardmask material to form first hardmask spacers 282a and second hardmask spacers 282b.

According to some embodiments, as shown in FIG. 4B, the first polysilicon structure 281a and the second polysilicon structure 281b are etched using the first hardmask spacer 282a and the second hardmask spacer 282b as masks, to form the first selection gate 280a and the second selection gate 280b, respectively.

According to some embodiments, after forming the semiconductor structure 400 as shown in FIG. 4B, the process steps as described above with reference to FIGS. 3L-3O may be performed to form a flash memory semiconductor device.

5 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming the first polysilicon structure 281a on the first region and the second polysilicon structure 281b on the second region as shown in FIG. 3I, as shown in FIG. The deposited select gate polysilicon is quasi-etched to form a first select gate 280a and a second select gate 280b, respectively.

According to some embodiments, after forming the semiconductor structure 500 as shown in FIG. 5, the process steps as described above with reference to FIGS. 3L-3O may be performed to form a flash memory semiconductor device.

6 is a schematic cross-sectional view of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming the first gate oxide film 291 covering the semiconductor device 300 as shown in FIG. 3F , as shown in FIG. 6 , select gates are performed in the first and second regions of the substrate 210 Channel ion implantation, including: performing selective gate channel lithography to form a photoresist pattern, so as to protect areas where ion implantation is not required; and using the formed photoresist pattern as a mask to perform selective gate channel lithography ion implantation; then, portions of the first gate oxide film 291 on the first and second regions and the upper surface of the gate stack are removed, and the first gate oxide film 291 on the side surfaces of the gate stack is removed A portion of the gate oxide film 291 to form sidewall oxide structures 291a and 291b on both sides of the gate spacer. According to some embodiments, by etching (eg, dry etching and wet etching) the first gate oxide film 291, a portion of the first gate oxide film 291 on the sidewalls of the gate stack remains. According to other embodiments, instead of partially removing the first gate oxide film 291 on the side of the gate stack, the first gate oxide film 291 on the side of the gate stack is completely removed, and then For example, a certain thickness of oxide is formed on the sidewall of the floating gate by means of polysilicon oxidation.

According to some embodiments, after forming the semiconductor structure 600 as shown in FIG. 6, the process steps as described above with reference to FIGS. 3H-3O may be performed to form a flash memory semiconductor device.

As an embodiment of the present disclosure, there is also provided a semiconductor device manufactured by the method for manufacturing a semiconductor device as described in the present disclosure.

FIG. 7 is a schematic cross-sectional structure diagram of a semiconductor device 700 according to some embodiments of the present disclosure.

According to some embodiments, semiconductor device 700 includes substrate 210, substrate oxide structure 221 formed over substrate 210, gate stacks 270a and 270b on substrate oxide structure 221, first select gate 280a , a second select gate 280b, a first drain region 211a, a second drain region 211b, and a source region 212 in the substrate 210, wherein the first gate stack 270a includes a first floating gate 230a, first dielectric structure 240a, first control gate 250a and first hard mask 260a, second gate stack 270b including second floating gate 230b, second dielectric structure 240b, second control gate 250b and the second hard mask 260b.

According to some embodiments, the semiconductor device 700 further includes the substrate gate oxide structure 221 under the first gate stack 270a and the second gate stack 270b, the first select gate 280a and the first gate stack first tunnel oxide structure 271a between the bodies 270a, second tunnel oxide structure 271b between the second select gate 280b and the second gate stack 270b, under the first select gate 280a The first select gate oxide structure 222a, and the second select gate oxide structure 222b under the second select gate 280b.

According to some embodiments, semiconductor device 700 includes two memory cells that share source region 212 . According to some embodiments, the semiconductor device 700 includes a first programming channel 213a, a second programming channel 213b, a first erasing channel 214a corresponding to the memory cells on the left, and a second programming channel 213c corresponding to the memory cells on the right, The second programming channel 213d and the second erasing channel 214b. According to some embodiments, the first programming channel 213a extends from the first drain region 211a to an edge portion of the first floating gate 230a facing the first select gate 280a, and the second programming channel 213b extends from the first drain region 211a extends to the source region 212, a first erase channel 214a extends from the first floating gate 230a to the first select gate 280a, and a third programming channel 213b extends from the second drain region 211b to the second floating gate The edge portion of the electrode 230b facing the second select gate 280b, the fourth programming channel 213b extends from the second drain region 211b to the source region 212, and the second erase channel 214b extends from the second floating gate 230b to The second select gate 280b. Wherein, the processes of performing programming, erasing and reading operations on the memory cells on the left and the memory cells on the right are similar. The following takes the memory cell on the left as an example to illustrate the programming operation, the erasing operation and the reading operation, respectively.

According to some embodiments, when a programming operation is performed, a positive voltage (eg, 1.0-1.6V) higher than the threshold voltage is applied on the first select gate 280a, while the source terminal (ie, the source region 212 ) is applied A positive voltage (for example, 4.5-7V) provides a strong lateral electric field, and a negative current (for example, 1 μA) is injected into the first drain region 211a. At this time, due to the electron source injection effect, a part of hot electrons pass through the first programming channel 211a is injected into the first floating gate 230a, and a portion of the hot electrons migrate to the source through the second programming channel 211b.

According to some embodiments, when an erase operation is performed, a relatively high positive voltage (eg, 7-11V) is applied to the first select gate 280a, and a relatively high negative voltage is applied to the first control gate 250a (eg, -7V to 11V) to form a voltage difference between the first select gate 280a and the first floating gate 230a, and both the first drain region 211a and the source region 212 are set to 0V, this At the time, due to the FN (Fowler-Nordheim) tunneling effect, the electrons are pulled away from the first floating gate 230a under the action of the voltage difference between the first select gate 280a and the first floating gate 230a.

According to some embodiments, when performing a read operation, a positive voltage (eg, 1.8V) is applied to the first control gate 250a by applying a positive voltage (eg, 1.8V) to the first select gate 280a , a lower positive voltage (for example, 0.6V) is applied to the first drain region 211a, and the source region 212 is set to 0V. At this time, the current value between the source terminal and the drain terminal is used to determine The state the memory cell is in.

8 is a circuit schematic diagram of a memory cell array 800 in accordance with some embodiments of the present disclosure. It should be understood that the numbers of memory cells, word lines, bit lines, source lines and erase lines in FIG. 8 are only illustrative, and any of the above numbers can be adjusted according to actual application requirements to achieve larger or smaller arrays of memory cells.

As shown in FIG. 8, memory cell array 800 includes a plurality of memory cells (eg, memory cell 810 shown in FIG. 8). According to some embodiments, each memory cell includes a selection transistor and a floating transistor connected in series, for example, memory cell 810 in FIG. 8 includes a selection transistor 811 and a floating gate transistor 812, wherein the The memory cell operates, and the floating gate transistor 812 can store information.

According to some embodiments, the memory cells of each row correspond to a word line, for example, in FIG. 8, the memory cells of the upper row correspond to word line WLn-1, the memory cells of the lower row correspond to word line WLn, and each The word lines are connected to the gates of the select transistors in the corresponding memory cells. According to some embodiments, each column of memory cells corresponds to a bit line. For example, in FIG. 8, the memory cells in the left column correspond to bit line BLn-1, the memory cells in the middle column correspond to bit line BLn, and the memory cells in the right column correspond to bit line BLn. The memory cells correspond to bit lines BLn+1, and each bit line is connected to the drain of a select transistor in the corresponding memory cell. According to some embodiments, memory cells in two adjacent rows correspond to one source line. For example, in FIG. 8 , memory cells in the upper and lower rows both correspond to source lines SL, and each source line is connected to a corresponding memory cell. the source of the floating gate transistor. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together. According to some embodiments, in the memory cell array 800, the memory cells of each row correspond to a control line, eg, in FIG. 8, the memory cells of the upper row correspond to the control line CGn-1, and the memory cells of the lower row correspond to the control line CGn-1. control lines CGn, and each control line is connected to the control gate of the floating transistor in the corresponding memory cell;

According to some embodiments, the drain of the select transistor in the memory cell corresponds to, for example, the first drain region 211a in the semiconductor device 700 shown in FIG. 7 , and the gate of the select transistor in the memory cell corresponds, for example, to that shown in FIG. The first select gate 280a in the semiconductor device 700, the floating gate of the floating transistor in the memory cell corresponds to the first floating gate 230a in the semiconductor device 700 shown in FIG. 7, the floating gate in the memory cell The control gate of the floating transistor corresponds to the first control gate 230a in the semiconductor device 700 shown in FIG. 7, and the source of the floating transistor in the memory cell corresponds to the source region in the semiconductor device 700 shown in FIG. 7 212.

9A-9B are top plan views of memory cell arrays in accordance with some embodiments of the present disclosure. As shown in FIG. 9A, the memory cell array 900 includes a plurality of bit lines BLn-1, BLn and BLn+1, a plurality of word lines WLn-1 and WLn, a plurality of floating gates FG1-FG6 and a source line SL.

According to some embodiments, the memory cells of each column correspond to the same bit line, eg, as shown in FIG. 9A, the two memory cells of the left column both correspond to the bit line BLn-1. It should be understood that, although not shown, the bit line structures of memory cells of the same column are electrically connected.

According to some embodiments, the memory cells of each row correspond to the same word line, eg, as shown in FIG. 9A, the three memory cells of the upper row all correspond to word line WLn-1. According to some embodiments, as shown in Figure 9A, each word line extends through multiple memory cells in the same row.

According to some embodiments, each row of memory cells corresponds to a control line, for example, in FIG. 9A , the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each The control lines are connected to the floating gates in the corresponding memory cells.

According to some embodiments, the memory cells of adjacent rows correspond to the same source line, eg, as shown in FIG. 9A , the six memory cells in the upper and lower rows all correspond to the source line SL. According to some embodiments, as shown in FIG. 9A, source lines SL extend in the substrate through adjacent rows of memory cells, wherein the source lines communicate with source regions in a plurality of bit lines.

The memory cell array 900 shown in FIG. 9B and FIG. 9B is different from the memory cell array 900 shown in FIG. 9A in that instead of source lines SL extending through a plurality of bit lines in the substrate, a corresponding tungsten plugs (eg, the corresponding tungsten plugs Wn-1 of the bit line BLn- 1 ), and the respective tungsten plugs are connected by metal lines to communicate the source regions in the plurality of bit lines.

Some exemplary aspects of the present disclosure are described below.

Aspect 1. A method of manufacturing a semiconductor device, comprising:

forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer in sequence on the substrate;

etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer a gate stack formed by the remaining portion of the floating gate layer;

removing portions of the oxide layer on first and second regions of the substrate, wherein the first and second regions flank the gate stack;

A first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, and on both sides of the gate stack, respectively forming a first tunneling oxide structure and a second tunneling oxide structure;

A first select gate is formed on the side of the first tunnel oxide structure opposite the gate stack, and on the side of the second tunnel oxide structure opposite the gate stack One side of the second select gate is formed;

etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remainder of the floating gate layer;

forming a source region in a portion of the substrate below the first opening; and

A first drain region is formed in the substrate on the side of the first select gate opposite the first opening, and a first drain region is formed on the side of the second select gate opposite the first opening A second drain region is formed in the substrate on the side.

Aspect 2. The method of aspect 1, wherein the forming a first select gate oxide structure and a second select gate oxide on the first region and the second region, respectively, of the substrate and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack respectively includes:

A second gate oxide film is deposited on the first region and the second region of the substrate, and on the side and upper surface of the gate stack to form the first select gate oxide an oxide structure and the second select gate oxide structure; and

removing portions of the first and second gate oxide films on the upper surface of the gate stack to form the first and second tunneling oxide structures oxide structure.

Aspect 3. The method of aspect 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film:

depositing a first gate oxide film on the first and second regions of the substrate, and on the side and upper surfaces of the gate stack; and

removing portions of the first gate oxide film on the first and second regions of the substrate, the upper surface of the gate stack, and removing the gate A portion of the first gate oxide film on the side surface of the electrode stack.

Aspect 4. The method of aspect 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film:

depositing a first gate oxide film on the first region and the second region of the substrate, and on the side and upper surfaces of the gate stack;

removing portions of the first gate oxide film on the first and second regions of the substrate, an upper surface and side surfaces of the gate stack; and

Sidewall oxide structures are formed on sides of the gate stack.

Aspect 5. The method of aspect 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film:

depositing a first gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack; and

removing portions of the first gate oxide film on the first region of the substrate, the second region, the upper surface and side surfaces of the gate stack, and the Deposition of a second gate oxide film on the first region and the second region of the substrate and on the side and upper surfaces of the gate stack includes:

A second gate oxide film is deposited on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack.

Aspect 6. The method of aspect 5, further comprising removing the first gate oxide film on the first region and the second region of the substrate, and the gate Before the section on the upper surface of the pole stack:

Select gate channel ion implantation is performed in the first region and the second region of the substrate.

Aspect 7. The method of aspect 5, further comprising on the first region, the second region, and the high voltage tube region of the substrate, and side and upper surfaces of the gate stack After depositing the second gate oxide film on:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate; and

A logic core gate oxide structure is formed on the substrate.

Aspect 8. The method of any of aspects 1-7, wherein the forming a first select gate on an opposite side of the first tunnel oxide structure from the gate stack , and forming a second select gate on a side of the second tunnel oxide structure opposite to the gate stack includes:

depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack; and

The portion of the deposited select gate polysilicon is removed to form the first select gate and the second select gate.

Aspect 9. The method of aspect 8, wherein the removing the deposited portion of the select gate polysilicon to form the first select gate and the second select gate comprises:

planarizing the deposited select gate polysilicon;

etching the select gate polysilicon subjected to the planarization process to form a first polysilicon structure and a second polysilicon structure on first and second regions of the substrate, respectively; and

The first and second polysilicon structures are etched to form the first and second select gates, respectively.

Aspect 10. The method of aspect 9, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively include:

performing a first photolithography process on the first polysilicon structure and the second polysilicon structure;

Using the photoresist pattern formed by the first photolithography process as a mask, the first polysilicon structure and the second polysilicon structure are etched to form the first selection gate and the first selection gate, respectively. two select gates; and

The photoresist pattern formed by the first photolithography process is removed.

Aspect 11. The method of aspect 9, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively include:

A first hard mask spacer and a second hard mask spacer are respectively formed on both sides of the gate stack, wherein the first hard mask spacer is located on the first polysilicon structure, and the second hardmask spacers are on the second polysilicon structure; and

etching the first polysilicon structure and the second polysilicon structure using the first hard mask spacers and the second hard mask spacers as masks to form the first select gates, respectively pole and the second select gate.

Aspect 12. The method of aspect 8, wherein the removing the deposited portion of the select gate polysilicon to form the first select gate and the second select gate comprises:

The deposited select gate polysilicon is self-aligned to form the first select gate and the second select gate, respectively.

Aspect 13. The method of aspect 8, further comprising:

While depositing the select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack, a logic gate of the substrate is depositing logic gate polysilicon on the pole regions; and

At the same time as the removing the deposited portion of the select gate polysilicon to form the first select gate and the second select gate, removing the portion of the logic gate polysilicon to form the logic gate.

Aspect 14. The method of any of aspects 1-7, wherein the forming a first drain in the substrate on a side of the first select gate opposite the first opening region, and forming a second drain region in the substrate on the opposite side of the second select gate from the first opening includes:

Light doping is performed in the substrate on the side of the first select gate opposite the first opening and in the substrate on the side of the second select gate opposite the first opening Drain implantation to form a first lightly doped drain region on one side of the first select gate and a second lightly doped drain region on one side of the second select gate;

A first drain spacer is formed on the opposite side of the first select gate from the first opening, and a first drain spacer is formed on the opposite side of the second select gate from the first opening. Two drain spacers;

A first source spacer is formed on a side of the first select gate facing the first opening, and a first source spacer is formed on a side of the second select gate facing the first opening two source spacers; and

Reproducing is performed in the substrate on the side of the first drain spacer opposite the first opening and in the substrate on the side of the second drain spacer opposite the first opening a doped drain implant to form a first heavily doped drain region on one side of the first drain spacer and a second heavily doped drain on one side of the second drain spacer area.

Aspect 15. The method of any of aspects 1-7, further comprising:

A suicide structure is formed on the first select gate, the first drain region, the source region, the second select gate and the second drain region.

Aspect 16. A semiconductor device fabricated by the method of any of aspects 1-15.

While the present disclosure has been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustration and description are to be considered illustrative and schematic and not restrictive; example. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more . The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising: forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer in sequence on the substrate; etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer a gate stack formed by the remaining portion of the floating gate layer; removing portions of the oxide layer on first and second regions of the substrate, wherein the first and second regions flank the gate stack; A first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, and on both sides of the gate stack, respectively forming a first tunneling oxide structure and a second tunneling oxide structure; A first select gate is formed on the side of the first tunnel oxide structure opposite the gate stack, and on the side of the second tunnel oxide structure opposite the gate stack One side of the second select gate is formed; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer and the remainder of the floating gate layer; forming a source region in a portion of the substrate below the first opening; and A first drain region is formed in the substrate on the side of the first select gate opposite the first opening, and a first drain region is formed on the side of the second select gate opposite the first opening A second drain region is formed in the substrate on the side. 2. The method of claim 1, wherein the forming a first select gate oxide structure and a second select gate oxide on the first region and the second region of the substrate, respectively and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack respectively includes: A second gate oxide film is deposited on the first region and the second region of the substrate, and on the side and upper surface of the gate stack to form the first select gate oxide an oxide structure and the second select gate oxide structure; and removing portions of the first and second gate oxide films on the upper surface of the gate stack to form the first and second tunneling oxide structures oxide structure. 3. The method of claim 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film: depositing a first gate oxide film on the first and second regions of the substrate, and on the side and upper surfaces of the gate stack; and removing portions of the first gate oxide film on the first and second regions of the substrate, the upper surface of the gate stack, and removing the gate A portion of the first gate oxide film on the side surface of the electrode stack. 4. The method of claim 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film: depositing a first gate oxide film on the first region and the second region of the substrate, and on the side and upper surfaces of the gate stack; removing portions of the first gate oxide film on the first and second regions of the substrate, an upper surface and side surfaces of the gate stack; and Sidewall oxide structures are formed on sides of the gate stack. 5. The method of claim 2, further comprising depositing a second gate on the first region and the second region of the substrate, and on side and upper surfaces of the gate stack Before oxide film: depositing a first gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack; and removing portions of the first gate oxide film on the first region of the substrate, the second region, the upper surface and side surfaces of the gate stack, and the Deposition of a second gate oxide film on the first region and the second region of the substrate and on the side and upper surfaces of the gate stack includes: A second gate oxide film is deposited on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack. 6. The method of claim 5, further comprising removing the first gate oxide film on the first region and the second region of the substrate, and the gate Before the section on the upper surface of the pole stack: Select gate channel ion implantation is performed in the first region and the second region of the substrate. 7. The method of claim 5, further comprising on the first region, the second region, and the high voltage tube region of the substrate, and side and upper surfaces of the gate stack After depositing the second gate oxide film on: performing logic well implantation in the substrate; forming a logic IO gate oxide structure on the substrate; and A logic core gate oxide structure is formed on the substrate. 8. The method of any one of claims 1-7, wherein the forming a first select gate on an opposite side of the first tunnel oxide structure from the gate stack , and forming a second select gate on a side of the second tunnel oxide structure opposite to the gate stack includes: depositing select gate polysilicon on the first select gate oxide structure and the second select gate oxide structure, and on the gate stack; and The portion of the deposited select gate polysilicon is removed to form the first select gate and the second select gate. 9. The method of claim 8, wherein the removing the deposited portion of the select gate polysilicon to form the first select gate and the second select gate comprises: planarizing the deposited select gate polysilicon; etching the select gate polysilicon subjected to the planarization process to form a first polysilicon structure and a second polysilicon structure on first and second regions of the substrate, respectively; and The first and second polysilicon structures are etched to form the first and second select gates, respectively. 10. A semiconductor device manufactured by the method according to any of claims 1-9.

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