CN114743945A - Advanced package structure with Si and organic interposer and method of making the same - Google Patents

Abstract

The invention discloses an advanced packaging structure with Si and organic interposer and a manufacturing method thereof. The structure includes a substrate for low-density wiring, a Si interposer for high-density RDL wiring, and an organic dielectric layer for medium-density RDL wiring. The interposer is embedded on the surface of the substrate, and the organic dielectric layer is packaged on the surface of the Si interposer and the substrate by using a fan-out panel level, and is electrically connected with the substrate and the Si interposer. The Si interposer provides high-density RDL wiring, the organic dielectric layer of the fan-out panel level packaging process provides medium-density RDL wiring, and the FCBGA substrate provides low-density wiring. The advanced packaging structure of the present invention simultaneously uses these three different wiring densities. The medium can provide processors, logic and multi-chip integration in an advanced package structure. From 1 to 6 chips can be put into the package. The more the number of chips, the better the computing efficiency of the processor.

Description

Advanced package structure with Si and organic interposer and method of making the same

technical field

The invention belongs to the field of semiconductor packaging, and in particular relates to an advanced packaging structure with Si and an organic intermediate layer and a manufacturing method thereof.

Background technique

As a variety of applications such as artificial intelligence (AI), data center, high performance computing (HPC), networking and graphics accelerated graphics cards require higher memory bandwidth, advanced packaging has become a support for high bandwidth memory (HBM, high bandwidth memory) wide I. /O is an increasingly important factor. At present, three advanced packaging technologies are mainly used in the industry, TSMC's CoWoS (Chip on Wafer on Substrate), Intel's EMIB (Embedded Multi-DieInterconnect Bridge) and Samsung's H-Cube.

TSMC's CoWoS: a typical 2.5D package, the processor, logic and HBM chips are mounted on the Si interposer, and there are multiple layers of redistribution layers (RDL, redistribution layer) on the Si interposer, and the line width of the distribution layer wiring is The line spacing is less than 1.2 micrometers (um). Such fine wiring can provide high- and medium-density signal connections between chips. At this time, the FCBGA substrate (or carrier board) cannot provide the wiring density, as well as the connection of medium and low-density signals. The Si interposer is then installed on the FCBGA substrate. The Si interposer has TSV (through silicon via, through silicon via), which conducts the upper layer signal to the lower layer, and then conducts signal conduction with the FCBGA substrate. The production of Si interposer wafers is done by the fab. Due to the limitations of reticle and exposure process equipment, it is difficult for the Si interposer to be large enough to place many chips. In addition, CoWoS is criticized for its high cost. place.

Intel's EMIB: Intel's approach is to reduce the size of the expensive Si interposer. The Si interposer has no TSV (through silicon via, through silicon via), and the upper layer signal is guided to the lower layer, because the signal is only on the surface of the Si interposer. RDL Intra-transmission, the absence of TSV potentially degrades the performance of the chip.

Single or multiple Si interposers are embedded in the FCBGA substrate. The wirings that require high and medium-density signal connections are designed on the Si interposer, and the wirings for low-density signal connections are designed on the FCBGA substrate, although the size of the Si interposer is reduced. Cost, but FCBGA substrate cannot design the wiring of medium-density signal connection (line width and line spacing between 8um and 1.5um), there is silica filler in ABF material, blind via hole cannot be used Etching is used to open holes, and laser drilling is used to open blind via holes. The size is limited. Too small holes cannot be drilled, so the size and spacing of the contacts between the substrate and the chip cannot be reduced. Si interposer And the chip size cannot be further reduced, and the cost cannot be reduced.

At present, the contact distance between the chip and the Si interposer is 55um, and the contact distance between the chip and the FCBGA substrate is 130um.

Samsung's H-Cube: Basically similar to TSMC's CoWoS, the chip is mounted on a large Si interposer, the Si interposer is mounted on a fine pitch substrate, and then mounted on a high-density interconnect ( HDI, high density interconnect) substrate. Because of the use of a large Si interposer and two substrates, the problems faced are the same as those of CoWoS. It is difficult to make the Si interposer large enough and the cost is high.

Therefore, the existing practice is not that the size of the Si interposer is large (because all the high, medium and low density wirings are on it), which causes the cost to be too expensive. That is, the size of the Si interposer is reduced, and the high and medium-density wiring is on it. The FCBGA substrate can only design low-density (line width and line spacing greater than 8um) wiring. The size of the Si interposer cannot be further reduced, even when more chips are placed. , the size of the Si interposer has to be increased, and the cost cannot be further reduced.

SUMMARY OF THE INVENTION

The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the present invention provides an advanced packaging structure with Si and an organic interposer and a manufacturing method thereof. The present invention has both low cost and high input/output density, and is suitable for integrating more HBM and processor chips ( or logic chip) to improve the performance of the operation is of great help.

The technical scheme adopted in the present invention is:

An advanced package structure with Si and organic interposer, comprising a substrate for low density wiring, a Si interposer for high density RDL wiring, and an organic dielectric layer for medium density RDL wiring, the Si interposer being embedded in all the surface of the substrate, the organic dielectric layer is encapsulated on the surface of the Si interposer and the substrate by using a fan-out panel, and is electrically connected to the substrate and the Si interposer; the line width of the low-density wiring The line spacing is larger than the line width and line spacing of the medium density RDL wiring, and the line width and line spacing of the medium density RDL wiring is larger than the line width and line spacing of the high density RDL wiring.

Optionally, the substrate is a FCBGA substrate, including a core layer and several build-up circuit layers laminated on both sides of the core layer, and each layer of the build-up circuit layer and the core layer passes through a laser. The opening and the metal plating in the hole are used for electrical connection.

Optionally, the line width and line spacing of the low density wiring is greater than 8 μm, the line width and line spacing of the medium density RDL wiring is between 8 μm and 1.5 μm, and the line width and line spacing of the high density RDL wiring is less than 1.5 μm.

Optionally, the organic dielectric layer includes alternately stacked multi-layer polyimide and multi-layer medium-density RDL wirings, and each layer of the medium-density RDL wirings is etched to open the polyimide between the holes and the inside of the holes. Metal plated for electrical connection.

Optionally, the Si interposer and the organic dielectric layer are provided on the upper surface of the substrate, the lower surface of the substrate is provided with tin ball pads, and the contacts on the upper surface of the organic dielectric layer are provided with tin-copper bumps piece.

Optionally, the line width and line spacing of the medium-density RDL wiring decreases as the distance from the location where the memory chip is to be installed decreases.

Optionally, a cavity is formed on the upper surface of the substrate corresponding to the position of the Si interposer, and the gap between the Si interposer and the cavity is filled with resin.

Optionally, the surface contacts of the Si interposer are provided with metal bumps, and when the Si interposer is embedded in the substrate, the metal bumps are coplanar with the surface contacts of the substrate.

A manufacturing method for manufacturing an advanced package structure with Si and an organic interposer as described above, the manufacturing method comprising:

Si interposer for making high-density RDL wiring;

making a low-density wiring substrate, and opening a cavity on the upper surface of the substrate corresponding to the position of the Si interposer;

embedding the Si interposer in the cavity;

Adhere the lower surface of the substrate with the Si interposer embedded on the carrier, and use the fan-out panel level packaging on the upper surface to make several layers of organic dielectric layers of medium density RDL wiring, so that the organic dielectric layers of the organic dielectric layers are RDL wiring is electrically connected to the Si interposer and the substrate;

forming tin-copper bumps on the top surface of the Si interposer;

Remove the carrier and cut into individual pieces.

Optionally, the substrate is an FCBGA substrate, and the step of fabricating the FCBGA substrate includes:

Making a core layer of a substrate, by opening holes on the core layer and plating metal to conduct circuits on both sides of the core layer;

Several build-up circuit layers are laminated and stacked on both sides of the core layer, and the build-up circuit layers and the core layer are electrically connected through laser openings and metal plating in the holes.

Optionally, metal bumps are provided on the contacts on the upper surface of the Si interposer, and after the Si interposer is embedded in the cavity, a metal bump is filled between the Si interposer and the cavity. The resin is poured, and the build-up circuit layer is continuously laminated on the Si interposer and the upper surface of the substrate. The height of the metal-plated portion in the laser opening between the build-up circuit layers is the same as the height of the metal bump.

Optionally, before using fan-out panel level packaging to fabricate the organic dielectric layer on the upper surface of the substrate, the method further includes the steps of:

Grind the build-up circuit layer on the upper surface of the substrate and the Si interposer until the metal-plated part in the laser opening between the metal bump and the build-up circuit layer is exposed, and reaches the designed thickness and flatness .

Optionally, the step of fabricating the organic dielectric layer includes: alternately stacking multiple layers of polyimide and multiple layers of medium-density RDL wiring on the upper surface of the substrate and the Si interposer, and each layer of the medium-density RDL The wirings are electrically connected by etching the polyimide between the holes and plating metal in the holes.

Optionally, after the last organic dielectric layer is fabricated, blind holes are opened in polyimide by exposure, development and etching to fabricate tin-copper bumps electrically connected to the medium-density RDL wiring.

Optionally, the manufacturing method further comprises the steps of:

Flip-chip processors, logic, and several high-bandwidth memory chips on the Si interposer on the upper surface of the single-cut substrate, and place a number of tin-copper bumps on the chip with the tin-copper on the upper surface of the Si interposer. Bump welding for electrical conduction;

Underfill the gap between the chip and the Si interposer, attach a heat sink, and the heat sink and the back of the chip have thermal interface materials to assist heat conduction;

Solder ball pads are formed on the lower surface of the substrate.

Owing to adopting the above-mentioned technical scheme, the present invention has the following beneficial effects:

The present invention has an advanced packaging structure with Si and an organic interposer, the Si interposer provides high-density RDL wiring, the organic dielectric layer of the fan-out panel-level packaging process provides medium-density RDL wiring, and the FCBGA substrate provides low-density wiring, The advanced packaging structure of the present invention uses these three media with different wiring densities at the same time, and can provide multi-chip integration of processor, logic and high bandwidth memory (HBM, high bandwidth memory) in the advanced packaging structure. 1 to 6 can be put into the package. The more HBMs, the better the computing efficiency of the processor.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 to 5 are schematic structural diagrams presented in each step of the FCBGA substrate manufacturing process provided by the embodiment of the present invention.

FIG. 6 is a schematic structural diagram of an FCBGA substrate embedded Si interposer manufacturing process according to an embodiment of the present invention.

FIGS. 7 to 11 are schematic structural diagrams presented in each step of a process of fabricating an organic dielectric layer on an FCBGA substrate provided in an embodiment of the present invention.

The corresponding relationship between the reference numerals is as follows:

1-FCBGA substrate; 11-core layer; 111-through hole; 112-copper foil; 12-build-up circuit layer; 121-ABF build-up diaphragm; 122-copper wire; 123-blind hole; 13-cavity; 2-Si interposer; 21-copper bumps or copper pillars; 22-DAF mucous membrane; 23-resin; 3-organic dielectric layer; 31-polyimide (PI); 32-medium density RDL wiring; 33-photoresist or photoresist film; 4-tin copper bumps; 5-solder ball pads; 6-glass carrier; 7-adhesive; 8-processor (Processor); 9-high bandwidth inner layer Chip (HBM); 10-underfill.

Detailed ways

The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted here that the descriptions of these embodiments are used to help the understanding of the present invention, but do not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

First, the technical terms that appear in the text are explained as follows:

RDL: Redistribution Layer, redistribution layer, contains copper connecting lines or traces, used to achieve electrical connections between various parts of the package, it is a metal or polymer dielectric material layer, the die can be stacked in the package, thereby shrinking The I/O spacing of the chipset; RDL has become an integral part of 2.5D and 3D packaging solutions, allowing the chips on it to communicate with each other through the interposer;

DAF: Die Attach Film, the purpose is that during laser cutting, the wafers can be cut and separated together, and peeled off, so that the cut wafers can still be attached to the film, and will not be scattered due to cutting. arrangement;

FCBGA (Flip Chip Ball Grid Array): The packaging format of flip chip ball grid array, and it is also the most important packaging format of graphics acceleration chips;

Build-up: It is a process of forming a thin film on the surface of the wafer;

ABF: ABF material is a material developed by Intel. It is used for the production of high-end carrier boards such as Flip Chip. Compared with BT base material, ABF material can be used as IC with thinner lines and suitable for high pin count and high transmission. It is suitable for large-scale high-end chips such as CPU, GPU and chipset; ABF is used as a build-up material, and the ABF can be directly attached to the copper foil substrate to make a circuit, and no hot pressing process is required;

HBM: High Bandwidth Memory, high bandwidth memory chip;

PI: Polyimide, polyimide, refers to a class of polymers containing an imide ring (-CO-N-CO-) in the main chain, and is one of the organic polymer materials with the best comprehensive properties. Its high temperature resistance is above 400 °C, the long-term use temperature range is -200 ~ 300 °C, some parts have no obvious melting point, high insulation performance, the dielectric constant at 103 Hz is 4.0, and the dielectric loss is only 0.004 ~ 0.007, which belongs to F to H class insulation.

At present, there are three types of packages for high-efficiency computing combined with Processor and HBM chips. TSMC's CoWoS, Intel's EMIB, and some companies propose to integrate the CPU and HBM chips in the FO package, and then put the FO package in the FCBGA. Program. Among them, CoWoS can provide the best high input/output density solution, but the cost is high. The other two solutions, although less expensive, can provide a lower density of input/output. The present invention has both low cost and high input/output density, and is of great help for integrating more HBMs to improve computing performance.

Specifically, refer to 1-11, wherein, FIGS. 1-5 are schematic structural diagrams of each step of the FCBGA substrate manufacturing process provided by the embodiment of the present invention; FIG. 6 is the FCBGA substrate embedded Si interposer provided by the embodiment of the present invention. Schematic diagram of the structure presented by the manufacturing process; FIGS. 7-11 are schematic diagrams of the structure presented by each step of the manufacturing process of the organic dielectric layer on the FCBGA substrate provided by the embodiment of the present invention.

The advanced packaging structure with Si and organic interposer provided by the embodiment of the present invention mainly uses interposers of different materials to express the width and spacing of different lines to support high input/output (I/O: Input/Output) The interconnection of signals between the density chips.

The advanced packaging structure with Si and organic interposer mainly includes a substrate 1 for low-density wiring, a Si interposer 2 for high-density RDL wiring, and an organic dielectric layer 3 for medium-density RDL wiring, wherein the Si interposer 2 is embedded On the surface of the substrate 1, the organic dielectric layer 3 is encapsulated on the surface of the Si interposer 2 and the substrate 1 by using a fan-out panel level, and is electrically connected to the substrate 1 and the Si interposer 2; wherein, the line width and line spacing of the low-density wiring is greater than that of the medium. The line width and line spacing of density RDL wiring, and the line width and line spacing of medium density RDL wiring are larger than those of high density RDL wiring. Preferably, the line width and line spacing of low-density wiring is greater than 8 μm, the line width and line spacing of medium density RDL wiring is between 8 μm and 1.5 μm, and the line width and line spacing of high density RDL wiring is less than 1.5 μm.

As shown in FIGS. 1 to 5 , the substrate 1 is preferably a FCBGA substrate, which includes a core layer 11 and several build-up circuit layers 12 laminated on both sides of the core layer 11 . Electrical connection is made through laser opening and metal plating in the hole.

As shown in FIG. 1 , the core layer 11 of the FCBGA substrate 1 has several layers, the main three layers are the middle layers made of glass fiber and resin, and the upper and lower layers of the middle layer are copper foils 112 . A hole 111 is opened on the substrate of the core layer 11, copper (or other equivalent metal) is plated in the through hole 111, and the copper foil 112 outside the circuit part is removed by etching to form a circuit, and the upper and lower circuits are plated through the through hole 111 and the inside of the hole. Copper conducts.

The upper and lower sides of the core layer 11 are laminated with multilayer build-up circuit layers 12 respectively, and the build-up circuit layers 12 on both sides of the core layer 11 are electrically connected through the through holes 111 and copper plating in the holes. Each build-up circuit layer 12 further includes an ABF build-up film 121 and a circuit formed by copper wires 122 (or other equivalent metal wires) formed on the surface of the ABF build-up film 121 . The specific method is to use a lamination process (or build-up process) to laminate ABF (Ajinomoto Build-up Film, Ajinomoto Build-up Film) or an equivalent material on both sides of the core layer 11, and expose the circuit pattern. , and directly form a copper wire circuit by developing and etching copper plating. Repeat this process for many times to stack and build up layers (layers). There are blind via holes 123 (blind via holes) between the copper wires 122 of each layer for electrical connection. The blind via holes 123 are drilled by laser, and the size is limited and too small. The holes cannot be drilled, and the blind holes 123 are filled with electroplated copper 124 (or other equivalent metals). The lamination process is repeated several times to the required number of layers, as shown in FIGS. 2 to 4 .

The ABF build-up film 121 of the last build-up circuit layer 12 on the upper surface of the FCBGA substrate 1 has a cavity 13 for placing the Si interposer 2. As shown in FIG. 5 and FIG. 6 , between the Si interposer 2 and the cavity 13 The gap is filled with resin 23 . High-density RDL wiring is arranged on the Si interposer 2, and copper bumps or copper pillars 21 (or other equivalent metal bumps) are arranged at the contact positions on the upper surface of the Si interposer 2. The Si interposer 2 is embedded in the FCBGA When inside the cavity 13 on the upper surface of the substrate 1, the copper bumps or copper pillars 21 face upward and are coplanar with the surface contacts of the FCBGA substrate 1. As shown in FIG. 7, a Si interposer can be embedded on the FCBGA substrate 1. After 2, the build-up circuit layer 12 is continuously laminated on the upper surface of the FCBGA substrate 1, and the height of the electroplated copper 124 in the laser openings between the build-up circuit layers 12 is consistent with the height of the copper bumps or copper pillars 21.

As shown in FIGS. 8-10 , the organic dielectric layer 3 includes multiple layers of polyimide 31 and multiple layers of medium-density RDL wirings 32 stacked alternately, and the polyimide between the layers of medium-density RDL wirings 32 is etched to open the holes between them. The amine 31 and the electroplated copper (or other equivalent metal) in the hole are electrically connected, and the medium density RDL wiring 32 and the polyimide 31 in the organic dielectric layer 3 are fabricated on the FCBGA substrate 1 and On the Si interposer 2 , the medium-density RDL wiring 32 electrically conducts the low-density wiring on the FCBGA substrate 1 and the medium-density RDL wiring on the Si interposer 2 . The Si interposer 2 and the organic dielectric layer 3 are disposed on the upper surface of the FCBGA substrate 1, and the lower surface of the FCBGA substrate 1 is provided with tin ball pads 5. As shown in FIG. 11, the upper surface of the organic dielectric layer 3 is provided with tin-copper bumps Block 4. The tin-copper bumps 4 can be used for soldering the tin-copper bumps on the memory chip 9. About the position close to the memory chip 8, the line width and line spacing of the medium-density RDL wiring 32 in the organic dielectric layer 3 are finer, even as thin as 1.5 μm～2.0μm.

The reduced size of the Si interposer embedded in the FCBGA can reduce the cost, the packaging process is relatively simple, and the packaging cost is relatively low. However, because the high and medium-density wiring is on the Si interposer, the size of the Si interposer cannot be further reduced, and even when more chips are placed, the size of the Si interposer must be increased.

In the present invention, the medium-density wiring is removed from the Si interposer and placed on the polyimide organic dielectric layer. This polyimide organic dielectric layer can design medium-density wiring (the RDL line width and line spacing capability is between 10 to 1.5 microns) and have a lower cost.

Throughout the entire electronics and semiconductor supply chain, the fab process mainly handles line widths and line spacings from 1 micrometer (um) to 3 nanometers (nm), and the printed circuit board process handles line widths of several millimeters (mm) or more. The line spacing, the process of the packaging factory handles the line width and line spacing of several millimeters (mm) to several micrometers (um), while the substrate used by the packaging factory processes the line width of 8 micrometers (um) to several hundreds of micrometers. The line spacing, the bumps of the packaging factory, and the fan-in/fan-out packaging process can handle the line width and line spacing of tens of microns to 1 micron, so as to solve the bottleneck encountered by the current advanced packaging.

The difference between fan-in wafer level package (FI-WLP, fan in wafer level package) and fan-out wafer level package (FO-WLP, fan out wafer level package) is that the solder balls of fan-in package are in the range of the chip Inside, the solder balls of the fan-out package have to go outside the range of the chip.

The fan-out wafer-level packaging process of packaging factories (and some fabs) is to pull out the required circuits from the terminal point (PAD) of the semiconductor bare die to the redistribution layer (Redistribution Layer), and then form the package. Therefore, there is no need for a packaging substrate, no wires, and no bumps, which can reduce production costs and make chips and packages thinner. In order to form the redistribution layer, the front-end process must be introduced into the packaging, which greatly improves the process capability of the packaging factory, from a few millimeters to a few microns.

Wafer-level packaging is mainly based on wafer-level processes, and the process is processed in units of one or more wafers.

The FOWLP process is divided into two categories:

Chip-first FO: Placed on a wafer-level carrier, and a known good die (KGD) picked from the original device wafer is wrapped with a molding resin into a re-constitution wafer (re-constitution). wafer), which is further processed into RDL on the wafer, ball placement, carrier removal, and singulation.

RDL-first FO: Wafer-level carriers build RDL layers and bond temporarily, place KGD on top and then mold resin, grind, remove carrier, ball, and singulate.

Under these two process architectures, various variations can also be derived according to the different needs of customers, such as die face-up bonding, die-side bonding, RDL thin line priority, RDL thick line priority type. FOWLP's RDL line width and line spacing capability can be as small as 1.5 microns.

FOWLP is more suitable for chip size less than 5mm ² . If the chip size is large, the wafer level is arc-shaped, which will waste a lot of wafer space. The solution is to use fan-out package FOPLP (fan out panel level package) to save space, increase unit output and greatly reduce cost by panel-level process.

The process capability of the panel level can be the same as that of the wafer level. If the working area of the wafer level equipment is enlarged, of course, suitable materials and process equipment must be developed together with the material and equipment manufacturers to achieve the same process capability and RDL line width. The line spacing capability can be as small as 1.5 microns.

Using newly developed materials and equipment, the RDL process line width and line spacing capability of fan-out panel level packaging can be as small as 1.5 microns, which just meets the requirements of medium density wiring (RDL line width and line spacing capability is between 10 and 1.5 microns). , so a fan-out panel-level packaging process can be used to make an interposer with medium wiring density.

The Si interposer provides high RDL wiring density, the organic dielectric layer of the fan-out panel-level packaging process provides medium-density RDL wiring, and the FCBGA substrate provides low-density wiring. If advanced packaging uses these three different wiring densities at the same time. It can provide multi-chip integration of Processor, logic and HBM in an advanced package. From 1 to 6 HBMs can be put into the package. The more the number of HBMs, the better the computing efficiency of the processor.

The solution provided by the present invention is to embed the Si interposer of high-density RDL wiring in the FCBGA substrate of low-density wiring. This work can be completed in the substrate factory. Down to the place where there is a fan-out panel-level packaging process (the ability of RDL line width and line spacing is as small as 1.5 microns), a plurality of layers of RDL (medium density wiring) organic dielectric layers are made on the surface of the substrate, with copper tin on the top. Bumps are used as electrical connections for chips to be mounted later. Finally, it is cut into single pieces and shipped to the packaging factory for the subsequent FCBGA process.

With reference to FIGS. 1-11 , a manufacturing method for manufacturing an advanced packaging structure with Si and an organic interposer layer provided in an embodiment of the present invention, the manufacturing method includes:

Step 1: Fabricate a Si interposer for high-density RDL wiring, the Si interposer 2 is provided with high-density RDL wiring, and copper bumps or copper pillars 21 (or other Equivalent metal bumps), copper bumps or copper pillars 21 are electrically connected to the high-density RDL wiring.

Step 2: Fabricate the FCBGA substrate 1 with low-density wiring, and open a cavity 13 on the upper surface of the FCBGA substrate 1 corresponding to the position of the Si interposer 2 .

Specifically, the step of making the FCBGA substrate 1 further includes:

To manufacture the core layer 11 of the substrate, a circuit formed by opening holes 111 on the core layer 11 and plating copper (or other equivalent metals) to conduct the copper foil 122 on both sides of the core layer 11, as shown in FIG. 1 ;

A plurality of build-up circuit layers 12 are laminated and stacked on both sides of the core layer 11 respectively, and the layers of build-up circuit layers 12 and the core layer 11 are filled with electroplated copper 124 (or other etc.) equivalent metal) for electrical conduction.

More specifically, the build-up wiring layer 12 adopts a lamination process (or a build-up process). Laminate the ABF (Ajinomoto Build-up Film, Ajinomoto Build-up Film) build-up film 121 or equivalent material on both sides of the core layer, expose the circuit pattern, and directly form the circuit (ie copper wire) through copper plating 122 circuit). Repeat this process for many times to stack and build up layers (layers). There are blind via holes 123 (blind via holes) between the copper wires 122 of each layer for electrical connection. The blind via holes 123 are drilled by laser, and the size is limited and too small. Holes cannot be drilled. The lamination process is repeated several times to the required number of layers, as shown in FIGS. 2 to 4 .

Step 3: Dig a cavity on the upper surface of the FCBGA substrate 1 at the position where the Si interposer 2 (with multiple layers of RDL line width and line spacing less than 1.5 microns) is to be placed, and the contacts on the upper surface of the Si interposer 2 have copper bumps or copper Pillar 21, the copper bumps or copper pillars 21 of the Si interposer 2 face upward, the bottom of the Si interposer 2 is fixed in the cavity 13, the gap between the Si interposer 2 and the cavity 13 is filled with resin 23, and then pressed together The ABF build-up film 121 covers the Si interposer 2 (with copper bumps or copper pillars 21 on the upper surface) and the copper wires 122 on the substrate 1, and a blind via hole 123 (blind via hole) is opened on the substrate 1 by a laser. The blind holes 123 are filled with electroplated copper 124 (or other equivalent metals), and the height is the same as that of the copper bumps or copper pillars 21 on the upper surface of the Si interposer 2 , as shown in FIGS. 5 to 7 .

Step 4: After the build-up process, carry out the outer layer process, clean, check the appearance and electrical characteristics, and complete the part of the FCBGA substrate 1 process.

Step 5: Send the panel of substrate 1 to the production line of fan-out panel level packaging. The surface morphology of the substrate panel made by the substrate factory is not flat, which will have a bad influence on the subsequent formation of fine lines (broken wire, short circuit) Wait). After cleaning the panel, the lower surface is glued on the glass carrier 6 with adhesive 7, and the upper surface is an ABF build-up film 121 (there are a plurality of blind holes 123 on it, and the blind holes 123 are filled with copper electroplating 124, which is suitable for the ABF. The surface of the build-up film 121 is ground by mechanical grinding or chemical mechanical polishing (CMP, chemical mechanical polish), and ground to the copper bumps or copper pillars 21 on the upper surface of the Si interposer 2 and the inside of the blind holes 123 . The copper filling and electroplating 124 is exposed and reaches the designed thickness and flatness.

Step 6: After grinding, clean the substrate 1 panel, and make multiple layers of medium density RDL wiring 32 and multiple layers of dielectric layers (polyimide or equivalent material) on a flat surface, and medium density RDL wiring 32 Blind via holes are opened in the polyimide 31 between the layers, the blind holes are opened by etching, and the electroplated buried holes are used for electrical connection between the copper wires of each layer. The closer to the medium density RDL wiring 32 of the chip, the finer the line width and line spacing, even as fine as 1.5 to 2.0 microns, so through the thickness control of the medium density RDL wiring 32 layer and the dielectric layer, the selection of dielectric layer materials, and The optimization of the process method can make the surface morphology of the dielectric layer as flat as possible, so that the copper wires of the patterned RDL can meet the requirements of thinning. As shown in Figures 8-10.

Step 7: After the last layer of medium density RDL wiring 32 and polyimide 31 is completed, open holes in polyimide 31 by exposure, development and etching. Because the holes are opened by etching, the size and spacing of the holes It can be reduced, and the tin-copper bumps 4 are formed on the contact portion of the mounted chip (bare chip). Cut the panel into multiple single FCBGA substrates, check the appearance and electrical characteristics, and ship them to the packaging factory to continue the subsequent process. The polyimide 31 is opened by etching, which has a smaller size and spacing than ABF's laser opening, so the contact distance between the chip and the Si interposer can be reduced to 35-40um (currently 55um). The size of the chip and Si interposer can be reduced accordingly. cut costs. As shown in Figure 11.

Step 8: The packaging factory flip-chips the processor 8 (processor), logic (logic), and 1 to 6 high-bandwidth memory (HBM, high bandwidth memory) chips 9 on the upper surface of the FCBGA substrate 1, and a plurality of chips 9 are on the chip 9. The tin-copper bumps are soldered to the contacts of a plurality of tin-copper bumps 4 on the upper surface of the FCBGA substrate 1 for electrical conduction. The gap between the chip 9 and the substrate 1 is underfilled 10 (underfill), and the heat sink is attached. The heat sink and the chip There is a thermal interface material (TIM, thermal interface material) on the back to assist in heat conduction. Finally, a plurality of solder balls are planted on the ball pads on the lower surface of the FCBGA substrate 1 to form the solder ball pads 5, and the heat sink is stamped to check the appearance and electrical characteristics to complete the packaging process of the FCBGA substrate, as shown in Figure 11.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "inner", "outer", etc. is based on the orientation or position shown in the accompanying drawings The relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

The terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature.

The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principle and spirit of the present invention, various changes, modifications, substitutions and alterations to these embodiments still fall within the protection scope of the present invention.

Claims (15)

1. an advanced packaging structure with Si and an organic interposer, characterized in that: a substrate comprising low-density wiring, a Si interposer for high-density RDL wiring and an organic dielectric layer for medium-density RDL wiring, the Si interposer The layer is embedded on the surface of the substrate, and the organic dielectric layer is packaged on the surface of the Si interposer and the substrate by using a fan-out panel level, and is electrically connected to the substrate and the Si interposer; The line width and line spacing of the low-density wiring is larger than the line width and line spacing of the medium density RDL wiring, and the line width and line spacing of the medium density RDL wiring is larger than the line width and line spacing of the high density RDL wiring. 2 . The advanced packaging structure with Si and organic interposer according to claim 1 , wherein the substrate is an FCBGA substrate, comprising a core layer and several layers laminated and stacked on both sides of the core layer. 3 . The build-up circuit layers are electrically connected between the build-up circuit layers and the core layers through laser openings and metal plating in the holes. 3 . The advanced packaging structure with Si and organic interposer according to claim 1 , wherein the line width and line spacing of the low-density wiring is greater than 8 μm, and the line width and line spacing of the medium-density RDL wiring is between 8 μm. 4 . From 8 μm to 1.5 μm, the line width and line spacing of the high-density RDL wiring is less than 1.5 μm. 4. The advanced packaging structure with Si and organic interposer according to claim 1, wherein the organic dielectric layer comprises alternately stacked multi-layer polyimide and multi-layer medium density RDL wiring, each The medium-density RDL wirings are electrically connected by etching the polyimide between the holes and plating metal in the holes. 5. The advanced packaging structure with Si and organic interposer as claimed in claim 1, wherein the Si interposer and the organic dielectric layer are disposed on the upper surface of the substrate, and the lower surface of the substrate A tin ball pad is provided, and a tin-copper bump is provided on the contact point on the upper surface of the organic dielectric layer. 6 . The advanced packaging structure with Si and organic interposer according to claim 1 , wherein the line width and line spacing of the medium-density RDL wiring decreases as the distance from the position where the memory chip is to be installed decreases. 7 . Small. 7 . The advanced packaging structure with Si and organic interposer according to claim 1 , wherein a cavity is formed on the upper surface of the substrate corresponding to the position of the Si interposer, and the Si interposer is connected to the Si interposer. 8 . The gaps between the cavities are filled with resin. 8 . The advanced packaging structure with Si and organic interposer according to claim 1 , wherein the surface contacts of the Si interposer are provided with metal bumps, and the Si interposer is embedded in the Si interposer. 9 . When the substrate is used, the metal protrusions and the surface contacts of the substrate are coplanar. 9 . A manufacturing method for manufacturing the advanced packaging structure with Si and an organic interposer according to any one of claims 1 to 8 , wherein the manufacturing method comprises: Si interposer for making high-density RDL wiring; making a low-density wiring substrate, and opening a cavity on the upper surface of the substrate corresponding to the position of the Si interposer; embedding the Si interposer in the cavity; Adhere the lower surface of the substrate with the Si interposer embedded on the carrier, and use the fan-out panel level packaging on the upper surface to make several layers of organic dielectric layers of medium density RDL wiring, so that the organic dielectric layers of the organic dielectric layers are RDL wiring is electrically connected to the Si interposer and the substrate; forming tin-copper bumps on the top surface of the Si interposer; Remove the carrier and cut into individual pieces. 10. The manufacturing method according to claim 9, wherein the substrate is an FCBGA substrate, and the step of fabricating the FCBGA substrate comprises: Making a core layer of a substrate, by opening holes on the core layer and plating metal to conduct circuits on both sides of the core layer; Several build-up circuit layers are laminated and stacked on both sides of the core layer, and the build-up circuit layers and the core layer are electrically connected through laser openings and metal plating in the holes. 11 . The manufacturing method according to claim 10 , wherein metal bumps are provided on the contacts on the upper surface of the Si interposer, and after the Si interposer is embedded in the cavity, the silicon interposer is placed in the cavity. 12 . Resin is filled between the Si interposer and the cavity, and the build-up circuit layer is continuously laminated on the Si interposer and the upper surface of the substrate. The height is the same as the height of the metal protrusion. 12 . The manufacturing method according to claim 11 , wherein before the organic dielectric layer is fabricated on the upper surface of the substrate by using fan-out panel level packaging, the method further comprises the steps of: 12 . Grind the build-up circuit layer on the upper surface of the substrate and the Si interposer until the metal-plated part in the laser opening between the metal bump and the build-up circuit layer is exposed, and reaches the designed thickness and flatness . 13 . The manufacturing method of claim 9 , wherein the step of fabricating the organic dielectric layer comprises: alternately stacking multiple layers of polyimide and multiple layers on the upper surface of the substrate and the Si interposer. 14 . Medium-density RDL wirings, the medium-density RDL wirings in each layer are electrically connected by etching the polyimide between the holes and plating metal in the holes. 14. The manufacturing method according to claim 13, characterized in that, after the last organic dielectric layer is fabricated, blind holes are opened in polyimide by exposure, development and etching, and the electrical properties of the medium-density RDL wiring are fabricated. Connected tin copper bumps. 15. The manufacturing method of claim 9, further comprising the steps of: Flip-chip processors, logic, and several high-bandwidth memory chips on the Si interposer on the upper surface of the single-cut substrate, and place a number of tin-copper bumps on the chip with the tin-copper on the upper surface of the Si interposer. Bump welding for electrical conduction; Underfill the gap between the chip and the Si interposer, attach a heat sink, and the heat sink and the back of the chip have thermal interface materials to assist heat conduction; Solder ball pads are formed on the lower surface of the substrate.

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