CN114743519A

CN114743519A - GOA circuit and display panel

Info

Publication number: CN114743519A
Application number: CN202210518321.5A
Authority: CN
Inventors: 赖谷皇
Original assignee: Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-05-12
Filing date: 2022-05-12
Publication date: 2022-07-12
Anticipated expiration: 2042-05-12
Also published as: CN114743519B

Abstract

The application relates to a GOA circuit and a display panel, which comprise a plurality of cascaded GOA units, wherein if the nth GOA unit is the first two GOA units, an up-down pull control module is connected with a GSP signal, an m-2 level clock signal line and a first node, otherwise, the up-down pull control module is connected with a signal output end of the n-2 level GOA unit, the m-2 level clock signal line and the first node; the pull-up and pull-down module is respectively connected with the mth level clock signal line, the first node and the second node; the capacitance module is respectively connected with the first node and the second node; the noise elimination module is respectively connected with the mth level clock signal line, the first node, the second node and the third node, and the third node is connected with the first low level signal; and if the nth grade GOA unit is the previous three grades of GOA units, the first clearing module is respectively connected with the VSS signal, the first node and the third node, otherwise, the first clearing module is respectively connected with the GSP signal, the first node and the third node. This application utilizes periodic clock signal and TFT collocation, has effectively reduced GOA circuit and has walked line quantity and circuit layout area.

Description

GOA circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

With the continuous iterative development of display technologies, a Gate On Array (GOA) is required in a panel driving architecture from a conventional liquid crystal display panel to a recently market comparable self-luminous display panel to provide gate driving signals required by the panel, so that the panel can work normally.

However, for the prior art, the NMOS process is mainly focused on the development of the GOA circuits of large-size related products, and the development of the GOA circuits of medium and small sizes is rare, so the conventional GOA circuits cannot be applied to the product specifications of narrow frames on the market.

Disclosure of Invention

Accordingly, it is necessary to provide a GOA circuit and a display panel for solving the technical problem in the prior art that the GOA circuit is too large in size and cannot be applied to narrow-frame products.

In order to achieve the above object, in one aspect, an embodiment of the present application provides a GOA circuit, where the GOA circuit includes multiple cascaded GOA units, and each GOA unit includes an up-and-down control module, an up-and-down module, a noise elimination module, a capacitor module, and a first clean module;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding pull-up and pull-down control modules are respectively connected with the GSP signal, the m-2-level clock signal line Ck (m-2) and the first node, and if the nth-level GOA unit is a GOA unit behind the previous two levels, the corresponding pull-up and pull-down control modules are respectively connected with the signal output end G (n-2) of the nth-2-level GOA unit, the m-2-level clock signal line Ck (m-2) and the first node, wherein n is a positive integer, and m is a positive integer greater than 2;

the pull-up and pull-down module is respectively connected with an m-th level clock signal line Ckm, a first node and a second node;

the capacitance module is respectively connected with the first node and the second node;

the noise elimination module is respectively connected with an m-th level clock signal line Ckm, a first node, a second node and a third node, wherein the third node is connected with a first low level signal;

if the nth grade GOA unit is a GOA unit in the previous three grades, the first clearing module is respectively connected with the VSS signal, the first node and the third node, and if the nth grade GOA unit is a GOA unit behind the previous three grades, the first clearing module is respectively connected with the GSP signal, the first node and the third node.

Optionally, if the nth-stage GOA unit is a GOA unit in the previous two stages, the first end of the first thin film transistor included in the corresponding up-down pull control module is connected to the GSP signal, and if the nth-stage GOA unit is a GOA unit after the previous two stages, the first end of the first thin film transistor included in the corresponding up-down pull control module is connected to the signal output end G (n-2) of the nth-2 th-stage GOA unit;

the grid electrode of the first thin film transistor is connected with the (m-2) th-level clock signal line Ck (m-2), and the second end of the first thin film transistor is connected with a first node;

a grid electrode of a seventh thin film transistor contained in the up-down pulling module is connected with the first node, a first end of the seventh thin film transistor is connected with the mth level clock signal line Ckm, and a second end of the seventh thin film transistor is connected with the second node;

the first end of a first capacitor contained in the capacitor module is connected with the first node, and the second end of the first capacitor is connected with the second node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the grid electrode of a sixth thin film transistor included in the first clearing module is connected with the VSS signal, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the grid electrode of the sixth thin film transistor included in the first clearing module is connected with the GSP signal;

the first end of the sixth thin film transistor is connected with the first node, and the second end of the sixth thin film transistor is connected with the third node.

Optionally, gates of a third thin film transistor and a fifth thin film transistor included in the noise elimination module are connected to the first node, a first end of the third thin film transistor is connected to the fourth node, a second end of the third thin film transistor is connected to the third node, a first end of the fifth thin film transistor is connected to the fifth node, and a second end of the fifth thin film transistor is connected to the third node;

the first end of a second capacitor contained in the noise elimination module is connected with the mth level clock signal line Ckm, and the second end is connected with the fourth node;

a grid electrode of a fourth thin film transistor contained in the noise elimination module is connected with a fourth node, a first end of the fourth thin film transistor is connected with an m-th level clock signal line Ckm, and a second end of the fourth thin film transistor is connected with a fifth node;

the gate of the eighth thin film transistor included in the noise elimination module is connected to the fifth node, the first end is connected to the second node, and the second end is connected to the third node.

Optionally, each GOA unit further includes at least one of a second purge module, a third purge module, a fourth purge module, and a fifth purge module;

the second clearing module is used for clearing the voltage of the first node under the control of the first clearing signal;

the third clearing module is used for clearing the voltage of the fifth node under the control of the second clearing signal;

the fourth clearing module is used for clearing the voltage of the second node under the control of the third clearing signal;

the fifth clearing module is used for clearing the voltage of the fourth node under the control of the fourth clearing signal.

Optionally, the second clearing module includes a ninth thin film transistor;

the ninth thin film transistor is connected with the first clearing signal line at the grid electrode, the first end is connected with the first node, and the second end is connected with the second low-level signal.

Optionally, the third cleaning module includes a tenth thin film transistor;

the tenth thin film transistor has a gate connected to the second clear signal line, a first end connected to the fifth node, and a second end connected to the third low level signal.

Optionally, the fourth cleaning module includes an eleventh thin film transistor;

the gate of the eleventh thin film transistor is connected to the third clear signal line, the first end of the eleventh thin film transistor is connected to the second node, and the second end of the eleventh thin film transistor is connected to the fourth low-level signal.

Optionally, the fifth cleaning module includes a twelfth thin film transistor;

the grid electrode of the twelfth thin film transistor is connected with the fourth clearing signal line, the first end of the twelfth thin film transistor is connected with the fourth node, and the second end of the twelfth thin film transistor is connected with the fifth low-level signal.

Optionally, the number of the clock signals included in one action period corresponds to the duty ratio of the clock signals, the clock signals included in one action period are sequentially effective in a time-sharing manner in the action period of the GOA circuit, and the pulse widths of the high-level signals in the same clock signal are all shorter than the pulse width of the low-level signal.

Optionally, if the number of the clock signals included in one action period is 6, the duty ratio of the clock signals is 50%;

if the number of clock signals included in one active period is 4, the duty ratio of the clock signal is 40% or 60%.

In order to achieve the above object, in another aspect, an embodiment of the present application further provides a display panel, where the display panel includes a display module and a GOA circuit in any one of the foregoing embodiments;

the GOA circuit is electrically connected with the display module and used for driving the display module to emit light.

One of the above technical solutions has the following advantages and beneficial effects:

according to the method and the device, the GSP signal during starting is utilized to effectively control the first clearing module to clear the voltage of the first node, so that the defects during initial driving of the GOA are reduced, and the risk of abnormal starting lighting pictures is reduced. The periodic clock signal and the output signal of the previous stage are used for controlling the pull-up and pull-down control module to charge the capacitor of the first node, the periodic clock signal and the voltage of the first node are used for controlling the pull-up and pull-down module to be turned on or turned off, and the output Gout of the GOA is synchronously made to be high potential when the periodic clock signal is changed into the high potential, so that the corresponding PixelTFT is effectively turned on. The noise elimination module is used to keep the output voltage Gout of the GOA at a low level so that the corresponding PixelTFT can be effectively turned off. According to the GOA circuit, the wiring quantity and the circuit layout area in the GOA circuit are effectively reduced by utilizing the collocation of the periodic clock signals and the TFTs. The GOA circuit is suitable for the panel requirement of the narrow frame.

Drawings

Fig. 1 is a block diagram of a GOA unit according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a prior art panel circuit;

fig. 3 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure;

fig. 4 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure;

fig. 5 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure;

FIG. 6 is a waveform diagram of a plurality of signals according to an embodiment of the present application;

FIG. 7 is a waveform diagram of a multi-channel signal in another embodiment of the present application;

FIG. 8 is a waveform diagram of clock signals and node voltages according to an embodiment of the present application.

Wherein the reference numerals are as follows:

the circuit comprises an up-down pull control module 100, an up-down pull module 200, a noise elimination module 300, a capacitor module 400 and a first clearing module 500.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element and be integral therewith, or intervening elements may also be present. The terms "mounted," "one end," "the other end," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Fig. 1 is a block diagram of a GOA unit according to an embodiment of the present disclosure, and referring to fig. 1, the GOA circuit includes a plurality of cascaded GOA units, each of which includes an up-down pull control module 100, an up-down pull module 200, a noise elimination module 300, a capacitance module 400, and a first clearing module 500;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding pull-up and pull-down control module 100 is respectively connected to the GSP signal, the m-2-level clock signal line Ck (m-2) and the first node, and if the nth-level GOA unit is a GOA unit after the previous two levels, the corresponding pull-up and pull-down control module 100 is respectively connected to the signal output terminal G (n-2) of the nth-2-level GOA unit, the m-2-level clock signal line Ck (m-2) and the first node, where n is a positive integer and m is a positive integer greater than 2;

the upper pull-down module 200 is respectively connected with the mth level clock signal line Ckm, the first node and the second node;

the capacitor module 400 is respectively connected with a first node and a second node;

the noise elimination module 300 is respectively connected with an m-th level clock signal line Ckm, a first node, a second node and a third node, wherein the third node is connected with a first low level signal;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module 500 is connected to the VSS signal, the first node, and the third node, respectively, and if the nth-level GOA unit is a GOA unit in the next three levels, the first clearing module 500 is connected to the GSP signal, the first node, and the third node, respectively.

Specifically, fig. 2 is a schematic diagram of a prior art panel circuit; referring to fig. 2, the panel circuit includes a GOA circuit and a SourceIC and a Pixel tft corresponding to each Pixel. The GOA circuit comprises a plurality of cascaded GOA units (G1, G2, G3 … Gn-1 and Gn). Each GOA cell is used to drive a row of pixeltfts. The Source IC includes a plurality of Source cells (S1, S2, S3 … Sn-1 and Sn). Each Source cell is used to provide power to the pixeltfts of a column.

From the imaging principle of the liquid crystal panel, the operation of the liquid crystal panel is commonly controlled by the gate and source voltages. The gate voltage is responsible for turning on and off the TFT transistor below a specific pixel point, thereby affecting the on and off of the pixel point. And then, the source voltage charges a liquid crystal area where the pixel point is located, the rotation angle of liquid crystal molecules is influenced, and the gray level of the pixel point is further influenced.

The main functional module of the Gate On Array (GOA) is to design an S/R circuit by using the TFT process of the panel, so that the panel can provide the capability of scanning sequentially. The Pixel TFT uses the signal provided by GOA circuit and Source IC to make the corresponding Sub Pixel possess correct voltage, and then drives LC inversion to generate color picture acceptable to human eye.

The pull-up and pull-down control module 100 is controlled by the m-2 th clock signal line Ck (m-2) to turn on or off, and the GSP signal or the output signal of the signal output terminal G (n-2) of the n-2 th GOA unit is used to control the capacitor module 400 at the first node to be charged and drive the pull-up and pull-down module 200 to be turned on. When the pull-up module 200 is turned on, if the clock signal output from the m-th level clock signal line Ckm changes from low level to high level, the output Gout of the n-th level GOA unit also changes to high level synchronously and is input to the panel AA area, so as to drive the corresponding Pixel tft (thin film transistor corresponding to the Pixel) to turn on, and enable the Pixel to charge the correct Source voltage.

After the PixelTFT in the AA area receives the Source signal, the output Gout of the n-level GOA unit needs to be synchronously changed into low level, so that the PixelTFT can be effectively closed, and the related Source voltage can be effectively locked by driving. Therefore, the voltage at the first node keeps high, driving the pull-up/pull-down module 200 to pull down the output voltage of Gout.

After the nth GOA unit is finished, the noise elimination module 300 in this embodiment is used to keep the low level of Gout for the rest of the time to continuously input the low level Gout to the PixelTFT.

In addition, in order to reduce the driving defects during the startup, the present embodiment effectively drives the first clearing module 500 by using the GSP signal to clear the first node voltage, so as to reduce the risk of abnormal lighting pictures caused by the defects during the initial driving of the GOA.

The present embodiment utilizes the GSP signal during the startup to effectively control the first clearing module 500 to clear the voltage of the first node, so as to reduce the defects during the initial driving of the GOA and reduce the risk of abnormal startup lighting pictures. The upper and lower pull-up control module 100 is controlled by the periodic clock signal and the output signal of the previous stage to charge the capacitor module 400 of the first node, the upper and lower pull-up module 200 is controlled to be turned on or off by the periodic clock signal and the voltage of the first node, and the output Gout of the GOA is synchronously made to be a high potential when the periodic clock signal is changed to be the high potential, so that the corresponding PixelTFT is effectively turned on. The noise elimination module 300 is used to keep the output voltage Gout of the GOA low so that the corresponding PixelTFT can be effectively turned off. According to the GOA circuit, the wiring quantity and the circuit layout area in the GOA circuit are effectively reduced by utilizing the collocation of the periodic clock signals and the TFTs. The GOA circuit is suitable for the panel requirement of the narrow frame.

In one embodiment, if the GOA cell of the nth level is the GOA cell of the first two levels, the first terminal of the first thin film transistor T1 included in the corresponding pull-up and pull-down control module 100 is connected to the GSP signal, and if the GOA cell of the nth level is the GOA cell of the second two levels, the first terminal of the first thin film transistor T1 included in the corresponding pull-up and pull-down control module 100 is connected to the signal output terminal G (n-2) of the GOA cell of the nth-2 level;

a gate of the first thin film transistor T1 is connected to the m-2 th stage clock signal line Ck (m-2), and a second end thereof is connected to the first node;

a gate of a seventh thin film transistor T7 included in the up-down pull module 200 is connected to the first node, a first end is connected to the mth stage clock signal line Ckm, and a second end is connected to the second node;

a first end of a first capacitor C1 included in the capacitor module 400 is connected to the first node, and a second end is connected to the second node;

if the nth GOA cell is the GOA cell in the previous three levels, the gate of the sixth tft T6 included in the first erase module 500 is connected to the VSS signal, and if the nth GOA cell is the GOA cell in the next three levels, the gate of the sixth tft T6 included in the first erase module 500 is connected to the GSP signal;

the sixth thin film transistor T6 has a first terminal connected to the first node and a second terminal connected to the third node.

Specifically, the pull-up and pull-down control module 100 includes a first thin film transistor T1. The pull-up/down module 200 includes a seventh tft T7, the first clearing module 500 includes a sixth tft T6, and the capacitor module 400 includes a first capacitor C1.

The first thin film transistor T1, the seventh thin film transistor T7, and the sixth thin film transistor T6 of this embodiment are all thin film transistors tft (thinfilm transistor).

The first node is a common node of the second terminal of the first thin film transistor T1, the gate of the seventh thin film transistor T7, the first terminal of the sixth thin film transistor T6, and the first terminal of the first capacitor C1.

The second node is a common node of the second terminal of the first capacitor C1, the second terminal of the seventh tft T7, and the noise elimination module 300.

The third node is a common node of the second terminal of the sixth thin film transistor T6 and the noise sorting module.

The first thin film transistor T1 is driven by the clock signal of the m-2 th stage clock signal line Ck (m-2), and when the first thin film transistor T1 is turned on, the first terminal of the first thin film transistor T1 charges the first node through the first thin film transistor T1, which drives the seventh thin film transistor T7 to be turned on.

In the case where the seventh thin film transistor T7 is turned on, if the voltage of the clock signal of the mth stage clock signal line Ckm is changed from the low potential to the high potential, the second terminal of the seventh thin film transistor T7, i.e., the output terminal Gout, is synchronously changed to the high potential. Gout is input to an AA area in the panel to drive the corresponding Pixel TFT to be opened, so that the Pixel is charged with correct Source voltage.

Since the first node is kept at the high potential by the first capacitor, the output of the second terminal Gout of the seventh thin film transistor T7 in the pull-up and pull-down module 200 can be driven to the low potential, so as to effectively pull down the Gout potential.

Since Gout is connected to the first low level signal through the noise elimination module 300, the noise elimination module 300 can continuously pull down the potential of Gout at other times after the GOA unit finishes working, so that Gout is effectively kept at a low potential.

In one embodiment, the noise elimination module 300 includes a third thin film transistor and a fifth thin film transistor having gates connected to the first node, a first end connected to the fourth node, a second end connected to the third node, a first end connected to the fifth node, and a second end connected to the third node;

the noise elimination module 300 includes a second capacitor having a first end connected to the mth clock signal line Ckm and a second end connected to the fourth node;

a gate of a fourth thin film transistor included in the noise elimination module 300 is connected to the fourth node, a first end of the fourth thin film transistor is connected to the mth-level clock signal line Ckm, and a second end of the fourth thin film transistor is connected to the fifth node;

the gate of the eighth tft included in the noise elimination module 300 is connected to the fifth node, the first end is connected to the second node, and the second end is connected to the third node.

Fig. 3 is a circuit diagram of a GOA unit according to an embodiment of the present disclosure; specifically, as shown in fig. 3, the noise elimination module 300 includes a third tft T3, a fourth tft T4, a fifth tft T5, an eighth tft T8 and a second capacitor C2.

The third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the eighth thin film transistor T8 are all thin film transistors tft (thinfilm transistor).

The fourth node is a common node of the second terminal of the second capacitor, the first terminal of the third thin film transistor T3, and the gate of the fourth thin film transistor T4.

The fifth node is a common node of the second terminal of the fourth thin film transistor T4, the first terminal of the fifth thin film transistor T5, and the gate of the eighth thin film transistor T8.

After the GOA unit finishes working, the low potential is continuously input to the Pixel TFT in the rest time, so the circuit uses the noise elimination module 300 to continuously maintain the low potential of Gout. At this time, the working principle mainly utilizes the periodic clock signal and the coupling capacitor to drive the fourth thin film transistor T4 to generate the switching signal, which can effectively transmit the clock signal of the mth clock signal line Ckm to the fifth node, and at the same time, because the fifth node discharge path is only provided with the fifth thin film transistor T5, except that the first node is pulled to the low potential when the GOA unit normally works, the fifth node is pulled to the high potential, and the high potential can be effectively maintained in the rest time, so the Gout potential can be continuously pulled down through the eighth thin film transistor T8, and at the same time, the first node can also be continuously kept at the low potential through the first thin film transistor T1 and the eighth thin film transistor T8.

The number of GOA TFTs and the number of Busline are reduced by the combination of the TFT functional modules, and the layout space of the GOA circuit is effectively reduced. The noise elimination circuit is designed by using the periodic clock signal CK and the capacitive coupling effect, so that the TFT Stress can be effectively reduced, and the reliability of the panel can be increased.

In one embodiment, each GOA unit further comprises at least one of a second purge module, a third purge module, a fourth purge module, and a fifth purge module;

In particular, the number and the type of the purge modules included in each GOA unit are not all the same, i.e. the number and the type of the purge modules included are not necessarily all the same. For example, some GOA units include one or two or three or four of the second, third, fourth, and fifth purge modules. It is possible that some GOA units contain the same number and kind of flush modules. The number and types of the purge modules included in each GOA unit are not limited by the present application.

In one embodiment, each GOA unit further comprises at least one of a second purge module, a fourth purge module;

the fourth clearing module is used for clearing the voltage of the second node under the control of the third clearing signal.

In one embodiment, the second cleaning module includes a ninth thin film transistor;

Specifically, the ninth thin film transistor T9 is a thin film transistor tft (thinfilm transistor).

In one embodiment, the third cleaning module includes a tenth thin film transistor;

the tenth thin film transistor has a gate connected to the second clear signal line, a first end connected to the fifth node, and a second end connected to the third low-level signal.

Specifically, the tenth thin film transistor T10 is a thin film transistor tft (thinfilm transistor).

In one embodiment, the fourth cleaning module includes an eleventh thin film transistor;

Specifically, the eleventh thin film transistor T11 is a thin film transistor tft (thinfilm transistor).

In one embodiment, the fifth cleaning module comprises a twelfth thin film transistor;

Specifically, the twelfth thin film transistor T12 is a thin film transistor tft (thinfilm transistor).

In a specific embodiment, the first low level signal, the second low level signal, the third low level signal, the fourth low level signal and the fifth low level signal are all the same low level signal.

Of course, some of the first low-level signal, the second low-level signal, the third low-level signal, the fourth low-level signal, and the fifth low-level signal may be the same low-level signal, and some of the low-level signals may be another low-level signal, which is not limited in this application.

In one embodiment, the first clear signal corresponding to the first clear signal line, the second clear signal corresponding to the second clear signal line, the third clear signal corresponding to the third clear signal line, and the fourth clear signal corresponding to the fourth clear signal line are all the same clear signal. That is, the first clear signal line, the second clear signal line, the third clear signal line, and the fourth clear signal line are the same clear signal line.

The thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. The first end of the same thin film transistor is a drain electrode, the second end is a source electrode, and the first end is a source electrode, and the second end is a drain electrode. The first terminal and the second terminal are determined as a drain or a source, depending on the type of the thin film transistor and the circuit connection condition.

Fig. 4 is a circuit diagram of a GOA unit in accordance with another embodiment of the present disclosure; referring to fig. 4, the GOA unit includes a second purge module, a third purge module, and a fourth purge module. And, the first low level signal, the second low level signal, the third low level signal, and the fourth low level signal are all the same low level signal VGL.

Fig. 5 is a circuit diagram of a GOA unit according to another embodiment of the present disclosure; referring to fig. 5, the GOA unit includes a second purge module, a third purge module, a fourth purge module, and a fifth purge module. And the first low level signal, the second low level signal, the third low level signal, the fourth low level signal and the fifth low level signal are all the same low level signal VGL.

Through increasing the clear away circuit, can effectively reduce the effect of GOA residual charge to circuit functionality, effectively reduced the bad risk of GOA lighting a lamp.

In one embodiment, the number of the clock signals included in one active period corresponds to the duty ratio of the clock signals, the clock signals included in one active period are sequentially effective in a time-sharing manner in the active period of the GOA circuit, and the pulse widths of the high-level signals in the same clock signal are all shorter than those of the low-level signals.

Specifically, the clock signal of the present application is a periodic clock signal. The clock signals are provided by corresponding clock signal lines. The clock signal included in one active period is sequentially time-shared and active in the active period. For example, if an active period contains 6 clock signals, then the 6 clock signals are active at different times during the active period. These 6 clock signals are still time-shared in the next active cycle.

An m-2 th-level clock signal line Ck (m-2) and an m-level clock signal line Ckm are connected to the nth-level GOA unit, and thus, two clock signals are provided to the GOA unit, and the two clock signals are separated by 2 levels. The 2 clock signals may be clock signals of the same action period or clock signals of adjacent action periods.

For example, if an active cycle includes 6 clock signals, if the clock signal provided by the m-2 th stage clock signal line Ck (m-2) is the 6 th clock signal of a certain active cycle, the clock signal provided by the m-th stage clock signal line Ckm is the 2 nd clock signal of the next active cycle.

In addition, one clock signal includes a high level signal and a low level signal. The waveforms of the high level signal and the low level signal of different clock signals are different.

In one embodiment, if the number of clock signals included in one active period is 6, the duty ratio of the clock signals is 50%;

Specifically, the same function can be achieved as long as the corresponding duty ratio (duty) is satisfied, regardless of how many clock signals are set for one duty cycle. Therefore, the number of the clock signal lines is not limited in the present application.

FIG. 6 is a waveform diagram of a plurality of signals according to an embodiment of the present application; referring to fig. 6, the multiplex signals include a GSP signal, 6 clock signals Ck1-Ck6 included in one active period, a clear signal CLR, and a low level signal VGL. And all low level signals are the same low level signal VGL. And a first clear signal corresponding to the first clear signal line, a second clear signal corresponding to the second clear signal line, a third clear signal corresponding to the third clear signal line, and a fourth clear signal corresponding to the fourth clear signal line are all the same clear signal CLR.

The first-level clock signal line provides clock signals for GOA units which are 6 levels away, such as the 5 th-level GOA unit, the 11 th-level GOA unit, the 17 th-level GOA unit …, the 2159 th-level GOA unit and the like.

The second level clock signal line provides clock signals for the 6 th level GOA unit, the 12 th level GOA unit, the 18 th level GOA unit …, the 2160 th level GOA unit, and so on, which are 6 levels apart.

The third level clock signal line provides clock signals for the GOA units 6 levels away, such as the 1 st level GOA unit, the 7 th level GOA unit, the 13 th level GOA unit, the 19 th level GOA unit …, and the 2161 th level GOA unit.

The fourth-level clock signal line supplies clock signals to the GOA units 6 levels away, such as the 2 nd, 8 th, 14 th, 20 th, and 2162 nd GOA units ….

The fifth level clock signal line provides clock signals for the GOA units 6 levels away, such as the 3 rd level GOA unit, the 9 th level GOA unit, the 15 th level GOA unit, the 21 st level GOA unit …, the 2163 rd level GOA unit, etc.

The sixth-level clock signal line supplies clock signals to GOA units 6 levels away, such as the 4 th-level GOA unit, the 10 th-level GOA unit, the 16 th-level GOA unit, and the 22 nd-level GOA unit …, the 2164 th-level GOA unit.

FIG. 7 is a waveform diagram of a plurality of signals according to another embodiment of the present application; referring to fig. 7, the multiplex signals include a GSP signal, 4 clock signals Ck1-Ck4 included in one active period, a clear signal CLR, and a low level signal VGL. And all low level signals are the same low level signal VGL. And a first clear signal corresponding to the first clear signal line, a second clear signal corresponding to the second clear signal line, a third clear signal corresponding to the third clear signal line, and a fourth clear signal corresponding to the fourth clear signal line are all the same clear signal CLR.

The first-level clock signal line provides clock signals for GOA units which are 4 levels away, such as the 3 rd-level GOA unit, the 7 th-level GOA unit, the 11 th-level GOA unit …, the 2159 th-level GOA unit and the like.

The second level clock signal line provides clock signals for GOA units 4 level apart, such as the 4 th level GOA unit, the 8 th level GOA unit, the 12 th level GOA unit …, the 2160 th level GOA unit, and so on.

The third level clock signal line provides clock signals for the GOA units 4 levels apart, such as the 1 st level GOA unit, the 5 th level GOA unit, the 9 th level GOA unit, and the 13 th level GOA unit …, the 2161 st level GOA unit.

The fourth-level clock signal line supplies clock signals to the GOA units 4 levels away, such as the 2 nd, 6 th, 10 th, 14 th, and 2162 nd GOA units ….

FIG. 8 is a waveform diagram of clock signals and node voltages according to an embodiment of the present application; referring to fig. 8, fig. 8 shows a waveform diagram of 6 clock signals Ck1-Ck6, a waveform diagram of voltage changes at the first node q (n) and the fifth node p (n), and a waveform diagram of G1, which are included in one active cycle.

The application also provides a display panel, which comprises a display module and the GOA circuit of any one of the display module and the GOA circuit; the GOA circuit is electrically connected with the display module and used for driving the display module to emit light. The display module comprises Pixel pixels corresponding to each Pixel TFT.

The GOA circuits designed by the prior art are all required by large-size panels, so that the GOA circuits have more TFTs, the common circuits all need 18 to 20 TFTs, and the unipolar GOA circuits have more TFTs, so that the circuit design layout space is larger, and the requirements of small and medium-sized narrow frames cannot be met. The GOA circuit successfully and effectively reduces the number of Busline wires and the number of TFTs (thin film transistors) by utilizing the collocation of the periodic CLK clock signal and the TFT device required by the original design and reducing two DC signal lines (LC1 and LC2) and one VSS signal line, thereby successfully achieving the purpose of reducing the circuit layout area and being suitable for narrow-frame panels.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. The GOA circuit is characterized by comprising a plurality of cascaded GOA units, wherein each GOA unit comprises an upper pull-down control module, a lower pull-up module, a noise elimination module, a capacitance module and a first clearing module;

if the nth-level GOA unit is a GOA unit in the previous two levels, the corresponding pull-up and pull-down control modules are respectively connected with a GSP signal, an m-2-level clock signal line Ck (m-2) and a first node, and if the nth-level GOA unit is a GOA unit behind the previous two levels, the corresponding pull-up and pull-down control modules are respectively connected with a signal output end G (n-2) of the nth-2-level GOA unit, an m-2-level clock signal line Ck (m-2) and the first node, wherein n is a positive integer, and m is a positive integer greater than 2;

the up-down drawing module is respectively connected with an m-th level clock signal line Ckm, the first node and the second node;

the noise elimination module is respectively connected with the mth level clock signal line Ckm, the first node, the second node and a third node, wherein the third node is connected with a first low level signal;

if the nth-level GOA unit is a GOA unit in the previous three levels, the first clearing module is respectively connected with the VSS signal, the first node and the third node, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the first clearing module is respectively connected with the GSP signal, the first node and the third node.

2. The GOA circuit of claim 1,

if the n-th-level GOA unit is a GOA unit in the previous two levels, a first end of a first thin film transistor included in the corresponding upper and lower pull-down control module is connected with a GSP signal, and if the n-th-level GOA unit is a GOA unit after the previous two levels, a first end of a first thin film transistor included in the corresponding upper and lower pull-down control module is connected with a signal output end G (n-2) of an n-2-level GOA unit;

the grid electrode of the first thin film transistor is connected with an m-2 level clock signal line Ck (m-2), and the second end of the first thin film transistor is connected with the first node;

a grid electrode of a seventh thin film transistor contained in the upper pull-down module is connected with the first node, a first end of the seventh thin film transistor is connected with the mth level clock signal line Ckm, and a second end of the seventh thin film transistor is connected with the second node;

a first end of a first capacitor contained in the capacitor module is connected with the first node, and a second end of the first capacitor is connected with the second node;

if the nth-level GOA unit is a GOA unit in the previous three levels, the grid electrode of a sixth thin film transistor included in the first clearing module is connected with a VSS signal, and if the nth-level GOA unit is a GOA unit behind the previous three levels, the grid electrode of the sixth thin film transistor included in the first clearing module is connected with the GSP signal;

and the first end of the sixth thin film transistor is connected with the first node, and the second end of the sixth thin film transistor is connected with the third node.

3. GOA circuit according to claim 1 or 2,

the noise elimination module comprises a first node, a second node, a third node, a fourth node, a second node, a third node, a fourth node, a fifth node, a fourth node, a fifth node, a fourth node, a fifth node, a fourth node, a fifth node, a fourth node, a fifth node, a fourth node;

a first end of a second capacitor included in the noise elimination module is connected with the m-th level clock signal line Ckm, and a second end of the second capacitor is connected with the fourth node;

a gate of a fourth thin film transistor included in the noise elimination module is connected with the fourth node, a first end of the fourth thin film transistor is connected with the mth-level clock signal line Ckm, and a second end of the fourth thin film transistor is connected with the fifth node;

the gate of the eighth thin film transistor included in the noise elimination module is connected to the fifth node, the first end of the eighth thin film transistor is connected to the second node, and the second end of the eighth thin film transistor is connected to the third node.

4. The GOA circuit of claim 3, wherein each GOA unit further comprises at least one of a second purge module, a third purge module, a fourth purge module, and a fifth purge module;

the second clearing module is used for clearing the voltage of the first node under the control of a first clearing signal;

the third clearing module is used for clearing the voltage of the fifth node under the control of a second clearing signal;

the fourth clearing module is used for clearing the voltage of the second node under the control of a third clearing signal;

the fifth clearing module is configured to clear the voltage of the fourth node under control of a fourth clear signal.

5. The GOA circuit of claim 4, wherein the second clear module comprises a ninth thin film transistor;

and the grid electrode of the ninth thin film transistor is connected with a first clearing signal line, the first end of the ninth thin film transistor is connected with the first node, and the second end of the ninth thin film transistor is connected with a second low-level signal.

6. The GOA circuit of claim 4, wherein the third cleaning module comprises a tenth thin film transistor;

and the grid electrode of the tenth thin film transistor is connected with the second clearing signal line, the first end of the tenth thin film transistor is connected with the fifth node, and the second end of the tenth thin film transistor is connected with the third low-level signal.

7. The GOA circuit of claim 4, wherein the fourth cleaning module comprises an eleventh thin film transistor;

and the grid electrode of the eleventh thin film transistor is connected with a third clearing signal line, the first end of the eleventh thin film transistor is connected with the second node, and the second end of the eleventh thin film transistor is connected with a fourth low-level signal.

8. The GOA circuit of claim 4, wherein the fifth clear module comprises a twelfth thin film transistor;

and the grid electrode of the twelfth thin film transistor is connected with a fourth clearing signal wire, the first end of the twelfth thin film transistor is connected with the fourth node, and the second end of the twelfth thin film transistor is connected with a fifth low-level signal.

9. The GOA circuit of claim 1, wherein the number of clock signals included in an active period corresponds to a duty cycle of the clock signals, and the clock signals included in an active period are sequentially time-shared and active in the active period of the GOA circuit, and the pulse widths of the high level signals are all shorter than those of the low level signals in the same clock signal.

10. A display panel, comprising a display module and the GOA circuit of any one of claims 1 to 9;