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CN114725118A - Preparation method of semiconductor device and semiconductor device - Google Patents

Preparation method of semiconductor device and semiconductor device Download PDF

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Publication number
CN114725118A
CN114725118A CN202210325853.7A CN202210325853A CN114725118A CN 114725118 A CN114725118 A CN 114725118A CN 202210325853 A CN202210325853 A CN 202210325853A CN 114725118 A CN114725118 A CN 114725118A
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CN
China
Prior art keywords
layer
stacked
connection region
semiconductor device
substrate
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Pending
Application number
CN202210325853.7A
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Chinese (zh)
Inventor
张鹏飞
陈金星
李贝贝
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202210325853.7A priority Critical patent/CN114725118A/en
Publication of CN114725118A publication Critical patent/CN114725118A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device, including forming a first stacked layer on a substrate, the first stacked layer including first connection region stacked layers located at both ends of the first stacked layer, and second connection region stacked layers located between the first connection region stacked layers. And then forming a protective layer covering the first connecting area stacking layer and the second connecting area stacking layer, and finally etching the first stacking layer uncovered by the protective layer. The width of the first connection area stacked layer in the second direction is larger than that of the second connection area stacked layer in the second direction, so that a protective layer on the first connection area stacked layer and the second connection area stacked layer near the first connection area stacked layer is not thin, the protective layer on the first connection area stacked layer and the second connection area stacked layer near the first connection area stacked layer can be reduced from being laterally drawn, and the protective layer can effectively protect the first connection area stacked layer and the second connection area stacked layer.

Description

Preparation method of semiconductor device and semiconductor device
Technical Field
The present disclosure relates generally to electronic devices, and more particularly, to a method of manufacturing a semiconductor device and a semiconductor device.
Background
The three-dimensional memory has low power consumption, light weight and belongs to a nonvolatile memory product with excellent performance, so that the three-dimensional memory is more and more widely applied to electronic products. But at the same time, the expectation and the demand of users for three-dimensional memories are also higher and higher. With the increase in the number of layers, semiconductor processing and manufacturing techniques become challenging.
Disclosure of Invention
The present disclosure is directed to a method for manufacturing a semiconductor device and a semiconductor device, which aim to effectively protect a connection structure by increasing the width of a first connection region stack layer.
In one aspect, the present disclosure provides a method for manufacturing a semiconductor device, including:
providing a substrate;
forming a first stacked layer on the substrate, the first stacked layer including first connection region stacked layers located at both ends of the first stacked layer in a second direction and a second connection region stacked layer located between the first connection region stacked layers, wherein a width of the first connection region stacked layer in the second direction is larger than a width of the second connection region stacked layer in the second direction;
forming a protective layer covering the first connection region stack layer and the second connection region stack layer;
and forming a connecting structure positioned below the protective layer.
Further preferably, the first stacked layer further includes a step region stacked layer, and the step region stacked layer and the second connection region stacked layer are alternately arranged in the second direction.
Further preferably, before the step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer, the preparation method further includes:
forming a shielding layer on the first connection region stack layer;
forming a mask layer on the second connection region stack layer;
etching the stepped region stacked layer based on the mask layer and the shielding layer to form a stepped structure in the stepped region stacked layer;
and removing the shielding layer and the mask layer.
Further preferably, the step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer includes:
forming a photoresist layer on the first stack layer;
and exposing and developing the photoresist to form a patterned photoresist layer, wherein the patterned photoresist layer is positioned on the first connecting area stacking layer and the second connecting area stacking layer and serves as the protective layer.
Further preferably, the step of forming the connection structure under the protection layer includes:
and continuously etching the stepped structure downwards, wherein the protective layer protects the first connecting area stacking layer and the second connecting area stacking layer from being etched to form the connecting structure.
Further preferably, the preparation method further comprises:
in the step of forming the first stacked layer, forming a second stacked layer disposed adjacent to the first stacked layer in a first direction on the substrate, the first direction being perpendicular to the second direction;
forming a memory structure through the second stacked layers in a third direction perpendicular to the substrate.
Further preferably, the step of forming, on the substrate, a second stack layer disposed adjacent to the first stack layer in the first direction in the step of forming the first stack layer includes:
alternately stacking layers of conductive material and layers of dielectric material in a third direction perpendicular to the substrate.
In another aspect, the present disclosure provides a semiconductor device comprising:
a substrate;
a first stack layer on the substrate;
wherein the first stacked layer includes first connection structures located at both ends of the first stacked layer in the second direction, and a plurality of second connection structures located between the first connection structures; the width of the first connecting structure in the second direction is greater than the width of the second connecting structure in the second direction.
Further preferably, the first stacked layer further includes a plurality of step structures, and the step structures and the second connecting structures are alternately arranged in the second direction.
Further preferably, the semiconductor device further includes: and a second stacked layer on the substrate and disposed adjacent to the first stacked layer in a first direction, the first direction being perpendicular to the second direction.
Further preferably, the first stacked layer and the second stacked layer respectively include dielectric material layers and conductive material layers that are alternately stacked in a third direction perpendicular to the substrate.
Further preferably, the semiconductor device further includes: a memory structure extending through the second stacked layers in a third direction perpendicular to the substrate.
The beneficial effects of this disclosure can include: a method for manufacturing a semiconductor device and a semiconductor device are provided, which include forming a stacked structure on a substrate, wherein the stacked structure includes a first stacked layer and a second stacked layer arranged adjacent to the first stacked layer in a first direction, and the first stacked layer includes first connection region stacked layers respectively located at two ends of the first stacked layer in a second direction and second connection region stacked layers located between the first connection region stacked layers. And then forming a protective layer covering the first connecting area stacking layer and the second connecting area stacking layer, and finally etching the first stacking layer uncovered by the protective layer. The width of the first connection area stacked layer in the second direction is greater than the width of the second connection area stacked layer in the second direction, so that the protective layer on the first connection area stacked layer and the second connection area stacked layer near the first connection area stacked layer is not thin, the protective layer on the first connection area stacked layer and the second connection area stacked layer near the first connection area stacked layer can be reduced from being undercut, and the protective layer can effectively protect the first connection area stacked layer and the second connection area stacked layer.
Drawings
The technical solutions and other advantages of the present disclosure will become apparent from the following detailed description of specific embodiments of the present disclosure, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic flow chart diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;
fig. 2a is a schematic cross-sectional structure diagram of a stack layer formed in a manufacturing process of a semiconductor device provided by an embodiment of the disclosure;
fig. 2b is a schematic top view of a stacked layer formed during a semiconductor device manufacturing process according to an embodiment of the disclosure;
fig. 2c is an enlarged structural schematic diagram of the first stacked layer in fig. 2b provided by the embodiment of the present disclosure;
FIG. 3a is a schematic diagram illustrating a top view of a first stack layer in a process of forming a step structure according to an embodiment of the disclosure;
FIG. 3b is a schematic diagram of a YZ cross-sectional structure of the stacked layers along the step region in FIG. 3a after forming the step structure provided by the embodiment of the disclosure;
FIG. 3c is a schematic cross-sectional view at B-B1 in FIG. 3B according to an embodiment of the present disclosure;
FIGS. 4a-4b are schematic cross-sectional views illustrating a protective layer formation process according to an embodiment of the disclosure;
FIG. 5a is a schematic cross-sectional view of a connection structure formed in accordance with an embodiment of the present disclosure;
fig. 5b is a schematic cross-sectional view at C-C1 in fig. 5a according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely a subset of the disclosed embodiments and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).
As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.
It should be noted that the drawings provided in the embodiments of the present disclosure are only for illustrating the basic idea of the present disclosure, and although the drawings only show the components related to the present disclosure and are not drawn according to the number, shape and size of the components in actual implementation, the type, amount and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
One memory plane of the 3D NAND may generally include two memories (GB) and a staircase region between the two memory regions, the staircase region including a plurality of staircase structures spaced apart to draw word line contacts from the staircase, so that the conductive material layers of the two memory regions may be connected to the word lines through the staircase structure. The step region further comprises a connecting structure positioned between two adjacent step structures.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The preparation method includes the following steps S1-S5.
Referring to steps S1-S2 in fig. 1 and fig. 2a-2b, fig. 2a is a schematic cross-sectional structure of a stack layer formed in a manufacturing process of a semiconductor device according to an embodiment of the present disclosure, and fig. 2b is a schematic top-view structure of a stack layer formed in a manufacturing process of a semiconductor device according to an embodiment of the present disclosure.
Step S1: a substrate 10 is provided.
In the present embodiment, the substrate 10 is a semiconductor substrate, and may be, for example, a Silicon (Si), Germanium (Ge), SiGe substrate, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe or the like.
Step S2: a stacked structure 20 is formed on the substrate 10, the stacked structure 20 including a first stacked layer 21 and a second stacked layer 22 disposed adjacent to the first stacked layer 21 in a first direction (Y), the first stacked layer 21 including a connection region stacked layer 211 and a step region stacked layer 212 alternately disposed in a second direction (X).
Specifically, dielectric material layers and conductive material layers are alternately stacked on the substrate 10 in a third direction (Z) perpendicular to the substrate 10 to form a stacked structure 20, and the stacked structure 20 may include a first stacked layer 21, and two second stacked layers 22 disposed adjacent to the first stacked layer 21 in the first direction (Y). The dielectric material layer may be silicon oxide, and the conductive material layer may be tungsten. In the present embodiment, the first stacked layer 21 may be used to form a staircase structure and a connection structure, and the second stacked layer 22 is used to form a memory structure. It is understood that the first stacked layer 21 is disposed along the second direction (X), meaning that the length direction of the first stacked layer 21 is along the second direction (X).
Referring to fig. 2c, fig. 2c is an enlarged structural diagram of the first stacked layer 21 in fig. 2b according to an embodiment of the disclosure. The extent of the stack structure 20 of fig. 2b is the extent of one storage plane (plane), and thus the edge of the first stack layer 21 in the second direction (X) is the edge of the storage plane. The first stacked layer 21 includes connection region stacked layers 211 and step region stacked layers 212 alternately arranged in the second direction (X), the connection region stacked layers 211 and the step region stacked layers 212 being arranged in the first direction (Y), respectively. In the present embodiment, the connection region stack layer 211 may include two first connection region stack layers 2111 respectively located at both ends of the first stack layer 21 in the second direction (X) direction, and a plurality of second connection region stack layers 2112 located between the two first connection region stack layers 2111. The first connection region stack layer 2111 is located at both ends of the first stack layer 21 in the second direction (X) direction, that is, at the edge of the storage plane.
In the present embodiment, the width of the first connection region stack layer 2111 in the second direction (X) is larger than the width of the second connection region stack layer 2112 in the second direction (X).
Referring to step S3 in fig. 1 and fig. 3a to 3c, fig. 3a is a schematic top view structure diagram of a first stacked layer in a step structure forming process provided by an embodiment of the disclosure, fig. 3B is a schematic YZ cross-sectional structure diagram of the stacked layers along a step region in fig. 3a after the step structure is formed provided by the embodiment of the disclosure, and fig. 3c is a schematic cross-sectional structure diagram at B-B1 in fig. 3B provided by the embodiment of the disclosure.
Step S3: a stair-step structure 30 is formed in the stair-step region stacked layer 212.
In the present embodiment, step S3 may include the following steps. 1) As shown in fig. 3a, a shielding layer 40 is formed on the two first connection region stack layers 2111. 2) A mask layer 41 is formed on the second connection region stack layer 2112 and a portion of the first connection region stack layer 2111, the mask layer 41 and the shielding layer 40 have an overlapping portion, and the material of the mask layer 41 may be the same as the material of the shielding layer 40, such as polysilicon, a high-k dielectric, titanium nitride, or any other suitable hard mask material. 3) The step region stack layers 212 are etched based on the mask layer 41 and the masking layer 40 to form a step structure 30 (as shown in fig. 3 b) in each step region stack layer 212, and the structure of the first stack layer 21 after the step structure 30 is formed is shown in fig. 3 c. Wherein the shielding layer 40 is used to protect the first connection region stack layer 2111 from forming a step structure, and the mask layer 41 can protect the second connection region stack layer 2112 from forming a step structure, so that the top surface of the connection region stack layer 211 is horizontal after step S3. Since the mask layer is square, if the shielding layer 40 is not present, the first connection region stack layer 2111 is etched to form a stepped structure. The manufacturing method further includes removing the blocking layer 40 and the mask layer 41 after the step structure 30 is formed.
In some embodiments, the width of first connection region stack layer 2111 is equal to the width of second connection region stack layer 2112 (e.g., both are equal to the width of second connection region stack layer 2112 in fig. 3 a), then the mask layer 41 formed as shown in fig. 3a can just cover up first connection region stack layer 2111 and second connection region stack layer 2112, so that first connection region stack layer 2111 and second connection region stack layer 2112 can be retained to form a first connection structure and a second connection structure, respectively, during subsequent etching of stepped structure 30. Thus in the embodiment of FIG. 3a (first connection region stack layer 2111 and a mask layer having a width greater than the width of second connection region stack layer 2112) the same mask layer is used as in some embodiments (meaning that the same mask pattern is used). Therefore, even if the first connection region stack layer 2111 and the second connection region stack layer 2112 have a larger width in the present embodiment, the same mask can be used as in some embodiments, and it is not necessary to change the pattern design of the mask at a high cost, as compared with some embodiments.
In a variation of the embodiment of FIG. 3a, mask layer 41 may cover only second connection region stack layer 2112, while barrier layer 40 covers first connection region stack layer 2111, which may also ensure that first connection region stack layer 2111 and second connection region stack layer 2112 are not etched in subsequent processes.
Further, the step structure 30 may include a plurality of sub-step structures 31 connected end to end, and the inclination directions of two adjacent sub-step structures 31 are opposite. Wherein each sub-step structure 31 comprises a plurality of small steps (not shown in the figure).
Please refer to step S4 in fig. 1 and fig. 4a-4b, wherein fig. 4a-4b are schematic cross-sectional structural diagrams in the process of forming the protection layer according to the embodiment of the disclosure.
Step S4: a protective layer 51 is formed covering the connection region stack layer 211.
In this embodiment, step S4 may include: 1) as shown in fig. 4a, a photoresist layer 50 is formed on the first stack layer 21; 2) as shown in fig. 4b, the photoresist layer 50 is exposed and developed to form a patterned photoresist layer, and the patterned photoresist layer is located on the connection region stack layer 211 as the protection layer 51. Here, the blank regions on both sides of the first connection region stacked layer 2111 are dicing street regions for dividing the semiconductor device to form a plurality of storage planes. In some embodiments, if the width of the first connection region stack layer 2111 is as narrow as that of the second connection region stack layer 2112, the photoresist layer 50 of the spin-coated photoresist layer 50 at the first connection region stack layer 2111 and the second connection region stack layer 2112 close to the first connection region 2111 will be thinner, and the side portion of the photoresist layer 50 at the thinner portion will also be removed (may be referred to as "undercut") when performing exposure and development, so that the photoresist layer 50 herein is prone to collapse, and thus the stack layer therebelow cannot be effectively protected in step S5, and the topography thereof is affected.
In this embodiment, the profile of the photoresist layer 50 is not flat outward at the edge of the first landing pad stack 2111, and forms an arc as shown in FIG. 4 a. Since the width of the first connection region stacked layer 2111 in the second direction (X) is greater than the width of the second connection region stacked layer 2112 in the second direction (X), the formed photoresist layer 50 is thinner only at the edge of the first connection region stacked layer 2111, and the thickness of the photoresist layer 50 above the middle second connection region stacked layer 2112 is uniform, so that the patterned photoresist layer is not undercut, the formed protection layer 51 can effectively protect the connection region stacked layer 211, and a connection structure with complete morphology can be formed in the subsequent process. Since the width of first connection region stack layer 2111 is wide, the risk of failure of first connection region stack layer 2111 can be reduced. That is, even if the first connection region stack layer 2111 at the edge is damaged a little, its entire structure does not fail.
Referring to step S5 in fig. 1 and fig. 5a-5b, fig. 5a is a schematic cross-sectional structure diagram in the process of forming a connection structure according to an embodiment of the disclosure, and fig. 5b is a schematic cross-sectional structure diagram at C-C1 in fig. 5a according to an embodiment of the disclosure.
Step S5: the first stack layer 21 not covered by the protective layer 51 is etched.
On the basis of fig. 3b, the step structure 30 is further etched downwards to reduce the height of the step structure 30 to form a step structure 30 ', the height of each sub-step structure 31 is reduced to form a sub-step structure 31 ', and the height of each sub-step structure 31 ' may be different. As shown in fig. 5b, under the protection of the protective layer 51 in fig. 4b, the first connection region stack layer 2111 and the second connection region stack layer 2112 are not etched to form a first connection structure 61 and a second connection structure 62, respectively, and the first connection structure 61 and the second connection structure 62 constitute a connection structure 60. The protective layer 51 is removed after the connection structure 60 is formed. Here, differences between first connection region stacked layer 2111 and second connection region stacked layer 2112 and first connection structure 61 and second connection structure 62 can be compared with fig. 3c and fig. 5 b. In FIG. 3c, first connection region stack layer 2111 and second connection region stack layer 2112 are integrally connected to step region stack layer 212; in fig. 5b, after the step structure 30' is formed, the first connecting structure 61 and the second connecting structure 62 are independent structures.
Referring to fig. 5a and 5b, when the stair-step structure 30 'is formed between two adjacent connection structures 60, a word line contact (one sub-stair-step structure 31' is regarded as one step) is formed on each sub-stair-step structure 31 'of the stair-step structure 30', and then the word line (or gate layer) of each step is driven through the word line contact. Since the step structure 30' separates the two second stacked layers on both sides in the Y direction, i.e. each step connects only one of the second stacked layers, for example, the step on the left in fig. 5a is connected only with the second stacked layer on the left, but not with the second stacked layer on the right. Since the stair-step structure 30' is adjacent to and in contact with the connection structure 60, the step on the left can be electrically connected to the second stacked layer on the right through the gate layer in the connection structure 60, so that a bidirectional word line driving scheme can be implemented, which is also the main role of the connection structure 60.
It will be appreciated that the stepped structure 30 'of figure 5a is not shown in figure 5b, since it is located at the bottom of the stepped structure 30' at C-C1 of figure 5 a. The connecting structure 60 includes two first connecting structures 61 respectively located at both ends of the first stacked layer 21 in the second direction (X), and a plurality of second connecting structures 62 located between the two first connecting structures 61. Since the width of the first connection region stack layer 2111 in the second direction (X) is larger than the width of the second connection region stack layer 2112 in the second direction (X), the width of the first connection structure 61 in the second direction (X) is larger than the width of the second connection structure 62 in the second direction (X).
The preparation method can also comprise the following steps: a memory structure is formed through the second stacked layers 22 in a third direction (Z) perpendicular to the substrate 10, the memory structure comprising a channel structure through the second stacked layers 22 in the third direction (Z).
In the manufacturing method of the semiconductor device according to the embodiment of the present disclosure, in the process of forming the step structure 30, the first connection region stack layer 2111 is shielded by the shielding layer 40, so that the first connection region stack layer 2111 is not etched to form a step. Since the first connection region stack layer 2111 has a larger width, the shape of the photoresist layer 50 (a uniform thickness over several connection region stack layers 211 at the edge) can be improved, and undercutting does not occur when forming a patterned photoresist layer (protective layer 51), so that the protective layer 51 can effectively protect the connection region stack layers 211 from forming the connection structure 60.
The disclosed embodiment also provides a semiconductor device, which can be prepared by the above method for preparing a semiconductor device, and therefore, reference may be made to fig. 2a to 2b and fig. 5a and 5b, and the semiconductor device includes: a substrate 10; a stacked structure 20 on the substrate 10, the stacked structure 20 including a first stacked layer 21 and two second stacked layers 22 adjacent to the first stacked layer 21 in a first direction (Y), the first stacked layer 21 including connection structures 60 and step structures 30 'alternately arranged in the second direction (X), the connection structures 60 and the step structures 30' being respectively arranged in the first direction (Y) parallel to the substrate 10 and perpendicular to the second direction (X).
Wherein the connecting structure 60 includes two first connecting structures 61 respectively located at both ends of the first stacked layer 21 in the second direction (X), and a plurality of second connecting structures 62 located between the two first connecting structures 61. The width of the first connection structure 61 in the second direction (X) is greater than the width of the second connection structure 62 in the second direction (X).
The semiconductor device may further include: the memory structures of the two second stacked layers 22 are penetrated in a third direction perpendicular to the substrate 10.
The stacked structure 20 includes dielectric material layers and conductive material layers alternately stacked in a third direction (Z) perpendicular to the substrate 10, respectively.
The above description of the embodiments is only for helping understanding the technical solutions of the present disclosure and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a stacked structure on the substrate, the stacked structure including a first stacked layer and a second stacked layer disposed adjacent to the first stacked layer in a first direction, the first stacked layer including first connection region stacked layers respectively located at both ends of the first stacked layer in the second direction and second connection region stacked layers located between the first connection region stacked layers, wherein a width of the first connection region stacked layer in the second direction is larger than a width of the second connection region stacked layer in the second direction, and the first direction is perpendicular to the second direction;
forming a protective layer covering the first connection region stack layer and the second connection region stack layer;
and etching the first stacked layer uncovered by the protective layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the first stacked layer further includes a step region stacked layer, and the step region stacked layer and the second connection region stacked layer are alternately arranged in the second direction.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer is preceded by:
forming a shielding layer on the first connection region stacking layer;
forming a mask layer on the second connection region stack layer;
etching the stepped region stacked layer based on the mask layer and the shielding layer to form a stepped structure in the stepped region stacked layer;
and removing the shielding layer and the mask layer.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the step of forming a protective layer covering the first connection region stack layer and the second connection region stack layer includes:
forming a photoresist layer on the first stack layer;
and exposing and developing the photoresist to form a patterned photoresist layer, wherein the patterned photoresist layer is positioned on the first connecting area stacking layer and the second connecting area stacking layer and serves as the protective layer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of etching the first stack layer uncovered by the protective layer comprises:
and continuously etching the stepped structure downwards to reduce the height of the stepped structure.
6. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a memory structure through the second stacked layers in a third direction perpendicular to the substrate.
7. The method according to claim 6, wherein the step of forming a stacked structure on the substrate comprises:
alternately stacking layers of conductive material and layers of dielectric material in a third direction perpendicular to the substrate.
8. A semiconductor device, comprising:
a substrate;
a stacked structure on the substrate, the stacked structure including a first stacked layer and a second stacked layer disposed adjacent to the first stacked layer in a first direction;
the first stacking layer comprises first connecting structures and a plurality of second connecting structures, wherein the first connecting structures are respectively positioned at two ends of the first stacking layer in the second direction, and the plurality of second connecting structures are positioned between the first connecting structures; the width of the first connecting structure in the second direction is larger than that of the second connecting structure in the second direction, and the first direction is perpendicular to the second direction.
9. The semiconductor device according to claim 8, wherein the first stack layer further comprises a plurality of step structures, the step structures being arranged alternately with the second connection structures in the second direction.
10. The semiconductor device according to claim 8, wherein the stacked structure comprises alternately stacked layers of dielectric material and conductive material, respectively, in a third direction perpendicular to the substrate.
11. The semiconductor device according to claim 8, further comprising: a memory structure extending through the second stacked layers in a third direction perpendicular to the substrate.
CN202210325853.7A 2022-03-29 2022-03-29 Preparation method of semiconductor device and semiconductor device Pending CN114725118A (en)

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