CN114725108A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure includes: providing a substrate; forming a trench in the substrate, and the bottom and sidewalls of the trench are covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, and the upper surface of the conductive layer is lower than The upper surface of the substrate; the sacrificial layer is removed to form air spacers on opposite sides of the conductive layer; an insulating protective layer is formed, and the insulating protective layer covers the upper surface of the conductive layer and the top of the air spacers. In the preparation method of the above semiconductor structure, by forming a conductive layer with a larger height in the trench, the cross-sectional area of the conductive layer can be increased while the line width of the word line structure remains unchanged, thereby greatly reducing the word line resistance. , increase the on-current of the word line and improve the response speed of the transistor; in addition, by forming air spacers on opposite sides of the conductive layer, the electric field between the gate and the drain can be reduced, the GIDL can be reduced, and the crystal power of the transistor can be reduced. consumption and improve the reliability of the transistor.

Description

Semiconductor structure and method of making the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.

Background technique

With the development of DRAM towards high speed, high integration density and low power consumption, the size of the DRAM device structure is getting smaller and smaller, especially in the process of manufacturing DRAM devices with smaller line width, the material, shape, size of the word line As well as electrical properties and other aspects have higher requirements.

The critical dimension of the word line structure is constantly shrinking, but the requirements for the electrical performance of the transistor have not decreased, which is prone to generate a large gate-induced drain leakage current (GIDL) in the transistor, which seriously affects the reliability of the transistor. At the same time, the resistance of the word line is closely related to the response speed of the semiconductor device. With the further reduction of the width of the word line, the resistance of the word line increases sharply, which reduces the response speed of the semiconductor device.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a semiconductor structure and a preparation method for the problems of increased word line resistance and GIDL current caused by the shrinking of the word line structure, so as to reduce the resistance of the word line structure, reduce the GIDL current, and improve the reliability of the device. performance and responsiveness.

An embodiment of the present application discloses a semiconductor structure, comprising: a substrate having a trench therein, the trench including a first trench close to a surface of the substrate and a first trench away from the surface of the substrate the width of the first trench is greater than the width of the second trench; a dielectric layer covers the bottom and sidewalls of the trench; a conductive layer is located in the trench, the The upper surface of the conductive layer is lower than the upper surface of the substrate; the air spacers are located in the first trench and are located on opposite sides of the conductive layer; an insulating protective layer covers the upper surface of the conductive layer and the top of the air side wall.

In the above semiconductor structure, air spacers are arranged on both sides of the conductive layer, and when they are applied to the transistor structure, the electric field between the gate and the drain can be reduced, thereby reducing the GIDL leakage current, reducing the static power consumption of the transistor, and prolonging the The device life is increased and the reliability of the transistor is improved.

In one embodiment, the upper surface of the conductive layer is flush with the middle or upper middle portion of the first trench.

In the above-mentioned semiconductor structure, by forming a conductive layer with a larger height, the resistance of the word line can be reduced, the conduction current of the word line can be increased, and the response speed of the semiconductor device can be improved under the condition that the line width of the word line remains unchanged.

In one embodiment, the conductive layer includes a metal layer and a metal barrier layer covering the bottom and sidewalls of the metal layer.

In one embodiment, the air spacer is located between the side wall of the conductive layer and the dielectric layer, and the top of the air spacer is flush with the upper surface of the conductive layer.

In one embodiment, the air spacer is a space enclosed and formed by the conductive layer, the insulating protective layer and the dielectric layer.

A method for preparing a semiconductor structure, comprising: providing a substrate; forming a trench in the substrate, the bottom and sidewalls of the trench being covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer layer, the upper surface of the conductive layer is lower than the upper surface of the substrate; the sacrificial layer is removed to form air spacers on opposite sides of the conductive layer; an insulating protective layer is formed, the insulating protective layer Cover the upper surface of the conductive layer and the top of the air spacer.

In the preparation method of the above semiconductor structure, by forming a conductive layer with a larger height in the trench, the cross-sectional area of the conductive layer can be increased under the condition that the line width of the word line structure remains unchanged, thereby greatly reducing the word line resistance. , increase the on-current of the word line and improve the response speed of the transistor; in addition, by forming air spacers on opposite sides of the conductive layer, the electric field between the gate and the drain can be reduced, the GIDL can be reduced, and the crystal power of the transistor can be reduced. consumption and improve the reliability of the transistor.

In one embodiment, the dielectric layer includes a first dielectric layer and a second dielectric layer; the trench is formed in the substrate, and the bottom and sidewalls of the trench are covered by the dielectric layer, including: forming a first trench in the substrate, the first trench having a first width; forming the first dielectric layer on the bottom and sidewalls of the first trench; removing the first trench the first dielectric layer at the bottom, and a second trench is formed at the bottom of the first trench, the second trench has a second width, and the second width is smaller than the first width; forming the The second dielectric layer covers the bottom and sidewalls of the second trench and the sidewalls of the first dielectric layer.

In one embodiment, the first dielectric layer and the second dielectric layer include silicon oxide layers.

In one embodiment, the thickness of the first dielectric layer includes 5 nm-15 nm; the thickness of the second dielectric layer includes 5 nm-15 nm.

In one embodiment, forming the sacrificial layer in the dielectric layer includes: doping the dielectric layer with a first component to obtain the sacrificial layer; wherein the sacrificial layer has a thickness less than the thickness of the dielectric layer.

In one of the embodiments, the first component includes phosphorus.

In one embodiment, the doping the first component into the dielectric layer includes: doping the second dielectric layer located on the sidewall of the first dielectric layer with the first component , to obtain the sacrificial layer.

In one embodiment, the thickness of the sacrificial layer is equal to the thickness of the second dielectric layer.

In one embodiment, the forming a conductive layer includes: forming a metal barrier layer, the metal barrier layer covering the surfaces of the sacrificial layer and the dielectric layer; forming a metal layer, the metal layer filling the surface of the dielectric layer trenching and covering the upper surface of the substrate; removing the metal layer on the upper surface of the substrate, and reducing the thickness of the metal layer in the trench so that the upper surface of the metal layer is lower than the upper surface of the substrate; removing part of the metal barrier layer so that the top of the metal barrier layer is flush with the upper surface of the metal layer.

In one embodiment, the upper surface of the metal layer is flush with the middle or upper middle portion of the sacrificial layer.

In one embodiment, the removing the sacrificial layer to form air spacers on opposite sides of the conductive layer includes: removing the sacrificial layer by an etching process to form the air spacers, The air spacer exposes the sidewall of the first dielectric layer, the top of the second dielectric layer and a part of the sidewall of the conductive layer.

In one embodiment, the forming the insulating protection layer includes: forming an insulating material layer, the insulating material layer covering the top of the air spacer, the upper surface of the conductive layer and the upper surface of the substrate ; removing the insulating material layer on the upper surface of the substrate to obtain the insulating protection layer; wherein, the upper surface of the insulating protection layer is flush with the upper surface of the substrate.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, the drawings of other embodiments can also be obtained according to these drawings without creative effort.

1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present application;

2 is a schematic cross-sectional structural diagram of a semiconductor structure after a patterned photoresist layer is formed on a substrate according to an embodiment of the present application;

3 is a schematic cross-sectional structural diagram of the semiconductor structure after the first trench is formed in an embodiment of the present application;

4 is a schematic cross-sectional structural diagram of a semiconductor structure after forming a first dielectric layer according to an embodiment of the present application;

5 is a schematic cross-sectional structural diagram of the semiconductor structure after the second trench is formed in an embodiment of the present application;

6 is a schematic cross-sectional structural diagram of a semiconductor structure after forming a second dielectric layer in an embodiment of the present application;

7 is a schematic cross-sectional structural diagram of a semiconductor structure after a sacrificial layer is formed in the dielectric layer on one side of the trench according to an embodiment of the application;

8 is a schematic cross-sectional structural diagram of a semiconductor structure after a sacrificial layer is formed in the dielectric layer on the other side of the trench according to an embodiment of the present application;

9 is a schematic cross-sectional structural diagram of a semiconductor structure after forming a metal barrier layer according to an embodiment of the present application;

10 is a schematic cross-sectional structural diagram of a semiconductor structure after forming a metal layer according to an embodiment of the present application;

11 is a schematic cross-sectional structural diagram of the semiconductor structure after the height of the metal barrier layer is reduced according to an embodiment of the present application;

12 is a schematic cross-sectional structural diagram of a semiconductor structure after forming an air spacer in an embodiment of the present application;

FIG. 13 is a schematic cross-sectional structure diagram of the semiconductor structure after the insulating protective layer is formed in an embodiment of the present application.

Description of reference numbers:

10, substrate; 11, patterned photoresist layer; 20, trench; 21, first trench; 22, second trench; 30, dielectric layer; 31, first dielectric layer; 32, second dielectric layer 33, sacrificial layer; 40, conductive layer; 41, metal layer; 42, metal barrier layer; 50, air sidewall; 60, insulating protective layer.

Detailed ways

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that a thorough and complete understanding of the present disclosure is provided.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In describing positional relationships, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present, unless otherwise specified. Further, when a layer is referred to as being "under" another layer, it can be directly under, and one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Where "including", "having", and "comprising" are used as described herein, unless an explicit qualifying language is used, such as "only", "consisting of," etc., another component may also be added . Unless mentioned to the contrary, terms in the singular may include the plural and should not be construed as having a number of one.

With the development of DRAM towards high speed, high integration density and low power consumption, the size of the DRAM device structure is getting smaller and smaller, especially in the process of manufacturing DRAM devices with smaller line width, the material, shape, size of the word line As well as electrical properties and other aspects have higher requirements. The critical dimension of the word line structure is continuously reduced, but the requirements for electrical performance have not decreased, which is prone to generate a large gate-induced drain leakage current (GIDL) in the transistor, which seriously affects the reliability of the transistor. At the same time, the resistance of the word line is closely related to the response speed of the semiconductor device. With the further reduction of the width of the word line, the resistance of the word line increases sharply, which reduces the response speed of the semiconductor device.

In order to solve the above problems, an embodiment of the present application discloses a method for preparing a semiconductor structure, as shown in FIG. 1 , including:

S10: provide a substrate;

S20: a trench is formed in the substrate, and the bottom and sidewalls of the trench are covered by a dielectric layer;

S30: forming a sacrificial layer in the dielectric layer;

S40: forming a conductive layer, and the upper surface of the conductive layer is lower than the upper surface of the substrate;

S50: removing the sacrificial layer to form air spacers on opposite sides of the conductive layer;

S60: forming an insulating protective layer covering the upper surface of the conductive layer and the top of the air sidewall.

In the preparation method of the above semiconductor structure, by forming an air spacer between the dielectric layer and the conductive layer, the electric field between the gate and the drain can be reduced, the GIDL effect of the device can be effectively improved, and the leakage of the device when the device is in an off state can be reduced. current, reducing static power consumption and extending device life.

Illustratively, the above-described method for fabricating a semiconductor structure may be used for fabricating a wordline structure, such as a buried wordline structure. Specifically, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. In step S20, for example, the trench 20 includes a first trench 21 close to the surface of the substrate 10 and a second trench 22 away from the surface of the substrate 10, and the dielectric layer 30 includes a first dielectric layer 31 and a second dielectric layer 32. Please refer to FIG. 2 to FIG. 6 , the specific steps of forming the trench 20 and the dielectric layer 30 include:

S21 : forming a first trench 21 in the substrate 10 , and the first trench 21 has a first width.

For example, as shown in FIG. 2 , a patterned photoresist layer 11 may be formed on the upper surface of the substrate 10 first, and the pattern in the patterned photoresist layer 11 is used to define the position and line width of the first trenches 21 . The first trench 21 has a first width, for example, the first width may be 30 nm to 100 nm, such as 30 nm, 50 nm, 70 nm or 100 nm.

Optionally, in some embodiments, a hard mask layer may also be formed between the patterned photoresist layer 11 and the substrate 10 to improve the quality and precision of pattern transfer.

For example, as shown in FIG. 3 , an etching process is used to form the first trench 21 in the substrate 10 . As an example, the substrate 10 may be etched by using BCl3 gas and Cl gas, and the RF bias power used in the etching process may be 100 watts to 700 watts, such as 100 watts, 300 watts, 500 watts or 700 watts; The etching pressure may be 5 mtorr to 20 mtorr, such as 5 mtorr, 10 mtorr, 15 mtorr or 20 mtorr; 100 degrees Celsius. As an example, the depth of the first trench 21 may be 50 nm to 100 nm, such as 50 nm, 70 nm or 100 nm.

Optionally, in some embodiments, after the first trench 21 is formed, a cleaning process may also be used to remove by-products or impurity particles remaining on the surface of the first trench 21 . For example, the cleaning process may include, but is not limited to, an SPM cleaning process, and the ambient temperature for performing the cleaning process may be 25 degrees Celsius to 50 degrees Celsius, such as 25 degrees Celsius, 30 degrees Celsius, 40 degrees Celsius, or 50 degrees Celsius.

Optionally, in some embodiments, a self-aligned double patterning process (SADP) or a self-aligned quadruple patterning process (SAQP) may also be used to form the first pattern in the substrate 10 . A groove 21 .

S22 : forming a first dielectric layer 31 on the bottom and sidewalls of the first trench 21 , as shown in FIG. 4 .

For example, an in-situ water vapor growth process, an atomic layer deposition process or a combination of the above two processes may be used to deposit the first dielectric layer 31 in the first trench 21 , and the first dielectric layer 31 covers the first trench 21 . Bottom and side walls. As an example, the first dielectric layer 31 may be a material layer with a relatively high dielectric constant, such as a silicon dioxide layer. The thickness of the first dielectric layer 31 may be 5 nm to 15 nm, for example, 5 nm, 7 nm, 10 nm or 15 nm. The upper surface of the first dielectric layer 31 is flush with the upper surface of the substrate 10 .

S23: removing the first dielectric layer 31 at the bottom of the first trench 21, and forming a second trench 22 at the bottom of the first trench 21, the second trench 22 has a second width, and the second width is smaller than the first width, As shown in Figure 5.

For example, a directional etching process may be used to first remove the first dielectric layer 31 at the bottom of the first trench 21, for example, an anisotropic plasma etching process may be used to etch the first dielectric layer 31 in the vertical direction, exposing the The bottom of the first trench 21 is removed. Then, using the remaining first dielectric layer 31 and the patterned photoresist layer 11 as mask layers, the substrate 10 is continuously etched, and a second trench 22 with a second width is formed at the bottom of the first trench 21 , the second width is smaller than the first width. As an example, the second width may be 20 nm to 70 nm, such as 20 nm, 30 nm, 50 nm or 70 nm. For the process parameters for forming the second trench 22 by etching, reference may be made to the process parameters for forming the first trench 21 in step S21 , which will not be repeated here.

S24 : forming a second dielectric layer 32 covering the bottom and sidewalls of the second trenches 22 and the sidewalls of the first dielectric layer 31 , as shown in FIG. 6 .

For example, the materials of the second dielectric layer 32 and the first dielectric layer 31 may be the same, for example, both are silicon dioxide layers. The process of forming the second dielectric layer 32 includes an in-situ water vapor generation process and an atomic layer deposition process. The thickness of the second dielectric layer 32 is 5 nm to 15 nm, such as 5 nm, 7 nm, 10 nm or 15 nm. As shown in FIG. 6 , the upper surface of the second dielectric layer 32 is flush with the upper surface of the substrate 10 . The first dielectric layer 31 and the second dielectric together form the dielectric layer 30 , covering the bottom and sidewalls of the trench 20 .

In step S30 , the dielectric layer 30 may be doped with the first component to obtain a sacrificial layer 33 ; wherein the thickness of the sacrificial layer 33 is smaller than that of the dielectric layer 30 , as shown in FIGS. 7 and 8 .

For example, the first component includes phosphorus ions. Phosphorus ions can be implanted into the dielectric layer 30 by using a method of inclination angle phosphorus ion implantation, and the formed phosphorus ion implantation layer is used as the sacrificial layer 33 . As an example, the implantation dose may be 1011-1012/cm2, the implantation energy may be 5keV-25keV, and the implantation depth may be 5nm-15nm. The depth of ion implantation can be adjusted as required, so as to obtain sacrificial layers 33 with different thicknesses. In FIG. 7 , the angle of ion implantation is 15° to 60° to the left in the vertical direction; in FIG. 8 , the angle of ion implantation is 15° to 60° to the right in the vertical direction. There are different etching selectivity ratios between the phosphorus ion implantation layer and the undoped dielectric layer, so the phosphorus ion implantation layer can be selectively removed in the subsequent etching process, leaving the undoped phosphorus ion dielectric layer 30.

In some embodiments, the second dielectric layer 32 located on the sidewall of the first dielectric layer 31 may be doped with the first component to obtain the sacrificial layer 33 , as shown in FIG. 7 and FIG. 8 . The thickness of the sacrificial layer 33 is equal to the thickness of the second dielectric layer 32 .

In step S40, please refer to FIG. 9 to FIG. 11, the specific steps of forming the conductive layer 40 include:

S41: forming a metal barrier layer 42, the metal barrier layer 42 covers the surfaces of the sacrificial layer 33 and the dielectric layer 30, as shown in FIG. 9 .

For example, the metal barrier layer 42 may include, but is not limited to, a titanium nitride layer. A titanium nitride layer with a certain thickness can be formed in the trench 20 by using a physical vapor deposition process or a chemical vapor deposition process to serve as the metal barrier layer 42 . Materials used to prepare the titanium nitride layer include TiCl4, NH3 and N2. In some embodiments, a rapid thermal nitridation (RTN) process can be used to improve the barrier properties of the titanium nitride layer. As an example, the thickness of the metal barrier layer 42 may be 2 nm to 10 nm, such as 2 nm, 5 nm or 10 nm.

After the metal barrier layer 42 is formed, the patterned photoresist layer is removed to obtain the structure shown in FIG. 9 .

S42 : forming the metal layer 41 , the metal layer 41 fills the trench 20 and covers the upper surface of the substrate 10 .

For example, the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). Taking the tungsten layer as an example, the tungsten layer can be formed in the trench 20 by using a physical vapor deposition process. The tungsten layer fills the trench 20 and covers the upper surface of the substrate 10 .

S43: Remove the metal layer 41 on the upper surface of the substrate 10, and reduce the thickness of the metal layer 41 in the trench 20, so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10, as shown in FIG. 10 .

For example, chemical mechanical polishing (CMP) may be used to planarize the metal layer 41 to grind the upper surface of the metal layer 41 until the upper surface of the metal layer 41 is flush with the upper surface of the substrate 10 . In some embodiments, the polishing progress of the CMP process can be controlled by means of an end point detection system. For example, the upper surface of the substrate 10 may be used as the end point for detection, and when the upper surface of the substrate 10 is ground, the CMP process is accurately ended to avoid damage to the substrate 10 caused by the CMP process.

Further, the metal layer 41 in the trench 20 is etched back by an etching process to reduce the height of the metal layer 41 so that the upper surface of the metal layer 41 is lower than the upper surface of the substrate 10 . As an example, the distance between the upper surface of the metal layer 41 and the upper surface of the substrate 10 is 20 nm to 40 nm, eg, 20 nm, 30 nm or 40 nm.

S44: Remove part of the metal barrier layer 42 so that the top of the metal barrier layer 42 is flush with the upper surface of the metal layer 41, as shown in FIG. 11 .

For example, the metal barrier layer 42 (eg, a titanium nitride layer) may be etched by an SPM cleaning process to reduce the height of the metal barrier layer 42 so that the top of the metal barrier layer 42 is flush with the upper surface of the metal layer 41 . The temperature at which the SPM cleaning process is performed is 25 degrees Celsius to 50 degrees Celsius. As shown in FIG. 11 , the metal barrier layer 42 and the metal layer 41 together constitute the conductive layer 40 .

As shown in FIG. 11 , the conductive layer 40 is located in the trench 20 , the upper surface of which is lower than the upper surface of the substrate 10 but higher than the second trench 22 . Optionally, the upper surface of the conductive layer 40 is flush with the middle of the first trench 21 , or higher than the middle of the first trench 21 , eg, flush with the middle and upper portion of the first trench 21 .

In the above-mentioned preparation method of the semiconductor structure, by forming the conductive layer 40 with a larger height in the trench 20, the cross-sectional area of the conductive layer 40 can be increased under the condition that the line width of the word line structure remains unchanged, thereby greatly reducing the The word line resistance increases the conduction current of the word line and improves the response speed of the transistor.

In step S50 , the sacrificial layer 33 is removed, and air spacers 50 are formed on opposite sides of the conductive layer 40 , as shown in FIG. 12 . The sacrificial layer 33 is removed by an etching process to form the air spacer 50 , which exposes the sidewall of the first dielectric layer 31 , the top of the second dielectric layer 32 and part of the sidewall of the conductive layer 40 .

Since the sacrificial layer 33 and the dielectric layer 30 not doped with phosphorus ions have different etching selectivity ratios, the sacrificial layer 33 can be selectively removed in the etching process, leaving the dielectric layer 30 not doped with phosphorus ions. . For example, the sacrificial layer 33 may be removed by a wet etching process. When the thickness of the sacrificial layer 33 is the same as the thickness of the second dielectric layer 32, the result shown in FIG. 12 can be obtained after the sacrificial layer 33 is removed. The air spacer 50 exposes the sidewall of the first dielectric layer 31 and the second dielectric The top of layer 32 and part of the sidewalls of conductive layer 40 .

Optionally, in some other embodiments, the thickness of the sacrificial layer 33 can be adjusted according to the requirement of the thickness of the air spacer 50 , so as to form a target between the conductive layer 40 and the dielectric layer 30 after the sacrificial layer 33 is removed Thickness of the air sidewall 50.

In step S60 , an insulating protective layer 60 is formed, and the insulating protective layer 60 covers the upper surface of the conductive layer 40 and the top of the air spacer 50 , as shown in FIG. 13 . Specific steps include:

S61 : forming an insulating material layer covering the top of the air spacer 50 , the upper surface of the conductive layer 40 and the upper surface of the substrate 10 .

For example, the insulating material layer may include, but is not limited to, a silicon nitride layer. A silicon nitride layer may be deposited on the upper surface of the conductive layer 40 by a chemical vapor deposition process to cover the top of the air spacer 50 , the upper surface of the conductive layer 40 and the upper surface of the substrate 10 . As an example, the raw materials for preparing the silicon nitride layer include TiCL4 and NH3.

S62 : removing the insulating material layer on the upper surface of the substrate 10 to obtain an insulating protective layer 60 ; wherein, the upper surface of the insulating protective layer 60 is flush with the upper surface of the substrate 10 , as shown in FIG. 13 .

For example, a chemical mechanical polishing process can be used to grind and planarize the insulating material layer, and the upper surface of the substrate 10 is used as the end point. The upper surface of the substrate 10 is flush with the insulating protective layer 60 .

In the above preparation method of the semiconductor structure, by forming the air spacer 50 between the dielectric layer 30 and the conductive layer 40, the GIDL effect of the device can be effectively improved, the leakage current of the device when the device is in an off state can be reduced, the static power consumption can be reduced, and the device can be extended. In addition, by forming the conductive layer 40 with a larger height in the trench 20, the cross-sectional area of the conductive layer 40 can be increased while the line width of the word line structure remains unchanged, thereby greatly reducing the word line resistance , to increase the on-current of the word line and improve the response speed of the transistor

As shown in FIG. 13 , an embodiment of the present application further discloses a semiconductor structure, including: a substrate 10 , a trench 20 is formed in the substrate 10 , and the trench 20 includes a first trench 21 close to the surface of the substrate 10 . and the second trench 22 away from the surface of the substrate 10, the width of the first trench 21 is greater than the width of the second trench 22; the dielectric layer 30 covers the bottom and sidewalls of the trench; the conductive layer 40 is located in the trench 20 , the upper surface of the conductive layer 40 is lower than the upper surface of the substrate 10 ; the air spacers 50 are located in the first trench 21 and are located on opposite sides of the conductive layer 40 ; the insulating protection layer 60 covers the upper surface of the conductive layer 40 Top of surface and air side walls 50 .

In the above semiconductor structure, air spacers are arranged on both sides of the conductive layer. When they are applied to the transistor structure, the electric field between the gate and the drain can be reduced, thereby reducing the GIDL leakage current and reducing the static power consumption of the transistor. Extend the life of the device and improve the reliability of the device.

As an example, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate. The trenches 20 are arranged in the substrate 10 in parallel and spaced apart. As an example, trench 20 may be a word line trench. The trench 20 includes a first trench 21 close to the surface of the substrate 10 and a second trench 22 away from the surface of the substrate 10 . The dielectric layer 30 covers the sidewall of the first trench 21 and the bottom and sides of the second trench 22 wall. As an example, the dielectric layer 30 may include, but is not limited to, a silicon oxide layer.

In some embodiments, the conductive layer 40 may include a metal layer 41 and a metal barrier layer 42 covering the bottom and sidewalls of the metal layer 41 . For example, the material for forming the metal layer 41 may include, but is not limited to, Ge (germanium), W (tungsten), Cu (copper), or Au (gold). The material for forming the metal barrier layer 42 may be, for example, a titanium layer or a titanium nitride layer. The metal barrier layer 42 is used to separate the metal layer 41 from the silicon layer in the substrate 10, so as to prevent the metal layer 41 and the silicon layer from infiltrating each other, thereby affecting product performance.

As shown in FIG. 13 , the conductive layer 40 fills the second trench 22 and extends to the first trench 21 , wherein the upper surface of the conductive layer 40 is lower than the upper surface of the substrate 10 . For example, the upper surface of the conductive layer 40 is flush with the middle and upper part of the first trench 21 . Optionally, in some other embodiments, the upper surface of the conductive layer 40 is flush with the middle of the first trench 21 .

In the above semiconductor structure, the conductive layer 40 fills at least half of the trench 20. Under the condition of keeping the line width unchanged, the cross-sectional area of the conductive layer is increased, the conductive resistance is reduced, the on-state current is increased, and the the response speed of the device.

In some embodiments, the air spacer 50 is located between the sidewall of the conductive layer 40 and the dielectric layer 30 , and the top of the air spacer 50 is flush with the upper surface of the conductive layer 40 .

As shown in FIG. 13 , the air spacers 50 are located in the first trench 21 on opposite sides of the conductive layer 40 to separate the conductive layer 40 from the dielectric layer 30 . The air spacer 50 is a space enclosed and formed by the conductive layer 40 , the insulating protective layer 60 and the dielectric layer 30 .

For example, the above-mentioned semiconductor structure may be a word line structure, such as a buried word line structure. The word line structure can be applied to a dynamic random access memory (DRAM), so as to improve the response speed of the device, reduce static power consumption, and extend the service life and reliability of the DRAM device.

The present application also discloses a semiconductor device including the semiconductor structure in any of the foregoing embodiments. By way of example, semiconductor devices may include DRAM devices, or other devices including transistor structures.

It should be understood that although the various steps in the flowchart of FIG. 1 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Also, at least a portion of the steps in FIG. 1 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily carried out sequentially, but can be performed with other steps or steps in other steps or At least a portion of the phases are performed in turn or alternately.

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (17)

1. a semiconductor structure, is characterized in that, comprises: A substrate, wherein the substrate has a groove, the groove includes a first groove close to the surface of the substrate and a second groove away from the surface of the substrate, the width of the first groove is greater than the width of the second groove; a dielectric layer covering the bottom and sidewalls of the trench; a conductive layer, located in the trench, the upper surface of the conductive layer is lower than the upper surface of the substrate; air spacers, located in the first trench and on opposite sides of the conductive layer; an insulating protective layer covering the upper surface of the conductive layer and the top of the air spacer. 2 . The semiconductor structure of claim 1 , wherein the upper surface of the conductive layer is flush with the middle portion or the upper middle portion of the first trench. 3 . 3 . The semiconductor structure of claim 1 , wherein the conductive layer comprises a metal layer and a metal barrier layer covering the bottom and sidewalls of the metal layer. 4 . 4 . The semiconductor structure of claim 1 , wherein the air spacer is located between the sidewall of the conductive layer and the dielectric layer, and the top of the air spacer is connected to the conductive layer. 5 . the top surface is flush. 5 . The semiconductor structure of claim 1 , wherein the air spacer is a space enclosed and formed by the conductive layer, the insulating protective layer and the dielectric layer. 6 . 6. A method for preparing a semiconductor structure, comprising: provide a substrate; forming a trench in the substrate, the bottom and sidewalls of the trench are covered by a dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, the upper surface of the conductive layer is lower than the upper surface of the substrate; removing the sacrificial layer to form air spacers on opposite sides of the conductive layer; An insulating protective layer is formed, and the insulating protective layer covers the upper surface of the conductive layer and the top of the air spacer. 7 . The method for fabricating a semiconductor structure according to claim 6 , wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer; the trench is formed in the substrate, and the trench is formed in the substrate. 8 . The bottom and sidewalls are covered by a dielectric layer, including: forming a first trench in the substrate, the first trench having a first width; forming the first dielectric layer on the bottom and sidewalls of the first trench; removing the first dielectric layer at the bottom of the first trench, and forming a second trench at the bottom of the first trench, the second trench has a second width, and the second width is smaller than the the first width; The second dielectric layer is formed, and the second dielectric layer covers the bottom and sidewalls of the second trench and the sidewalls of the first dielectric layer. 8. The method for fabricating a semiconductor structure according to claim 7, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide layers. 9 . The method for fabricating a semiconductor structure according to claim 7 , wherein the thickness of the first dielectric layer is 5 nm-15 nm; the thickness of the second dielectric layer is 5 nm-15 nm. 10 . 10. The method for fabricating a semiconductor structure according to claim 7, wherein the forming a sacrificial layer in the dielectric layer comprises: Doping the first component into the dielectric layer to obtain the sacrificial layer; Wherein, the thickness of the sacrificial layer is smaller than the thickness of the dielectric layer. 11. The method for fabricating a semiconductor structure according to claim 10, wherein the first component comprises phosphorus. 12 . The method for fabricating a semiconductor structure according to claim 10 , wherein the doping the first component into the dielectric layer comprises: 12 . The second dielectric layer located on the sidewall of the first dielectric layer is doped with the first component to obtain the sacrificial layer. 13 . The method for fabricating a semiconductor structure according to claim 12 , wherein the thickness of the sacrificial layer is equal to the thickness of the second dielectric layer. 14 . 14. The method for fabricating a semiconductor structure according to claim 13, wherein the forming a conductive layer comprises: forming a metal barrier layer covering the surfaces of the sacrificial layer and the dielectric layer; forming a metal layer that fills the trench and covers the upper surface of the substrate; removing the metal layer on the upper surface of the substrate, and reducing the thickness of the metal layer in the trench, so that the upper surface of the metal layer is lower than the upper surface of the substrate; Part of the metal barrier layer is removed so that the top of the metal barrier layer is flush with the upper surface of the metal layer. 15 . The method for fabricating a semiconductor structure according to claim 14 , wherein the upper surface of the metal layer is flush with the middle or upper middle portion of the sacrificial layer. 16 . 16 . The method for fabricating a semiconductor structure according to claim 15 , wherein the removing the sacrificial layer to form air spacers on opposite sides of the conductive layer comprises: 16 . The sacrificial layer is removed by an etching process to form the air spacer, and the air spacer exposes the sidewall of the first dielectric layer, the top of the second dielectric layer and a part of the side of the conductive layer wall. 17. The method for preparing a semiconductor structure according to any one of claims 6-16, wherein the forming an insulating protective layer comprises: forming an insulating material layer covering the top of the air spacer, the upper surface of the conductive layer and the upper surface of the substrate; The insulating material layer on the upper surface of the substrate is removed to obtain the insulating protection layer; wherein, the upper surface of the insulating protection layer is flush with the upper surface of the substrate.

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