CN1147209C - inverter - Google Patents

Abstract

An integrated circuit control device for driving a half bridge type of inverter. The IC control inverter powers a load including a lamp. The device includes at least one pin, which during the preheat cycle of the lamp is at a high logic level resulting in the coupling of an additional capacitor to an unloaded resonant tank circuit. The overall resonant frequency of the unloaded circuit is reduced making it less likely that a high voltage will be applied to the lamp during preheat. Once the lamp filaments have been preheated the pin is at a low logic level. The low logic level at the pin causes the additional capacitor to be decoupled from the tank circuit. The pin when at the low logic level also receives a signal representing the voltage condition across the lamp.

Description

inverter

technical field

The invention relates to an inverter for supplying a load comprising a lamp, the inverter comprising:

switching means for switching between a conductive state and a non-conductive state in response to a drive signal, thereby transferring power to said load such that a voltage is applied to said lamp and current flows through said lights, and

control circuitry for generating drive signals including amplifiers for comparing a feedback signal based on a lamp power signal reflecting the amount of power consumed by the lamp with a varying voltage, said The varying voltage represents a desired lamp power level ranging from a minimum light level to maximum brightness at full lamp power.

Background technique

Such an inverter or conventional electronic ballast typically includes an input stage and an output stage. The input stage provides a DC power supply for the output stage by converting the AC signal obtained from the power line to a DC signal. A lamp is driven by the output stage, which may be of the half-bridge inverter type. Control circuitry, such as that disclosed in U.S. Patent No. 4,952,849, provides linear control of lamp power between 20% and 100% of full lamp power in response to an external dimming control signal indicative of the desired amount of illumination. Below 15% of full lamp power the linear relationship between the external dimming control signal and the lamp power provided by the control circuit cannot be maintained.

Such a control circuit, as disclosed in US Patent No. 4,952,849, controls lamp power based on a weighted sum of lamp current and lamp voltage. Below about 15% of full lamp power, light output is no longer linearly proportional to lamp current. This non-linearity makes it difficult to regulate lamp power at very low light levels (eg, as low as 1% to 3% of full light output).

Contents of the invention

Therefore, there is a need to provide an improved lamp ballast with which the light output can be adjusted as low as 1% to 3% of the full light output. It is advisable that the adjustment at such extremely low light levels should be performed with a linear relationship between the external dimming control signal and the lamp power.

Therefore, an inverter as described in the opening paragraph is characterized in that said feedback signal is the sum of the DC bias voltage and the lamp power signal.

The DC bias voltage can be chosen such that even for very low magnitudes of power consumed by the lamp, the relationship between the varying voltage and the power consumed by the lamp is linear, resulting in good performance at very low light levels. Lamp power regulation feature.

The direct bias voltage can be made dependent on the lamp power signal by eg choosing different constant values of the direct bias voltage for different ranges of the lamp power signal. This maintains multiple linear relationships between the full range of varying voltage and said feedback signal, and between that feedback signal and the power consumed by the lamp, so that there is a relationship between the full range of changing voltage and the power consumed by the lamp. Multiple linear relationships.

Alternatively, the DC voltage may be chosen to be a constant DC voltage over the full range of the lamp power signal. This constitutes an inverter in which there is a single linear relationship between the full range of variation of the varying voltage and the feedback signal, and between the feedback signal and the power consumed by the lamp, so that over the full range of variation of the varying voltage There is a single linear relationship with lamp power consumption.

In a preferred embodiment of an inverter according to the invention, the control circuit is formed on an integrated circuit, said integrated circuit including a circuit for limiting the variable voltage between a minimum value and a maximum value Varying voltage clamping circuit. This voltage clamping circuit allows a very precise dynamic range for varying voltages. Another advantage is that if the user inadvertently adjusts the variable voltage to a value that could cause the lamp to go out, the voltage clamp circuit will correct for this and keep the lamp on. Although this varying voltage cannot have a magnitude below the lower limit, it is still possible to regulate the light output of the lamp to very low values due to the presence of a DC bias voltage in the feedback signal.

Said control circuit may include a multiplier for generating a lamp power signal proportional to the product of lamp current and lamp voltage. It has been found that the linearity of the relationship between the varying voltage and the power consumed by the lamp is further improved. Furthermore, it has been found that an inverter equipped with such a control circuit can drive different types of lamps with substantially the same light output, ie the desired lighting conditions can be repeatedly achieved for different types of lamps.

Said control circuit may be formed on an integrated circuit and further comprises a series connection between a DC voltage source and a resistive divider circuit externally connected to the integrated circuit for generating DC bias levels and by means of One pin of the integrated circuit is connected to said multiplier, and the voltage of the pin is used as a feedback voltage. This feedback voltage appears across a first ohmic resistor included in said resistive divider. The voltage portion on the first ohmic resistor generated by the current sent by the DC voltage source is the DC bias voltage. The portion of the voltage across said first ohmic resistor generated by the current delivered by the multiplier is the lamp power signal.

Where a better linear relationship to lamp power consumption over the full range of varying voltage is required, this can be achieved by, for example, connecting a series combination of a diode and a second ohmic resistor in parallel to said first ohmic resistor. achieve this purpose. In the event that the feedback voltage at the pin is such that the diode is turned on, both the current supplied by the DC voltage source and the current supplied through said pin by the multiplier in the integrated circuit flow through said first and second ohmic resistance, resulting in a different linear relationship between the varying voltage and the power consumed by the lamp. In order to establish a better linear relationship, a series combination of a third resistor and another diode or the like can be connected in parallel with the second resistor. By means of such multiple linear relationships, a linear relationship between the required varying voltage and the lamp power consumption can be established.

Description of drawings

In order to understand the present invention more fully, introduce below in conjunction with accompanying drawing, in said accompanying drawing:

Fig. 1 is a schematic block diagram showing a ballast formed according to the present invention;

Fig. 2 is a kind of inverter of the present invention and the schematic diagram of the drive control circuit that it has;

Fig. 3 is a logical block diagram of an integrated circuit as the drive control circuit shown in Fig. 2;

Fig. 4 is a graph showing the relationship between lamp power and dimming control input voltage of different lamps according to the prior art;

5 is a graph showing the relationship between lamp power and dimming control input voltage for different lamps according to the present invention.

Detailed ways

As shown in FIG. 1 , ballast 10 is powered by an AC power line represented by AC source 20 . The ballast 10 includes an EMI (electromagnetic interference) filter 30 , a diode full-wave bridge 40 , a pre-regulator 50 , an inverter 60 and a drive control circuit 65 . The output of the inverter 60, which is the output of the ballast 10, is connected to a load 70 comprising an inductor 75 in series with the parallel combination of a capacitor 80 and a fluorescent lamp 85. EMI filter 30 filters out harmonics generated by pre-regulator 50 and inverter 60 . Diode bridge 40 rectifies the filtered sinusoidal voltage to produce a DC voltage with a pulsating component. The preconditioner 50 has several functions. The rectified peak AC voltage output from the diode bridge 40 is boosted and changed to a substantially constant DC voltage to be supplied to the inverter 60 . Pre-regulator 50 also improves the overall power factor of ballast 10 . For example, 120 volts, 220 volts, and 277 volts RMS applied to EMI filter 30 by AC source 20 generate DC voltages of approximately 250 volts, 410 volts, and 490 volts, respectively, that are supplied to inverter 60 .

Inverter 60 is driven by drive control circuit 65 to convert the DC voltage to a square wave voltage waveform applied to load 70 during full arcing of lamp 85 at a switching frequency of approximately 45 kHz. By decreasing and increasing the frequency of this square wave voltage the brightness of the lamp can be increased and decreased respectively.

Figure 2 shows the inverter 60 and drive control circuit 65 in more detail. A substantially constant voltage VDC generated by the pre-regulator 50 is applied to the inverter 60 via a pair of input terminals 61 and 62 of the inverter 60 . The inverter 60 has a half-bridge structure and includes a B+ (fire wire) bus 101, a ground return bus 102, and a pair of switches (ie power MOSFETs) 100 and 112 connected in series between the bus 101 and the bus 102. Switches 100 and 112 are connected at node 110 and are generally considered to form a single-ended push-pull output circuit configuration. The MOSFETs used as switches 100 and 112 have a pair of gates G1 and G2, respectively. Buses 101 and 102 are connected to inputs 61 and 62, respectively. Resistor 103 and capacitor 106 are connected at node 104 and connected in series between bus 101 and bus 102 . A pair of capacitors 115 and 118 are connected at node 116 and connected in series between node 110 and bus 102 . A Zener diode 121 and a diode 123 are connected at node 116 and connected in series between node 104 and bus 102 .

Inductor 75 , capacitor 80 , capacitor 81 , lamp 85 and a resistor 174 are connected at node 170 . A pair of coils 76 and 77 are coupled to coil 75 for applying a voltage across a filament (not shown) of lamp 85 to regulate lamp 85 during its filament warm-up operation. A DC blocking capacitor 126 and inductor 75 are connected in series between nodes 110 and 170 . Capacitor 80 and a pair of resistors 153 and 177 are connected at node 179 . Lamp 85 and resistor 153 are connected at node 88 and are connected in series between nodes 170 and 179 . Resistors 174 and 177 are connected at node 175 and are connected in series between nodes 170 and 179 . Capacitor 81 and switch (eg MOSFET) 82 are connected in series between nodes 170 and 179 . A resistor 162 is connected between bus 102 and node 179 . Diode 180 and capacitor 183 are connected at node 181 and are connected in series between node 175 and ground.

Integrated circuit (IC) 109 includes a number of pins. Pin RIND is connected to node 179 . The input voltage at pin RIND reflects the value of the current flowing through capacitor 75 (typical example). A pin VDD connected to node 104 provides a voltage for driver IC 109 . Pin LI2 is connected to node 88 through a resistor 168 . Pin LI1 is connected to node 179 through a resistor 171 . The difference between the currents input to pins LI1 and LI2 reflects the sensed current flowing through lamp 85 . The voltage at pin VL connected to node 181 through resistor 189 reflects the peak voltage of lamp 85 . The voltage at pin VL (which is also applied to gate G3 of switch 82 ) controls when capacitor 81 is connected in parallel with capacitor 80 . The current flowing from pin CRECT through the parallel circuit of resistor 195 and capacitor 192 to ground reflects the average power of lamp 85 (ie, the product of lamp current and lamp voltage). An optional external DC bias circuit 198, described in greater detail below, includes a series circuit of VDD and a resistor 199 that directs a DC bias current through a resistor 195 to ground.

Capacitor 192 is used to generate a filtered DC voltage across resistor 195 . A resistor 156 is connected between pin RREF and ground and is used to set a reference current inside IC109. A capacitor 159 connected between pin CF and ground determines the frequency of the current controlled oscillator (CCO) which will be described in greater detail below. A capacitor 165 connected between pin CP and ground is used to determine the timing of the preheat cycle and the non-oscillating/standby mode, which will be discussed below. The pin GND is directly grounded. A pair of pins G1 and G2 are directly connected to gates G1 and G2 of switches 100 and 112, respectively. Pin S1 directly connected to node 110 is used to input the source voltage of switch 100 . Pin FVDD is coupled to node 110 via capacitor 138 and represents the floating supply voltage supplied to IC 109 . Pin G2 is connected to pin DIM through a series circuit of capacitor 215 , resistor 212 and diode 203 . Resistor 206 and capacitor 213 are connected between pin DIM and ground. The secondary winding of transformer T is connected between node 210 connecting resistor 212 to diode 203 and ground. The dimming control circuit 211 is connected to both ends of the primary winding of the transformer T. The voltage applied to the pin DIM reflects the illumination level set by the dimming control circuit 211 .

The working process of the inverter 60 and the drive control circuit 65 will be introduced below. Initially (ie, during start-up), when capacitor 106 charges according to the RC time constant of resistor 103 and capacitor 106, switches 100 and 102 are in off and on states, respectively. The current flowing into pin VDD of IC 109 is maintained at a small value (less than 500 microamperes) during this start-up phase. Capacitor 138 connected between node 110 and pin FVDD is charged to a relatively constant voltage approximately equal to VDD and serves as a voltage source for the drive current of switch 100 . When the voltage across capacitor 106 exceeds a voltage turn-on threshold (e.g., 12 volts), IC 109 enters its operating (oscillating/switching) state, while switches 100 and 112 operate at well above the resonance determined by inductor 75 and capacitor 80, respectively. The frequency switches back and forth between the on state and the off state.

When the inverter 60 starts to oscillate, the IC 109 first enters a warm-up cycle (ie a warm-up state). Depending on the switching state of switches 100 and 112, the voltage at node 110 varies between 0 volts and VDC. Capacitors 115 and 118 are used to slow down the rate at which the voltage at node 110 increases and decreases, thereby reducing switching losses and the level of EMI generated by inverter 60 . Zener diode 121 generates a pulsating voltage at node 116 which is supplied to capacitor 106 via diode 123 . As a result, a relatively large operating current, such as 10-15 mA, is applied to the pin VDD of IC109. Capacitor 126 serves to block the DC voltage component applied to lamp 85 . Pin VL is at a high logic level, which closes switch 82 . At this time, capacitor 81 and capacitor 80 are connected in parallel. The parallel circuit of inductor 75 and capacitors 80 and 81 forms a resonant circuit.

Lamp 85 is not ignited during the preheat cycle, ie no arc is generated within lamp 85 . The initial operating frequency of IC 109 is determined by resistor 156 and capacitor 159 and the reverse diode conduction times of switches 100 and 112, which is approximately 100 kHz. IC109 then reduces the operating frequency at a speed set in the IC. The frequency continues to decrease until the peak voltage across the resistor 162 is detected at one end of the pin RIND to be -0.4V (ie, the negative peak voltage is 0.4V). The switching frequency of switches 100 and 112 is adjusted to maintain a voltage sensed at pin RIND at -0.4 volts, which produces a relatively stable frequency of approximately 80-85 kHz at node 110 (specified as the preheat frequency). A relatively steady RMS current flows from inductor 75 which, through coupling with coils 76 and 77, enables the filament (i.e., cathode) of lamp 85 to be adequately prepared for subsequent ignition of lamp 85 to extend lamp life. The duration of the preheat cycle is determined by capacitor 165 . When capacitor 165 has a value of zero (ie, an open circuit), there is virtually no preheating of the filament, allowing lamp 85 to start operating immediately.

At the end of the preheating process, as determined by capacitor 165 , pin VL asserts a low logic level to open switch 82 . Capacitor 81 is no longer connected in parallel with capacitor 80 . IC 109 now begins sweeping down from the switching frequency at warm-up towards the no-load resonant frequency (ie, the resonant frequency of inductor 75 and capacitor 80 before lamp 85 ignites, eg 60 kHz) at a rate programmed into IC 109 . As the switching frequency approaches the resonant frequency, the voltage across lamp 85 increases rapidly (eg, 600-800 volts peak), and is usually sufficient to ignite lamp 85 . Once lamp 85 is lit, the current flowing through it increases from a few milliamps to hundreds of milliamperes. The current through resistor 153, which is equal to the lamp current, is sensed at pins LI1 and LI2, respectively, from the difference between the currents proportionally determined by resistors 168 and 171. The voltage of lamp 85 , scaled by the voltage divider of resistors 174 and 177 , is converted by diode 180 and capacitor 183 to a DC voltage proportional to the peak voltage of the lamp and sensed at node 181 . The voltage at the node 181 is converted into a current flowing into the pin VL through the resistor 189 .

The current flowing into pin VL is multiplied within IC 109 by the difference current between pins LI1 and LI2 to produce a rectified AC current which flows out of pin CRECT into the parallel circuit of capacitor 192 and resistor 195 . Capacitor 192 and resistor 195 convert the AC rectified current to a DC voltage which is proportional to lamp 85 power. Because there is a feedback circuit/loop inside IC109, the voltage of the pin CRECT is forced to be equal to the voltage of the pin DIM. The adjustment of the power consumed by the lamp 85 is thereby realized.

The desired brightness level of lamp 85 is determined by the voltage at pin DIM. The feedback loop includes a lamp voltage sensing circuit and a lamp current sensing circuit, which will be described in detail later. The switching frequency of the half-bridge inverter 60 is adjusted by the above-mentioned feedback loop, so that the voltage of the pin CRECT is equal to the voltage of the pin DIM. The voltage at pin CRECT varies between 0.3 and 3.0 volts (ie a 1:10 ratio). When the voltage of the pin DIM rises to more than 3.0 volts or drops to less than 0.3 volts, the voltage is clamped at 3.0 volts or 0.3 volts inside the inverter respectively. The voltage of the pin DIM is a DC voltage. A dimming control input voltage of 1-10 volts applied to the DIM control circuit 211 is transformed by the combined circuit of the transformer T, resistors 206 and 212, diode 203 and capacitors 213 and 215 into 0.3-3.0 volts applied to the DIM pin signal of. Transformer T electrically isolates the DC control input signal from the high voltage within inverter 60 . The signal applied to the DIM pin can be generated by different methods, for example, the phase-angle dimming method that cuts off part of the phase of the AC input line voltage. These methods convert the phase angle of the input line voltage cutoff to a DC signal applied to the DIM pin.

The voltage at the CRECT pin is zero when lamp 85 is on. As the lamp current increases, capacitor 192 is charged by a current at pin CRECT proportional to the product of the lamp voltage and lamp current. The switching frequency of the inverter 60 decreases or increases until the voltage of the CRECT pin is equal to the voltage of the DIM pin. When the dimming amount is set to full light output (100%), the capacitor 192 can be charged to 3.0 volts, so the voltage of the CRECT pin rises to 3.0 volts due to the effect of the feedback loop. During the voltage rising process, the feedback loop is in an open state, which will be described in detail below. When the CRECT pin voltage reaches approximately 3.0 volts, the feedback loop is closed. Likewise, when the dimming amount is set to minimum light output, the capacitor 192 can be charged to 0.3 volts, so the voltage at the CRECT pin rises to 0.3 volts due to the feedback loop. Generally, 0.3 volts at the DIM pin is equivalent to 10% of the full light output. For very low light down to 1% of full light output, an external bias circuit 198 can be used such that a DIM pin voltage of 0.3 volts is equivalent to 1% of full light output, whereas this bias circuit would otherwise be disabled. need to use. When the dimming amount is set to minimum light output, the CRECT capacitor charges to 0.3 volts before the feedback loop closes.

Lamps in the prior art are set to low light when ignited, and usually produce an ignited flash. This greater-than-desired flicker results from the application of high power to the lamp for a relatively long and unnecessary time (eg, up to several seconds) after ignition. In this way, prior art ballasts ensure smooth ignition of the lamp. According to the invention, however, the ignition flash can be minimized. At low dimming settings, the duration of the bright light state after ignition is very short, thereby minimizing visual stimulation from unnecessary flashes. Ignition flashes can be substantially avoided by reducing the amount of power applied to lamp 85 using a feedback loop immediately after the ignition process.

Referring now to FIG. 3 , IC 109 includes a power regulation and dimming control circuit 250 . The differential current between pins LI1 and LI2 is applied to active rectifier 300 . The active rectifier 300 utilizes an amplifier with internal feedback instead of a diode bridge to full-wave rectify the AC waveform to avoid the voltage drop normally associated with diodes. Current source 303 , responsive to the output of active rectifier 300 , produces a rectified current ILDIFF representing the current through lamp 85 as one of two input signals applied to current multiplier 306 .

During the preheating period, the P-channel MOSFET 331 is turned on and the N-channel MOSFET 332 is turned off, so that the potential of the pin VL increases to the potential of the pin VDD. When the preheat period ends (eg, 1 second duration), the P-channel MOSFET 331 is turned off and the N-channel MOSFET 332 is turned on, so that the power regulation and dimming control operations of the inverter 60 can be performed. Current flows through pin VL and N-channel MOSFET 332 and is scaled by resistor 333 after the preheating process. The current source (ie, current amplifier) 336 generates a current signal IVL in response to the scaled current from the pin VL. Current clamp 339 limits the maximum value of current signal IVL applied to the other input of multiplier 306 . The current source 309 outputs a current ICRECT in response to the output of the multiplier 306, which is input to the CRECT pin and the non-inverting input terminal of an error amplifier 312 simultaneously. As shown in FIG. 2, the capacitor 192 and the resistor 195 convert the AC rectified current input from the pin CRECT into a DC voltage.

Referring again to FIG. 3 , the DC voltage at the pin DIM is applied to the voltage clamping circuit 315 . The voltage clamping circuit 315 limits the voltage of the pin CRECT between 0.3 and 3.0 volts. The output of the voltage clamp circuit 315 is applied to the inverting input of the error amplifier 312 . The output of the error amplifier 312 controls the magnitude of the current IDIF flowing through the current source 345 . The current comparator 348 compares the current IDIF with a reference current IMIN and a current IMOD, and outputs a current signal of the maximum magnitude. Current IMOD is controlled by a switched capacitor integrator 327 . The current output by current comparator 348 produces a control signal that determines the oscillation (switching) frequency of VCO 318 . When the lamp is ignited, the voltage at the terminal CRECT and the current IDIF are zero. The output of comparator 348 selects a maximum current, ie, IMOD, from among IMIN, IDIF and IMOD. As the voltage at the pin CRECT terminal increases to the voltage at the pin DIM terminal, the current IDIF increases. When current IDIF is greater than current IMOD, the output of comparator 348 is equal to current IDIF.

The feedback loop is centered around the error amplifier 312 and includes components internal or external to IC 109 to make the voltage at pin CRECT equal to the voltage at pin DIM. When the voltage of the pin DIM is less than 0.3V, a DC voltage of 0.3V is applied to the inverting input terminal of the error amplifier 312 . When the voltage of the pin DIM is greater than 3.0 volts, a voltage of 3.0 volts is applied to the error amplifier 312 . The voltage applied to pin DIM should be in the range of 0.3 volts to 3 volts inclusive to achieve the desired 10:1 ratio between the maximum and minimum luminance of lamp 85 . The input current to the multiplier 306 is clamped by the current clamp 339 so that the current input to the multiplier 306 is properly scaled.

The frequency of the CCO 318 controls the switching frequency of the half-bridge inverter 60 according to the output of the comparator 348 . Comparator 348 supplies current IMOD to CCO 318 during warm-up and ignition sweeps. In steady state comparator 348 outputs the IDIF current to CCO 318 . When the comparator 348 outputs a current IMIN, the CCO 318 limits the minimum switching frequency in response to the IMIN current. The minimum switching frequency also depends on capacitor 159 and resistor 156, which are externally connected to IC 109 at pins CF and RREF, respectively. When the voltage at the pin CRECT is equal to the voltage at the pin DIM, the inverter 60 forms a closed-loop operation. The error amplifier 312 adjusts the output current IDIF of the comparator 348 to maintain the voltage at the pin CRECT approximately equal to the voltage at the pin DIM.

A resonant inductor current sense circuit monitors the resonant inductor current, as indicated by the signal at pin RIND, to determine if inverter 60 is in or near a capacitor mode of operation. When the current through inductor 75 leads the voltage across switch 112, inverter 60 is in a capacitive mode of operation. In the near capacitive mode of operation, the current through inductor 75 approaches but does not lead the voltage across switch 112 . For example, given a resonant frequency of about 50 kHz determined by inductor 75 and capacitor 80, when the current through inductor 75 lags the voltage across switch 112 within about 1 microsecond, there is an approximate capacitance Operating mode.

Circuitry 364 also detects whether switch 100 or 110 forms forward conduction or body diode conduction (substrate to drain). When the switch 100 or 112 conducts in the forward direction, the signal IZEROb generated by the resonant inductor current detection circuit 364 (i.e., the signal IZEROb generated at the Q output of the flip-flop 370) is at a high logic level; When the body diode of or 112 conducts, the signal IZEROb generated by the Q output terminal of the flip-flop 370 is at a low logic level. Signal IZEROb is applied to pin IZEROb of CCO318. When the signal IZEROb is at a low logic level, the waveform at the pin CF379 is substantially a constant level. When the signal IZEROb is at a high logic level and the switch 100 is turned on, the voltage at the pin CF increases. When the signal IZEROb is at a high logic level and the switch 112 is turned on, the voltage at the pin CF decreases/drops.

When the switching frequency of the inverter 60 is in the approximately capacitive mode, the signal CM generated by the resonant inductor current detection circuit 364 (ie, the signal CM generated by the OR gate 373 ) is at a high logic level. The switched capacitor integrator 327 increases the output of the current source 329 (ie, the IMOD current) in response to the signal CM having a high logic level. An increase in the magnitude of the IMOD current causes comparator 348 to apply the IMOD current to VCO 318 , causing the switching frequency of inverter 60 to increase. Resonant inductor current sense circuit 364 detects approximately Capacitive working mode. When the sign of the voltage waveform at the pin RIND terminal is + (positive) or the gate pulse G2 is - (negative) during the leading edge of the gate pulse G1 , the inverter 60 is in an approximate capacitive working mode.

NAND gate 376 outputs a CMPANIC signal which is at a high logic level when inverter 60 is operating in capacitive mode. Once the capacitive mode is detected, the value of the IMOD current increases rapidly in response to the sharp increase in the output of the switched capacitor integrator 327 . The VCD 318 relatively instantaneously increases the operating frequency of the inverter to the maximum switching frequency of the inverter 60 according to the IMOD signal, the resistor 156 and the capacitor 159 . Capacitive mode is detected by monitoring the sign (+-) of the voltage waveform at pin RIND during the trailing (falling) edge of each gate drive pulse generated at pins G1 and G2 of IC 109 . When the voltage waveform sign of the pin RIND terminal is - (negative) during the trailing edge of the gate pulse G1 or the voltage waveform sign of the pin RIND terminal is + (positive) during the trailing edge of the gate pulse G2, the inverter 60 It is in capacitive mode of operation.

Circuit 379 sets the time to preheat the filament of lamp 85 and the time to place inverter 60 in a ready-to-operate mode based on the value of capacitor 165 (connected between pin CP and ground). During the preheating period, 2 pulses (duration greater than 1 second) are generated at the pin CP. The switching frequency of the inverter 60 during the warm-up period is about 80 kHz. At the end of the preheat cycle, signal IGNST is a high logic level that initiates ignition from about 80 kHz to about, but higher than, the resonant frequency of inductor 75 and capacitor 85, e.g. The ignition frequency sweep process is carried out at the switching frequency of the resonant frequency of the load. The ignition sweep may be performed at a rate of, for example, 10 kHz/ms.

IC 109 regulates the value of the current flowing through resonant inductor 75, which is sensed at pin RIND. When the voltage at the RIND terminal exceeds 0.4, the signal PC output by the comparator 448 is at a high logic level, so that the output of the switched capacitor integrator 327 adjusts the IMOD value. As a result the RMS switching frequency increases, which reduces the magnitude of the current flowing through resonant inductor 75 . When the voltage at the RIND terminal drops below 0.4, the signal PC is at a low logic level, so that the output of the switched capacitor integrator 327 adjusts the IMOD value to reduce the switching frequency. Accordingly, the current flowing through the resonant inductor 75 is increased. By achieving accurate regulation of the current flow through resonant inductor 75, the voltage across each filament of lamp 85 is substantially constant during preheating. On the other hand, by connecting a capacitor (not shown) in series with each filament, the current through the filament can be kept substantially constant during the preheating process.

Circuit 379 also includes an ignition timer that starts after the warm-up period is complete. Once the timer starts, a pulse is generated at pin CP. If after this pulse it is detected that the inverter is operating in capacitive mode, or if an overvoltage condition across lamp 85 is detected, IC 109 enters a ready-to-operate mode. During the preparation process, VCO 318 stops oscillating, at this time, switches 112 and 100 remain conducting and non-conducting states, respectively. To exit the ready-to-operate mode, the voltage applied to IC 109 (i.e., applied to pin VDD) must decrease to at least a turn-off threshold (e.g., 10 volts) and then increase to at least a turn-on threshold (e.g., 12 volts ).

The preheat timer includes a Schmitt trigger 400 (ie, hysteresis comparator), which determines the trigger point of the CP waveform. These trigger points represent the voltages that are applied to the inputs of the Schmitt trigger 400 in order to trigger the Schmitt trigger 400 on and off. Switch 403 provides a path for capacitor 165 to discharge when in a conductive state. Whenever the Schmitt trigger 400 generates a pulse and for the duration of each pulse, the switch 403 is always on. Whenever the voltage at the pin CP exceeds the upper trigger point determined by the Schmitt trigger 400, the capacitor 165 is discharged. The discharge path includes pin CP, switch 403 and ground. Capacitor 165 is charged by current source 388 . When the capacitive mode of operation indicated by the generation of the CMPANIC signal at NAND gate 376 is detected, switch 392 is turned on. Capacitor 165 is also now charged by current source 391 . When the capacitive mode of operation is detected, the charging current of the capacitor 165 is 10 times that when the capacitive mode of operation is not detected. The time taken for the voltage of the pin CP to reach the upper trigger level of the Schmitt trigger is 1/10 of the time taken when not in the capacitive mode. Therefore, when the capacitive working mode is detected, the duration of the pulse at the pin CP is one-tenth of that when the capacitive working mode is not detected. Therefore, IC 109 enters ready-to-operate mode for a relatively short time whenever the increase in switching frequency does not remove the capacitive mode condition.

The preheat timer also includes a D flip-flop forming counter 397 . The output of NAND gate 406 generates signal COUNT 8b which is at a low logic level at the end of the ignition process. Gate 412 outputs a logic high whenever an overvoltage minimum threshold state across lamp 85 (indicated by signal OVCLK) is detected, or when an inverter capacitive mode of operation is detected (indicated by signal CMPANIC). level. When the output of gate 415 is at a high logic level, switch 403 is turned on, causing capacitor 165 to discharge.

As mentioned above, to achieve power regulation and dimming control, the input current flowing through the pin VL terminal is applied to the multiplier 306 through the current source 336 after the warm-up period. The current input from the pin VL is also supplied to the non-inverting input terminals of the comparators 421 , 424 and 427 through the current source 417 , the current source 418 and the current source 419 , respectively.

Comparator 421 starts the ignition timer once it detects that the lamp voltage has exceeded the overvoltage minimum threshold. When the ignition timer expires, if there is an overvoltage minimum threshold state, IC109 enters the ready-to-work mode. The D flip-flop 430 provides clock synchronization to the output of the comparator 421 at the falling edge of the gate pulse generated by the pin G2. Whenever the overvoltage minimum threshold is exceeded during the first ignition sweep, the logical combination of D flip-flop 433, AND gate 436, and NOR gate 439 causes switch (N-channel MOSFET) 440 to turn on, thereby Blocks ICRECT signaling. Flip-flop 433 has a D input connected to internal node 385 . When the minimum overvoltage condition is detected, the D input of flip-flop 433 assumes a high logic level at the end of the warm-up process. When the input of flip-flop 433D is at a high logic level, its output is at a low logic level, causing the output of gate 439 to switch to a low logic level. Further, the switch 440 is opened, preventing the signal ICRECT from being transmitted to the pin CRECT. Capacitor 192 is discharged through resistor 195 when signal ICRECT is blocked from passing to pin CRECT. A complete discharge would occur if no external bias circuit 198 was used. Partial discharge occurs when biasing circuit 198 as shown in FIG. 2 is used. In either case, the discharge of capacitor 192 reduces the voltage at pin CRECT to ensure that the feedback loop is not closed. During warm-up, the IGNST signal at internal node 385 is at a low logic level. NOR gate 439 will then keep switch 440 open during preheat. No ICRECT signal is applied to error amplifier 312 or out pin CRECT, thereby charging capacitor 192 .

Signal IGNST is at a high logic level once the ignition sweep begins (this process begins immediately after the warm-up process is complete). At this point switch 440 is turned on and remains on during the ignition scan until an overvoltage minimum threshold (e.g. approximately 1/2 of the maximum voltage that is applied to the lamp during ignition) is detected by comparator 421. 85) until the hour. During the ignition sweep, the switching frequency keeps decreasing, causing the voltage across lamp 85 and the sensed lamp current to increase. Signal ICRECT increases in value, which charges capacitor 192, thereby increasing the voltage at pin CRECT. Under low dimming conditions, the voltage at the pin CRECT can be equal to the voltage at the pin DIM. Without the intervention of other signals, the error amplifier will prematurely close the feedback loop before the successful ignition of lamp 85 when it detects that there is no difference between the voltages of the two pins.

To avoid premature closure of the feedback loop, gate 439 will open switch 440 during the ignition sweep and keep switch 440 open until comparator 421 detects the presence of an overvoltage minimum threshold. By preventing the signal ICRECT from being transmitted to the pin CRECT, the voltage at the pin CRECT terminal drops, thereby preventing the voltage at the pin CRECT terminal from being equal to the voltage at the pin DIM terminal even when the pin DIM voltage is set to be extremely weak. Therefore, the feedback loop will not be closed during the ignition sweep, thereby preventing smooth ignition. More preferably, switch 440 is opened only once during ignition, starting when the lamp voltage reaches the overvoltage minimum threshold, and continuing until lamp 85 is ignited. While switch 440 is open, capacitor 192 can discharge sufficiently through resistor 195 to ensure that the feedback loop does not close prematurely during the ignition sweep.

In order to ignite the lamp smoothly, the prior art ballast driver applies a relatively high power to the lamp for an unnecessarily long time (eg, up to several seconds). Applying relatively high power to the lamp for an unnecessarily long period of time can result in a condition known as ignition flash if an attempt is made to start the lamp at a lower intensity. In this state, a flash of light much larger than required appears.

In the inverter shown in Figure 2, the ignition flicker has been substantially eliminated, ie made so small that it cannot be perceived. By avoiding application of relatively high power to lamp 85 for unnecessarily long periods of time, substantial elimination of ignition flash is achieved. More specifically, relatively high power is applied to lamp 85 for only about 1 millisecond or less before the power amplitude is reduced to the magnitude after lamp ignition. This momentary reduction in lamp power is accomplished by monitoring the overvoltage condition, particularly when the lamp voltage drops below the overvoltage minimum threshold (as determined by comparator 421 ) before allowing switch 440 to close again. status achieved. When the lamp 85 is successfully ignited, the lamp power immediately drops below the overvoltage minimum threshold. In other words, under low light conditions where ignition flicker could occur, ignition can be avoided by first detecting when the lamp voltage reaches and/or exceeds the overvoltage minimum threshold, and then detecting when the lamp voltage drops below the overvoltage minimum threshold flash.

Comparator 424 asserts a high logic level when the lamp voltage exceeds the overvoltage maximum threshold (eg, twice the overvoltage minimum threshold). When the output of comparator 424 is at a high logic level and no near-capacitive mode is detected, switched capacitor integrator 327 is responsive to the signal output by flip-flop 445 at a high logic level (i.e., at a high logic level). The Q output of the D flip-flop 445 of FI (Frequency Increase) increases the oscillation frequency of the VCO 318 at a fixed rate (for example, a sweep rate of 10 KHz/ms), thereby increasing the switching frequency. So the time interval of the switching cycle of the inverter 60 is reduced. When the output of comparator 424 is at a high logic level and a near-capacitive mode is detected, switched capacitor integrator 327 responds to the output of NAND gate 442 at a high logic level (i.e., output by NAND gate 442 at a high logic level). The signal FSTEP (frequency step)) immediately (for example, within 10 microseconds) increases the oscillation frequency of the VCO318 and thus the switching frequency to its maximum value (for example, 100 kHz). The switching period of inverter 60 is then reduced to its minimum time interval (eg, 10 microseconds) in response to the output of VCO 318, which is now at its maximum oscillation frequency value.

When the lamp voltage exceeds an overvoltage protection threshold (ie, greater than the maximum overvoltage threshold), the output of the comparator 427 is logic high. When the output of the comparator 427 is at a high logic level, the switched capacitor integrator 327 responds to the output of the NAND gate 442 at a high logic level (i.e., the signal FSTEP (frequency step) output by the NAND gate 442 at a high logic level ) And immediately increase the switching frequency of VCO318 to its maximum value.

Gate drive circuits 320 are well known in the art and are more fully described in US Patent No. 5,373,435. The description of the gate drive circuit in US Patent No. 5,373,435 is incorporated herein by reference. Pins FVDD, G1, S1 and G2 of IC 109 correspond to nodes P1, P2, P3 and GL shown in FIG. 1 of US Patent No. 5,373,435. The signals G1L and G2L shown in FIG. 3 of the present application correspond to the terminal INL in US Patent No. 5,373,435 and the signal generated between the controller and the level shifter when a higher drive DU is applied, respectively.

Power regulator 592 includes a bandgap regulator 595 that produces an output voltage of approximately 5 volts. Voltage regulator 595 is substantially stable over a wide range of temperature and supply voltage (VDD). The output of the Schmitt trigger (ie, hysteresis comparator) 598, known as the LSOUT (low supply output) signal, is used to identify the state of the supply voltage. When the input supply voltage at pin VDD exceeds a turn-on threshold (eg, 12 volts), the LSOUT signal is at a low logic level. When the input supply voltage of the pin VDD drops below a cut-off threshold (eg, 10 volts), the LSOUT signal is at a high logic level. During startup, the LSOUT signal is at a high logic level, which sets the output of latch 601 (ie, the signal referred to as STOPOSC) to a high logic level. VCO 318 stops oscillating in response to a STOPOSC signal at a high logic level and sets the voltage at pin CF equal to the output voltage of bandgap regulator 595 .

When the supply voltage at pin VDD exceeds the turn-on threshold, the LSOUT signal assumes a low logic level. At this time, the STOPOSC signal is at a low logic level. In response to the STOPOSC signal at a low logic level, VCO 318 drives inverter 60 to oscillate at the switching frequency described herein, applying a substantially trapezoidal waveform to pin CF. When the pin VDD voltage drops below the cut-off threshold and the gate drive voltage of the pin G2 becomes a high logic level, the VCO318 stops oscillating. Switches 100 and 112 remain in their off and on states, respectively.

When the output of the NOR gate 604 is at a high logic level, the output of the latch 601 is also at a high logic level, which causes the VCO 318 to stop oscillating and enter the ready-to-operate mode. After the ignition process is complete, the output of NOR gate 604 (represented as NOIGN signal) assumes a high logic level when it is detected that the lamp 85 is in an overvoltage state or that the inverter is in a capacitive operating mode. One of these states will occur when lamp 85 is removed from the circuit. When lamp 85 fails to ignite, an overvoltage condition will result.

The VL pin is used to regulate the lamp power to protect the lamp from overvoltage, and provides an output drive signal to distinguish between preheat regulation and normal regulation. The input signal at pin VL is a current proportional to the lamp voltage (eg peak or rectified average). The VL pin current enters the multiplier 306 which produces a signal representing the product of the lamp current and the lamp voltage and is used, as described above, to regulate lamp power. The VL pin current also enters comparators 421, 424 and 427 for detecting overvoltage conditions. However, during the preheat cycle, since a full arc discharge does not yet exist within lamp 85, there is no need to detect an overvoltage condition. During the warm-up period, the operating frequency of the inverter 60 is much higher than the resonant frequency of the LC resonant circuit of the unloaded inductor 75 and capacitor 80 . This extremely high frequency during preheating results in a relatively low voltage across lamp 85 which will not damage ballast 10 or lamp 85 components.

During the preheating process, the P-channel MOSFET 331 is turned on and the N-channel MOSFET 332 is turned off, so that the VL pin has the same voltage as the VDD pin. So the VL pin is at a high logic level during warm-up, and at a low logic level during other conditions (such as during ignition and steady state). These two logic levels of the VL pin can distinguish whether the inverter 60 is working in a preheating or non-preheating mode.

A high logic level on the VL pin during the preheat cycle turns on the N-channel MOSFET switch 82 . At this time, capacitor 81 is connected in parallel with capacitor 80 . The addition of capacitor 81 lowers the resonant frequency at no load, which results in a lower voltage being applied across lamp 85 during the preheat cycle. Once the preheat cycle is complete, switch 82 is turned off by a low logic level at the VL pin. At this time, capacitor 81 is no longer connected in parallel with capacitor 80 . The unloaded resonant frequency is increased and can be more easily approached during the ignition sweep. A sufficiently high voltage can thus be applied across the lamp 85 to ignite it.

During the preheat cycle, IC 109 need not sense the voltage across lamp 85 represented by the voltage at pin VL. Therefore, the VL pin is used to drive the switch 82 into the conduction state during the preheating period. After the preheat period, overvoltage conditions and lamp power need to be monitored, which requires detection of the lamp voltage represented by the voltage at pin VL. At this point the VL pin voltage is at a low logic level, typically in the range of 0-800 millivolts, which causes switch 82 to be turned off. Therefore, the logic level of the VL pin (it indicates whether the IC109 is working in the preheating mode) is used to control the operation of the resonant circuit. The VL pin can also be used to control the switching between active and inactive states of other devices located outside of IC 109 to affect the performance of inverter 60 or lamp 85 during and after the preheat state.

Referring now to FIG. 4, a plot of lamp power versus dimming control input signal illustrates the non-repeatability of prior art ballast driving methods. Curves 90, 92 and 94 represent fluorescent lamps containing different noble gases and/or having different diameters. Curves 90 and 92 or curves 90 and 94 represent substantially different lamp powers for the same dimming control input voltage. The required repeatability of ignition conditions cannot be consistently and reliably achieved with the same dimming control input for different types of lamps powered by the same ballast. Furthermore, these prior art ballast drivers do not regulate well in very low light conditions, ie down to 1% to 3% of full light output. Indeed, none of the three lights can reach below 20% of full light output.

On the contrary, as shown in Fig. 5, the present invention provides excellent repeatability and easy adjustment of extremely low light conditions. All three curves have essentially the same lamp power at the same dimming control input voltage. All three lights can also be operated at very low light levels, that is, as low as 1% of full light output. Additionally, each curve is essentially linear, which makes it relatively easy to adjust lamp power in extremely low-light conditions.

It is now easy to understand that dimming can be adjusted for as low as 1% to 3% of full light output. With the help of a relatively good linear relationship between the external dimming control signal and the lamp power, the adjustment under such low light conditions is realized. The ballast 10 can also drive different types of lamps at substantially the same level of light output, ie, with the repeatability of the desired brightness for different types of lamps. This adjustability and repeatability is achieved by driving the inverter based on actual lamp power consumption rather than only approximate lamp power consumption as in the prior art.

Claims (8)

1. inverter that is used to drive the load that comprises a lamp, it comprises:

Switching device, it responds drive signal, be used between conducting and off-state, switching, thus with electric power transmission to said load, on said lamp, apply a voltage and make electric current through said lamp and

Be used to produce the control circuit of drive signal, it comprises an amplifier, be used for a feedback signal and a variation electricity are being compared, said feedback signal is to produce according to the lamp power signal of representing the quantity of power that said lamp consumed, said variation voltage is represented the scope of the required lamp power value of the high-high brightness from a minimum low light level value to full lamp power, it is characterized in that said control circuit is arranged such that operationally said feedback signal is a dc offset voltage and said lamp power signal sum.

2. a kind of inverter as claimed in claim 1 is characterized in that said dc offset voltage is a constant DC voltage.

3. a kind of inverter as claimed in claim 1 or 2, it is characterized in that said control circuit is formed on the integrated circuit, and said integrated circuit comprises that one is used for the voltage clamping circuit of said variation voltage limit between a lower limit and upper limit.

4. a kind of inverter as claimed in claim 1 or 2 is characterized in that said control circuit comprises a multiplier, is used to produce a lamp power signal that is proportional to lamp current and modulating voltage product.

5. a kind of inverter as claimed in claim 4, it is characterized in that said control circuit is formed on the integrated circuit, and comprise the tandem compound of a direct voltage source and resistor voltage divider circuit, said resistor voltage divider circuit is external in said integrated circuit, be used to produce dc offset voltage, and a pin by said integrated circuit links to each other with said multiplier, and the voltage of said pin is as feedback voltage.

6. a kind of inverter as claimed in claim 5, one first ohmic resistor that it is characterized in that being comprised in said resistor voltage divider circuit is in parallel with the tandem compound of being made up of a diode and one second ohmic resistor.

7. a kind of inverter as claimed in claim 1, it is characterized in that said control circuit operationally is arranged such that between whole excursions of said variation voltage and said feedback signal and all only has one or more linear relationships between feedback signal and lamp consumed power, thereby make and between whole excursions of said variation voltage and said lamp consumed power, only have one or more linear relationships.

8. a kind of inverter as claimed in claim 2, it is characterized in that said control circuit operationally is arranged such that between whole excursions of said variation voltage and said feedback signal and all has single linear relationship between feedback signal and lamp consumed power, thereby make and between whole excursions of said variation voltage and said lamp consumed power, have single linear relationship.

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