CN114698259B

CN114698259B - Package structure of radio frequency front end module board level system and package method thereof

Info

Publication number: CN114698259B
Application number: CN202110129853.5A
Authority: CN
Inventors: 黄河; 向阳辉; 刘孟彬
Original assignee: Ningbo Semiconductor International Corp
Current assignee: Ningbo Semiconductor International Corp
Priority date: 2020-12-30
Filing date: 2021-01-29
Publication date: 2024-05-28
Anticipated expiration: 2041-01-29
Also published as: CN114698259A

Abstract

The invention provides a radio frequency front end module board-level system packaging structure and a board-level system packaging method thereof, wherein the board-level system packaging method comprises the following steps: providing a circuit board, wherein a plurality of first welding pads are formed on the surface of the circuit board, and the first welding pads are recessed on the surface; providing a radio frequency chip, wherein the radio frequency chip comprises at least one filter chip, a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip; bonding at least one radio frequency chip on the circuit board, wherein a second welding pad of the at least one radio frequency chip is opposite to a corresponding first welding pad on the circuit board to form a gap; and forming a first conductive bump in the gap through an electroplating process to electrically connect the first bonding pad and the second bonding pad. The conductive bump is formed through an electroplating process, is compatible with the process of the packaging front section, and can realize the system-in-package process of the radio frequency front end module board level by utilizing the traditional chip manufacturing process or the wafer-level packaging process.

Description

Package structure of radio frequency front end module board level system and package method thereof

Technical Field

The invention relates to the field of semiconductor device manufacturing, in particular to a radio frequency front end module board-level system packaging structure and a packaging method thereof.

Background

The system-in-package employs any combination of a plurality of active components/devices, passive components/devices, MEMS devices, discrete KGD (Known Good Die) such as optoelectronic chips, biochips, etc. having different functions and fabricated using different processes, are integrally assembled in three dimensions (X-direction, Y-direction, and Z-direction) into a single standard package having a multi-layered device structure, and can provide multiple functions to form one system or subsystem.

In the prior art, a radio frequency Chip module is generally packaged by adopting a Flip Chip (FC) welding process which is relatively commonly used at present, and the system-in-package method comprises the following steps: providing a PCB, wherein solder balls (formed by a ball-planting process) arranged according to certain requirements are formed on the PCB; dipping soldering flux on the circuit board, and then flip-mounting the chip on the circuit board; a solder pad (pad) on the chip is electrically connected with a solder ball on the circuit board after being welded by a reflow soldering process; and then filling glue between the bottom of the chip and the circuit board so as to increase the mechanical strength of the whole structure.

However, the existing system-in-package method has the following disadvantages: 1. the process is complex, and the packaging efficiency is low; 2. each chip needs to be welded on the solder balls in sequence, and the packaging efficiency is low; 3. the electric connection between the chip and the PCB is realized by utilizing a welding process, and the chip and the PCB cannot be compatible with the process of the front section of the package; 4. the circuit board is easy to be broken when a large pressure is applied by a little careless in the process of dipping the soldering flux. The method is applied to system integration of the plate radio frequency front end module, and can cause the problems of low packaging efficiency and low yield.

Disclosure of Invention

The invention aims to solve the problems that the existing radio frequency front end module board pole system has low packaging efficiency, cannot be compatible with the front-end chip forming process and the like.

In order to achieve the above objective, the present invention provides a method for packaging a board level system of a radio frequency front end module, comprising: providing a circuit board, wherein a plurality of first welding pads are formed on the surface of the circuit board, and the first welding pads are recessed on the surface; providing a radio frequency chip, wherein the radio frequency chip comprises at least one filter chip, other radio frequency chips comprise at least one function of signal amplification, signal reception and signal tuning, a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip; bonding at least one radio frequency chip on the circuit board, wherein a second welding pad of the at least one radio frequency chip is opposite to a corresponding first welding pad on the circuit board to form a gap; and forming a first conductive bump in the gap through an electroplating process to electrically connect the first bonding pad and the second bonding pad.

In order to achieve the above object, the present invention further provides a board-level system packaging structure of a radio frequency front end module, including: the circuit board is provided with a plurality of first welding pads on the surface, and the first welding pads are recessed on the surface of the circuit board; the radio frequency chip comprises at least one filter chip, other radio frequency chips comprise at least one function of signal amplification, signal reception and signal tuning, a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip; at least one radio frequency chip is bonded on the circuit board, and a first electroplated conductive bump is formed between a second bonding pad of the radio frequency chip and a corresponding first bonding pad on the circuit board so as to electrically connect the first bonding pad and the second bonding pad.

The invention has the beneficial effects that:

The invention completely avoids the traditional packaging process of realizing the electric connection of the radio frequency chip and the circuit board by utilizing welding on the PCB, and forms the first conductive bump by an electroplating process so as to realize the electric connection of the radio frequency chip and the circuit board. Firstly, compared with the traditional packaging technology, the technology has simple technological process and high packaging efficiency; secondly, after all chips are bonded on the circuit board, the electric connection between each chip and the circuit board is formed through an electroplating process, and compared with the traditional method that each chip is independently welded and electrically connected with the circuit board, the packaging efficiency is greatly improved. Third, the electroplating process is compatible with the process of the packaging front section, and the conventional chip manufacturing process or wafer level packaging process can be utilized to realize the board level system level packaging process.

Furthermore, the radio frequency chip and the circuit board are physically connected through the photoetching bonding material, and the photoetching bonding material covers the peripheral area of the first conductive bump, so that the mechanical strength of the whole structure is directly enhanced, and the filling and glue filling process in the prior art can be omitted. And when the plastic packaging process is carried out subsequently, the plastic packaging material does not need to fill a gap between the radio frequency chip and the circuit board, so that the time of the plastic packaging process is saved. In addition, the photoetching bonding material of the dry film material can be easily deformed without damage when being subjected to thermal stress due to the small elastic modulus, so that the bonding stress of the radio frequency chip and the circuit board is reduced. Further, the photo-bondable material may define the location of the first conductive bump, preventing the first conductive bump from laterally overflowing during the electroplating process.

Further, when the areas of the opposite parts and the staggered parts of the first welding pad and the second welding pad are larger than one half of the area of the first welding pad or the second welding pad, the electroplating process can be better realized, so that the formed first conductive bump is filled in the gap as completely as possible, and the increase of resistance caused by the too small contact area of the formed first conductive bump and the welding pad is avoided; on the other hand, the staggered parts can be more easily contacted with the electroplating solution, so that the problem that the electroplating solution is not easy to flow into the gaps due to small gaps, and the first conductive bumps which are relatively good cannot be formed can be avoided.

Further, when the height of the gap is 5-200 micrometers, the problem that the electroplating time is long due to the fact that the electroplating liquid easily enters the gap to perform electroplating is solved, and therefore the electroplating efficiency and the electroplating yield are both achieved.

Furthermore, as a welding process is not needed, the solder resist and the soldering flux are not needed to be formed on the circuit board, and the solder resist and the soldering flux can be organic medium layers with photoetching bonding characteristics or inorganic medium layers, so that the forming efficiency of the circuit board is improved, and the process is saved. When the top layer is an organic medium layer with photoetching bonding characteristics, the organic medium layer with a certain thickness can be selected according to the requirement, so that the radio frequency chip can be conveniently bonded onto the circuit board in the follow-up process, and a bonding layer is not required to be additionally formed. When the top layer is an inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is small, the electroplating solution is easier to enter the gaps, and the formation yield of the first conductive bumps is improved.

Furthermore, a cavity is formed at least below the filter chip, and can be used as an upper cavity of the filter chip, so that the filtering performance of the filter is improved; further, it is unnecessary to form an upper cavity in the filter, and the thickness of the filter chip can be reduced.

Furthermore, the front and the back of the circuit board are bonded with radio frequency chips and/or the radio frequency chips can be stacked and bonded, so that the integration level of the radio frequency front end module is further improved, and the area of the module is reduced.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 to 5 are schematic structural diagrams illustrating different steps in a method for packaging a board level system of a radio frequency front end module according to a first embodiment of the present invention;

FIG. 6 is a schematic diagram of a board-level system package of a radio frequency front end module according to a second embodiment of the present invention;

FIG. 7 is a schematic diagram of a board-level system package of a radio frequency front end module according to a third embodiment of the present invention;

FIG. 8 is a schematic diagram of a board level system package of a radio frequency front end module according to a fourth embodiment of the present invention;

FIG. 9 is a schematic diagram of a board-level system package structure of a radio frequency front end module according to a fifth embodiment of the present invention;

FIG. 10 is a schematic diagram of a board-level system package structure of a RF front-end module in a sixth embodiment of the present invention;

FIG. 11 is a schematic diagram of a board-level system package of a RF front-end module according to a seventh embodiment of the invention;

FIG. 12 is a schematic diagram of a board-level system package of a radio frequency front end module according to an eighth embodiment of the present invention;

FIG. 13 is a schematic diagram of a board-level system package of a radio frequency front end module according to a ninth embodiment of the present invention;

Fig. 14 to 17 show corresponding structural schematic diagrams in different steps in the circuit board forming process according to the eleventh embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a board-level system packaging method of a radio frequency front-end module, which comprises the following steps:

Providing a circuit board, wherein a plurality of first welding pads are formed on the surface of the circuit board, and the first welding pads are recessed on the surface; providing radio frequency chips, wherein at least one radio frequency chip is a filter chip, and other radio frequency chips comprise at least one function of signal amplification, signal reception and signal tuning, wherein a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip; bonding at least one radio frequency chip on the circuit board, wherein the second welding pad and the corresponding first welding pad on the circuit board are opposite to form a gap; and forming a first conductive bump in the gap through an electroplating process so as to electrically connect the first welding pad and the second welding pad.

The invention completely avoids the traditional packaging process of realizing the electric connection of the chip and the circuit board by utilizing welding on the PCB, and forms the conductive bump by an electroplating process so as to realize the electric connection of the radio frequency chip and the circuit board. Firstly, compared with the traditional packaging technology, the technology has simple technological process and high packaging efficiency; secondly, after all the radio frequency chips are bonded on the circuit board, the electric connection between each chip and the circuit board is formed through an electroplating process, and compared with the traditional method that each chip is independently welded and electrically connected with the circuit board, the packaging efficiency is greatly improved. And thirdly, the electroplating process is compatible with the process of the packaging front section, the conventional chip manufacturing process or wafer level packaging process can be utilized to realize the board level system level packaging process, and finally the packaging efficiency and the product yield of the radio frequency front end module are improved.

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Example 1

The embodiment 1 of the present invention provides a board-level system integration method of a radio frequency front end module, and the system integration method is described with reference to fig. 1 to 5.

Referring to fig. 1, a circuit board 10 is provided, the circuit board 10 having a front surface and a rear surface, the front surface being formed with a plurality of first pads 11, the first pads 11 being recessed in the front surface. The first PAD 11 may be a PAD (PAD), but is not limited to a PAD, and may be other conductive blocks having an electrical connection function.

The circuit board 10 includes: at least one layer 12, each layer 12 at least comprises a substrate and an interconnection structure on the surface of the substrate, and the first bonding pad 11 is located on the top layer and is electrically connected with the interconnection structure. The circuit board 10 is a printed circuit board, namely a PCB board, and the circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc., and specifically, the number of layers of the circuit board 10 can be determined according to actual requirements. In this embodiment, the circuit board 10 is a three-layer board, each layer board 12 includes an interconnection structure 14 on the surface of the substrate, and an interconnection plug 15 electrically connected to the interconnection structure 14, the interconnection plug 15 includes a via hole and a conductive layer plated on the surface of the via hole, and the via hole is filled with an insulating resin. Or the through holes can be filled with conductive resin, so that the process of forming the conductive layer is saved. In the invention, whether each layer board contains the interconnection plug and the interconnection structure or not can be determined according to actual requirements, and only the interconnection structure can be provided, and no interconnection plug is provided. In the present invention, the circuit board is not limited to the PCB board, but may be other forms of circuit boards, such as a ceramic circuit board.

In the prior art, the top layer of the circuit board is a solder mask layer and a soldering flux layer, and the solder mask layer covers the top surface of the circuit board and exposes the bonding pads. In the invention, the top layer of the circuit board can be the same as the prior art, and the top surface is provided with a solder mask layer and a solder mask; in the invention, the electric connection between the radio frequency chip in the radio frequency front end module and the circuit board is not needed to be realized through welding, so that the top surface can be provided with no solder mask (green oil) or no soldering mask. The top layer may be a first organic dielectric layer 13 having photolithographic bonding characteristics, and the first pad 11 is buried in the first organic dielectric layer 13 and partially exposed. When the top layer is the first organic medium layer with photoetching bonding characteristics, the first organic medium layer with a certain thickness can be selected according to the requirement, so that the radio frequency chip can be conveniently bonded onto the circuit board later, and a bonding layer is not required to be additionally formed, thus the process can be saved, and the forming efficiency of the circuit board is improved. The top layer can also be a first inorganic medium layer, when the top layer is an inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is small, the electroplating solution can enter the gap more easily, and the formation yield of the first conductive bump is improved; in addition, the formation of a soldering-assisting layer and a soldering-resisting layer is not needed, so that the process can be saved, and the formation efficiency of the circuit board is improved.

Referring to fig. 2 and 3, a plurality of radio frequency chips are provided, including at least a filter chip 301, a radio frequency chip 302 having a power amplifying function, a radio frequency chip 303 having a signal receiving and/or transmitting function, and a radio frequency chip 304 having a signal tuning function. A second bonding pad 31 is formed on one surface of the filter chip 301 and the other radio frequency chips 302, 303 to 304, and the second bonding pad 31 is recessed on the surface; typically, the surface containing the second pads 31 is the front surface of the chip, but may be the back surface of the chip, and each rf chip may contain a conductive through-chip via, such as a through-silicon via (Through Silicon Via, abbreviated as TSV), to which the second pads 31 are electrically connected. In some embodiments, the second pads 31 may be formed on two opposite side surfaces of the rf chip, and the second pads 31 on two sides may be interconnected by conductive vias in the chip, or respectively connected to interconnection lines in the chip.

The filter chip 301 may include: at least one of a surface acoustic wave filter (SAW) chip or a bulk acoustic wave filter (BAW) chip, wherein the bulk acoustic wave resonator may be an FBAR, which is a filter having cavities on both upper and lower sides of a resonant unit, or an SMR, which is a bragg reflection layer on the bottom surface of the resonant unit, and an upper cavity on the other side. In this embodiment, the filter chip 301 is an FBAR bulk acoustic wave filter, and a lower cavity 3011 and an upper cavity 3012, and a resonant film 3013 disposed between the lower cavity 3011 and the upper cavity 3012 are formed therein. The filter chip 301 may be a saw filter chip that is only required to have an upper cavity or a lower cavity.

The radio frequency front end module can be a module suitable for a signal receiving end or a signal transmitting end, or can be a radio frequency front end module integrated with the transmitting end and the receiving end. According to different use scenes of the radio frequency front end module, a radio frequency chip with proper functions can be selected. The filter chip 302 having the power amplifying function may include: at least one of a Power Amplifier (PA) chip and a Low Noise Amplifier (LNA) chip; the radio frequency chip 303 having a signal receiving and/or transmitting function may include: an antenna chip, etc.; the rf chip 304 with signal tuning function may include: a tuner chip. The radio frequency chip may further include a duplexer chip, a multiplexer chip, a radio frequency switch chip, an envelope tracker chip, a radio frequency receiver, and other functional chips, which are not listed here, and a person skilled in the art may select a suitable radio frequency chip to integrate according to a specific functional architecture of the radio frequency front end module to be integrated. In this embodiment, only the filter chip 301 and the radio frequency chips 302 to 304 are shown as examples.

The filter chip 301 and the radio frequency chips 302 to 304 may include at least one of a bare chip, a plastic-encapsulated layer, a shielding layer on a top surface, and an interconnection via structure formed through the chip. The radio frequency chips with different functions have different structural characteristics correspondingly, and are not limited herein. In some embodiments, a single rf chip may further have a plurality of rf devices integrated therein, or the single rf chip may be an rf chip module packaged by a plurality of rf devices or bare chips.

The filter chip 301 and the rf chips 302-304 are bonded to the circuit board 10, and the first bonding pad 11 and the second bonding pad 31 are opposite to each other to form a gap 32. The void 32 is ready for a subsequent electroplating operation, in which a first conductive bump is subsequently formed to electrically connect the first pad 11 and the second pad 31.

With continued reference to fig. 2 and 3, in this embodiment, the radio frequency chip is bonded to the circuit board 10 by the lithographically bondable material 20, and the lithographically bondable material 20 is disposed away from the first pads 11. The lithographically bondable material 20 may be formed on the circuit board 10, on the rf chip, or on both the rf chip and the circuit board 10.

In this embodiment, the lithographically-bondable material 20 is formed on the circuit board 10. The specific method comprises the following steps: forming a lithographically bondable material on the surface of the circuit board; patterning the lithographically bondable material to form openings to expose the first pads 11; the radio frequency chips 301 to 302 are bonded together with the circuit board 10 by the lithographically bondable material. The photoetching bonding material can be a liquid dry film or a film dry film. The liquid dry film may be spin-coated on the surface of the circuit board 10 and then subjected to a patterning process. The film-like dry film may be coated on the surface of the circuit board 10 and then subjected to a patterning process.

The region of the periphery of the first conductive bump formed later is covered by the photo-bondable material 20, that is, the forming position of the first conductive bump is defined, that is, the photo-bondable material encloses the boundary of the void 32, and the first conductive bump formed later cannot exceed the boundary, so that the electroplating process can be controlled conveniently. Because the radio frequency chips and the circuit board 10 are physically connected through the photoetching bonding material 20, and the photoetching bonding material covers the peripheral area of the first conductive bump, the mechanical strength of the whole structure is directly enhanced, and the filling and glue filling process in the prior art can be omitted. And when the plastic packaging process is carried out subsequently, the plastic packaging material does not need to fill a gap between the radio frequency chip and the circuit board, so that the time of the plastic packaging process is saved. In addition, the photoetching bonding material of the dry film material can be easily deformed without damage when being subjected to thermal stress due to the small elastic modulus, so that the bonding stress of the radio frequency chip and the circuit board is reduced.

In the embodiment of the invention, the thickness of the photoetching bonding material is 5-200 mu m, and the photoetching bonding material at least covers 10% of the area of each radio frequency chip, so that the bonding strength between the radio frequency chip and the circuit board can be ensured.

In the embodiment of the present invention, the first organic medium layer 13 may be a lithographically bondable material, in which case the lithographically bondable material 20 need not be formed separately, thereby saving the process.

Referring to fig. 4, a first conductive bump 40 is formed in the gap 32 (please refer to fig. 3) through an electroplating process to electrically connect the first pad 11 and the second pad 31.

In the present invention, the plating process includes electroless plating. The plating solution used in the electroless plating is determined according to the material of the conductive bump and the materials of the first welding pad and the second welding pad which are actually required to be formed. The material of the first and second pads 11 and 31 is selected from any one of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium, or any combination thereof. The material of the first conductive bump includes: copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium, or any combination thereof. In alternative embodiments, the height of the first conductive bump is 5-200 μm, such as 10 μm, 50 μm, 100 μm. When the height of the first conductive bump, namely the gap, is 5-200 mu m, the problem that the electroplating time is long due to the fact that the electroplating liquid easily enters the gap to carry out electroplating is solved, and the electroplating efficiency and the electroplating yield are both considered.

Optionally, electroless palladium plating and gold leaching are carried out, wherein the time for electroless nickel is 30-50 minutes, the time for electroless gold is 4-40 minutes, and the time for electroless palladium is 7-32 minutes; or electroless nickel gold, wherein the electroless nickel time is 30-50 minutes and the electroless gold time is 4-40 minutes.

When electroless palladium immersion gold (ENEPIG) or electroless nickel gold (eneig) is selected for the electroplating process, the process parameters can be referred to in table 1 below.

TABLE 1

Before electroless plating, the surface of the bonding pad can be cleaned to remove a natural oxide layer on the surface of the bonding pad and improve the surface wettability (wetabilities) of the bonding pad in order to better complete the electroplating process; then, an activation process can be performed to promote nucleation growth of the plating metal on the to-be-plated metal.

In order to better implement electroplating, to form the relatively perfect first conductive bump 40, the first and second pads should also be disposed to meet certain requirements, such as: the exposed area of the first welding pad or the second welding pad is 5-200 square micrometers, and in the range, the welding pad can be fully contacted with the electroplating liquid, so that the problem that the contact between the conductive bump and the welding pad is influenced due to insufficient contact between the welding pad and the electroplating liquid, such as the influence of the contact area on the resistance due to too small contact area or poor electrical contact due to the fact that the contact cannot be performed is avoided; in addition, the contact area can be ensured not to be too large so as not to reduce the electroplating efficiency and not to occupy too many surfaces.

The cross section area of the formed first conductive bump is larger than 10 square micrometers, so that the occupied area of the first conductive bump can be prevented from being too large, and the bonding strength between the first conductive bump and the welding pad can be ensured.

In order to perform the electroplating process better, the opposite bonding pads may be designed, and in this embodiment, the first bonding pad 11 and the second bonding pad 31 opposite to each other include a facing portion and a staggered portion, and the area of the facing portion is greater than one half of the area of the bonding pad. When the areas of the opposite parts and the staggered parts of the first welding pad and the second welding pad are larger than one half of the area of the welding pad, the electroplating process can be better realized, so that the formed conductive convex blocks are filled in the gaps as completely as possible, and the increase of resistance caused by the too small contact area of the formed conductive convex blocks and the welding pad is avoided; on the other hand, the staggered parts can be more easily contacted with the electroplating solution, so that the problem that the electroplating solution is not easy to flow into the gaps due to small gaps, and a relatively intact conductive bump cannot be formed can be avoided.

In an alternative, the material of the first conductive bump is the same as that of the second pad and the first pad, so that the first conductive bump is easier to form in the void. Of course, the materials of the first bonding pad and the second bonding pad may be different from those of the conductive bump, and in order to facilitate the subsequent formation of the first conductive bump, a material layer may be formed on the first bonding pad or the second bonding pad, where the material of the material layer is the same as that of the first conductive bump, and a method for forming the material layer may be a deposition process.

In other embodiments, a part of the rf chip may be bonded to the circuit board by flip-chip bonding, and the second bonding pad of the rf chip and the first bonding pad on the circuit board may be electrically connected by soldering, as required.

Referring to fig. 5, a molding layer 50 is formed, and the molding layer 50 covers the circuit board 10 and the individual radio frequency chips 301 to 304 bonded thereon.

In this embodiment, each rf chip is a bare chip that needs to be protected by a plastic layer 50. In other embodiments, if the rf chips are covered with a plastic layer, for example, the rf chips are packaged chips, the plastic layer 50 may not be formed in the present invention.

Specifically, the plastic layer 50 may be formed through an injection molding process. The filling performance of the injection molding process is good, and the injection molding agent can be filled between the radio frequency chips better, so that the packaging effect is improved. In other embodiments, other processes may be used to form the plastic layer 50.

In this embodiment, the gap between the rf chip and the circuit board is completely filled with the photo-lithographically bonding material layer, so that the plastic layer 50 does not need to be filled between the rf chip and the circuit board, thereby saving the time of the plastic packaging process. Of course, in the invention, if the gap exists between the radio frequency chip and the circuit board if the radio frequency chip and the circuit board are not completely occupied by the photoetching bonding material, the plastic layer can enter the gap, and better insulation, sealing and protection effects are carried out on the radio frequency chip.

Example two

Referring to fig. 6, a first difference from the embodiment is that: the back surface of the circuit board 10 is also formed with a first bonding pad 11, and the interconnection structure on the bottom plate is electrically connected with the corresponding interconnection structure, and when the electroplating process is performed, a second conductive bump 80 may be formed on the first bonding pad 11 on the back surface. The chip can be connected to the second conductive bump by soldering according to actual needs.

The exposed area of the first bonding pad 11 on the back surface is 5-200 square micrometers, and in this range, the first bonding pad 11 on the back surface can be in relatively full contact with the plating solution, so that the problem that the contact between the conductive bump and the bonding pad is affected due to insufficient contact between the bonding pad and the plating solution, such as poor contact resistance due to too small contact area, or poor electrical contact due to the fact that the contact cannot be performed is avoided.

When the second conductive bump 80 is formed on the bottom surface, i.e., the back surface, a solder mask layer is usually required to be formed on the back surface, and the solder mask layer covers the bottom surface, i.e., the back surface, of the circuit board and exposes the second conductive bump 80, so that no soldering phenomenon occurs in the solder mask layer region on the periphery of the second conductive bump during soldering.

In other embodiments, the second conductive bump 80 may be formed on the back surface of the circuit board 10 by electroplating or soldering after the molding layer 50 is formed.

The radio frequency chips are electrically connected through the circuit board 10 to form a signal receiving path and a signal transmitting path inside the radio frequency front end module. In one embodiment, the signal receiving path may include, connected in sequence: an antenna, a radio frequency switch, a filter, a low noise filter; the signal transmission path may include, connected in sequence: power amplifier, filter, radio frequency switch, antenna. The signal receiving path and the signal transmitting path may also share the antenna and/or the radio frequency switch.

In other embodiments, the signal receiving path may include, connected in sequence: an antenna, a radio frequency switch, a duplexer, and a low noise amplifier; the signal transmission path may include, connected in sequence: a power amplifier, a duplexer, a radio frequency switch; the signal receiving path and the signal transmitting path share the diplexer.

Example III

In a first embodiment, the lithographically bondable material does not form a cavity. Referring to fig. 7, in the third embodiment, a first cavity 21 may be formed in the lithographically bondable material, and then the filter chip 301a may be bonded on the first cavity 21, so that the first cavity 21 is enclosed between the filter chip 301a, the circuit board 10 and the lithographically bondable material 20, and the first cavity 21 may be a closed cavity or a non-closed cavity.

In this embodiment, the first cavity 21 is disposed only below the filter chip 301, and the first cavity may be used as an upper cavity of the filter chip 301, so as to improve the filtering effect of the radio frequency chip 301. In this embodiment, the filter chip 301a is a bulk acoustic wave filter, and only the lower cavity 3011 needs to be formed inside the filter chip 301a, the resonant film 3013 is exposed toward one side surface of the circuit board, and the first cavity 21 is used as the upper cavity, so that the thickness of the filter chip 301 can be reduced.

In other embodiments, the first cavity may be formed under the radio frequency chip on the entire circuit board, where the first cavity is required to be formed for the corresponding portion of the lithographically-bondable material of each radio frequency chip.

The integration method of the board-level rf front-end module of the third embodiment is different from that of the first embodiment in that: after the lithographically bondable material is formed on the circuit board, when the lithographically bondable material is patterned, not only the first bonding pad 11 is exposed, but also the first cavity 21 is formed, and then the radio frequency chip is bonded on the first cavity 21. Other embodiments are the same as the embodiments and will not be described in detail herein.

When the lithographically bondable material is formed on the rf chip, the lithographically bondable material 20 on the rf chip may be patterned to form the first cavity 21, and then bonded.

In addition, in the third embodiment, the second conductive bump 80 is also formed on the back surface of the circuit board, and specific reference is made to the description of the second embodiment. Of course, in other embodiments, the back surface of the circuit board may be the same as the first embodiment, and the first pads and the second conductive bumps are not required to be formed.

In addition, if the back side of the circuit board 10 is also bonded with the chip, the second organic dielectric layer 17 may be a lithographically bondable material, in which case it is not necessary to separately re-form the lithographically bondable material between the adhered chip and the circuit board, to save the process.

Example IV

Referring to fig. 8, in a first difference from the embodiment,:

In the fourth embodiment, the circuit board 10 includes a groove 101, the radio frequency chip 301 is embedded in the groove 101, a third bonding pad 1011 is formed at the bottom of the groove 101, and the second bonding pad 31 of the filter chip 301a and the third bonding pad 1011 are opposite to form the gap. The process of forming the conductive bump in the gap is the same as the process of forming the conductive bump between the first bonding pad and the second bonding pad, and the two are formed simultaneously, which is not described herein. And a first cavity 21 is provided in the lithographically bondable material under the filter chip 301a as an upper cavity of the filter chip 301 a.

In this embodiment, only a single recess 101 is formed in the front surface of the circuit board 10, and the radio frequency chip 301 is disposed in the recess 101 as an example. In other embodiments, the front and/or back side of the circuit board 10 may each form a single or multiple grooves, which may be formed by etching the circuit board 10. One or more radio frequency chips can be arranged in each groove, and the depth of each groove can be larger than, equal to or smaller than the thickness of each radio frequency chip. Preferably, the radio frequency chip with larger thickness is arranged in the groove, so that the thickness of the whole radio frequency front end module can be reduced. Since the thickness of the rf chip 301 as a filter chip is generally large, in this embodiment, the rf chip is disposed in the recess 101.

Example five

In the above embodiments of the present invention, the radio frequency chip is bonded only on one side, i.e., the front side, of the circuit board, and in other embodiments of the present invention, the first pads may be formed on both the front side and the back side of the circuit board, the radio frequency chips may be bonded on both the front side and the back side, and the chips of the radio frequency front end module are distributed on both the front side and the back side of the circuit board, so that the integration level of the radio frequency front end module may be improved, and the space area occupied by the module may be reduced.

Referring to fig. 9, in this embodiment, a radio frequency chip 302 and a filter chip 301 are bonded to the front surface of the circuit board 10, a radio frequency chip 303 and a radio frequency chip 304 are bonded to the back surface of the circuit board 10, a gap is formed between the second bonding pads of the radio frequency chip 302 and the filter chip 301 and the first bonding pad 11 on the front surface of the circuit board 10, a gap is formed between the second bonding pads 31 of the radio frequency chip 303 and the filter chip 304 and the first bonding pad 11 on the back surface of the circuit board, and during the electroplating process, a first conductive bump 40 is formed in the gaps on the front surface and the back surface of the circuit board 10.

After the bonding of the rf chips on both sides of the circuit board 10 is completed, electroplating is performed, and the first conductive bump 40 is formed in the gaps between the front and back sides of the circuit board 10.

In some embodiments, the radio frequency chip of the signal receiving channel and the radio frequency chip of the signal transmitting channel in the radio frequency front end module may be bonded to the front surface and the back surface of the circuit board respectively, so as to reduce interference between the received radio frequency signal and the transmitted radio frequency signal, and improve the isolation effect.

In the first embodiment, the relevant content may be cited herein, and will not be described herein.

In this embodiment, the bottom layer of the circuit board 10 may be the same as the prior art, and a solder mask layer and a solder resist layer are disposed on the bottom surface; in the invention, the electric connection between the radio frequency chip and the circuit board is not needed to be realized by welding, so that the bottom surface is not provided with a solder mask (green oil) or a soldering-assisting layer. The bottom layer may be an organic dielectric layer having a photolithographic bonding characteristic, and the first pad 11 on the back surface is buried in the organic dielectric layer and partially exposed. When the bottom layer is an organic medium layer with photoetching bonding characteristics, the organic medium layer with a certain thickness can be selected according to the requirement, so that the radio frequency chip can be conveniently bonded onto the back surface of the circuit board in the follow-up process, and the bonding layer is not required to be additionally formed, so that the process can be saved, and the forming efficiency of the circuit board is improved. When the bottom layer is an inorganic medium layer, compared with the organic medium layer, the surface tension of the electroplating solution on the inorganic medium layer is small, the electroplating solution is easier to enter the gaps, and the formation yield of the conductive bumps is improved; in addition, the formation of a soldering-assisting layer and a soldering-resisting layer is not needed, so that the process can be saved, and the formation efficiency of the circuit board is improved.

In other embodiments, the back surface of the circuit board 10 may also be formed with a groove, the radio frequency chip on the back surface of the circuit board 10 may be fully or partially disposed in the groove, the second bonding pad of the radio frequency chip and the third bonding pad on the bottom of the groove form a gap, and the first conductive bump is formed in the gap during electroplating. Please refer to the related content of the fourth embodiment.

The chips of the rf front-end modules may be bonded to the circuit board 10 at the same time, and fig. 9 shows a schematic diagram of two rf front-end modules after bonding, and each rf front-end module may be subsequently split by cutting the circuit board. In this way, packaging efficiency can be improved.

Example six

Referring to fig. 10, in this embodiment, compared with fig. 9 in the fifth embodiment, the lithographically-bondable material 20 under the filter chip 301a and the circuit board 10 have a cavity 103 therethrough. After patterning the photo-bondable material layer 20 to form the first cavity 21, the circuit board may be further etched along the patterned photo-bondable material layer 20, and a second cavity 103 may be formed in the circuit board 10, where the first cavity 21 and the second cavity 103 are integrally used as an upper cavity of the filter chip 301 a.

In other embodiments, after the second cavity 103 is formed in the circuit board 10 through patterning, after the photoetching bonding material is formed on the surface of the circuit board 10 or the filter chip 301a, the photoetching bonding material may be patterned to form the first cavity 21, where the positions of the first cavity 21 and the second cavity 103 are opposite, and the first cavity and the second cavity 103 are mutually communicated after bonding.

Example seven

Referring to fig. 11, in this implementation, the method further includes stacking and bonding a portion of the rf chips. In this embodiment, the filter chip 301a and the rf chip 302 are directly bonded to the front surface of the circuit board 10, while the rf chip 303 is stacked and bonded to the other side surface of the rf chip 302, and the rf chip 304 is stacked and bonded to the other side surface of the filter chip 301 a.

The two opposite side surfaces of the filter chip 301a and the rf chip 302 at the lower layer are respectively formed with a second bonding pad, the first surface is disposed towards the circuit board 10, and is bonded to the surface of the circuit board 10 (for a specific process, please refer to the foregoing embodiment), and the rf chip 303 and the rf chip 304 are bonded to the second surfaces of the filter chip 301a and the rf chip 302. A second bonding pad is also formed on the second surfaces of the filter chip 301a and the rf chip 302, and the rf chip 303 and the rf chip 304 are bonded on the second surfaces of the filter chip 301a and the rf chip 302, and bonding is achieved through a photo-lithographically bondable material, which is specifically referred to the bonding process between the rf chip and the circuit board in the foregoing embodiment, and is not described herein in detail.

The second bonding pads on the two side surfaces of the lower layer radio frequency chip can be electrically connected through the through holes penetrating through the chip, or the second bonding pads on the two side surfaces are respectively connected with devices inside the chip through interconnection structures inside the chip.

In other embodiments, only a portion of the radio frequency chip stack is provided; or the front and the back of the circuit board are provided with the radio frequency chips which are stacked.

In some embodiments, the rf chips may be stacked on each other, then bonded to the surface of the circuit board 10, and finally plated to form the first conductive bumps 40 between the chips and the circuit board and between the chips. In other embodiments, after the lower rf chip is bonded to the circuit board 10, the upper rf chip is bonded to the top of the lower rf chip, and finally the first conductive bump 40 is formed by electroplating. In other embodiments, the conductive bumps may also be formed multiple times, for example, by forming the first conductive bumps between the chips and the circuit board in two times.

Fig. 11 is a schematic diagram showing two rf front-end module chips after bonding, and each rf front-end module may be subsequently singulated by cutting the circuit board. In this way, packaging efficiency can be improved.

All the technical features in the above embodiments can be replaced or combined with each other, and a person skilled in the art can perform reasonable scheme combination according to the description in the above embodiments to form the radio frequency front end module with other structures, which are all within the protection scope of the present invention.

Example eight

Referring to fig. 12, this embodiment is different from fig. 10 in the sixth embodiment in that the filter chip 301b is a Surface Acoustic Wave (SAW) filter, the surface of the filter chip 301b is exposed to the resonance film 3013, the filter chip 301b is bonded above the first cavity 21 and the second cavity 103, and the first cavity 21 and the second cavity 103 which are in communication are used as the upper cavities of the filter. In this embodiment, no cavity is required to be formed in the filter chip 301b, so that the thickness of the filter can be reduced, the process steps can be saved, and the module volume can be reduced.

Example nine

Referring to fig. 13, this embodiment is different from fig. 10 in the sixth embodiment in that the filter chip 301c is a bulk acoustic wave (BAW-SMR) filter having a resonator mounted therein, and a resonant film 3013 of the filter chip 301c has one side surface exposed and the other side surface provided with a bragg reflection layer 3014. In this embodiment, the first cavity 21 and the second cavity 103 which are in communication are taken as the upper cavity of the filter chip 301 c.

Examples ten

Referring to fig. 5 to 13, a tenth embodiment provides a board-level system package structure of a radio frequency front end module, including:

a circuit board 10, the circuit board 10 having a front surface and a back surface, the front surface being formed with a plurality of first pads 11, the first pads 11 being recessed in the front surface; a plurality of radio frequency chips, such as radio frequency chips 301 to 304, wherein a second bonding pad 31 is formed on one surface of the radio frequency chips, and the second bonding pad 31 is recessed on the surface; the filter chips 301/301a, 302, 303, 304 are bonded to the circuit board 10, the first bonding pad 11 and the second bonding pad 31 are opposite to each other to form a gap, and the first conductive bump 40 is formed in the gap to electrically connect the first bonding pad 11 and the second bonding pad 31.

The radio frequency chip and the circuit board 10 are bonded together by a photo-bondable material 20, and the photo-bondable material 20 is disposed away from the bonding pads (the first bonding pad and the second bonding pad) and covers the peripheral area of the first conductive bump 40. The first welding pad and the second welding pad comprise opposite parts and staggered parts, the area of the opposite parts is at least one half of the area of the first welding pad or the second welding pad, and the height of the gap is 5-200 microns.

The circuit board 10 includes: and each layer of plate at least comprises a substrate and an interconnection structure positioned on the surface of the substrate, and the first welding pad is positioned on the interconnection structure of the top layer and is electrically connected with the interconnection structure. In this embodiment, the circuit board 10 is a three-layer board.

The circuit board 10 may also have a plastic layer 50 formed thereon that covers the rf chips.

Referring to fig. 6, the back surface of the circuit board 10 may also be formed with a first bonding pad 11, the first bonding pad 11 on the back surface is located on the interconnection structure on the bottom layer and is electrically connected with the corresponding interconnection structure, and the first bonding pad 11 on the back surface may also be formed with a second conductive bump 80 formed by electroplating.

Referring to fig. 7, the photolithographic bonding material layer 20 may also be formed with a first cavity 21, and at least a portion of a radio frequency chip, such as a filter chip 301a, is bonded to the first cavity 21. In other embodiments, the first cavity may be formed under the rf chip on the entire circuit board 10, where the first cavity is required to be formed in the lithographically-bondable material corresponding to the rf chip.

Referring to fig. 8, the circuit board 10 may further be formed with a groove 101, the groove 101 is embedded with a filter chip 301a, a third bonding pad 1011 is formed on the surface of the groove 101, and an electroplated conductive bump is formed between the third bonding pad 1011 and the second bonding pad 31 of the corresponding filter chip 301 a. In other embodiments, the circuit board 10 may be formed with a plurality of grooves, and all or part of the rf chips located on the same back surface of the circuit board 10 are disposed in the grooves.

Referring to fig. 9, a radio frequency chip is bonded to both the front and back surfaces of the circuit board 10. In this embodiment, the rf chip 302 and the filter chip 301a are bonded to the front surface of the circuit board 10, the rf chip 303 and the rf chip 304 are bonded to the back surface of the circuit board 10, a gap is formed between the second bonding pad of the rf chip 302 and the filter chip 301a and the first bonding pad 11 on the front surface of the circuit board 10, a gap is formed between the second bonding pad 31 of the rf chip 303 and the rf chip 304 and the first bonding pad 11 on the back surface of the circuit board, and electroplated first conductive bumps 40 are formed in the gaps.

A first organic dielectric layer 13 (please refer to fig. 1) with photolithographic bonding characteristics is formed on the front surface of the circuit board 10, and the first bonding pad 11 is embedded in the first organic dielectric layer 13; and/or, the back surface is formed with a second organic medium layer with photoetching bonding characteristics, and the first four bonding pads 11 on the back surface of the circuit board are buried in the second organic medium layer instead of the solder resist. In other embodiments, the first organic dielectric layer 13 may be replaced with a first inorganic dielectric layer; the second organic dielectric layer may be replaced with a second inorganic dielectric layer.

Referring to fig. 10, the lithographically-bondable material 20 under the filter chip 301a has a first cavity 102 and a second cavity 103 in the circuit board 10. The first cavity 102 and the second cavity 103 extend through the lithographically bondable material 20 and into the circuit board 10.

Referring to fig. 11, in this embodiment, the rf front-end module may be stacked. In this embodiment, the filter chip 301a and the rf chip 302 are directly bonded to the front surface of the circuit board 10, while the rf chip 303 is stacked and bonded to the other side surface of the rf chip 302, and the rf chip 304 is stacked and bonded to the other side surface of the filter chip 301 a. The two opposite side surfaces of the filter chip 301a and the rf chip 302 at the lower layer are respectively formed with a second bonding pad, the first surface is disposed towards the circuit board 10, and is bonded to the surface of the circuit board 10 (for a specific process, please refer to the foregoing embodiment), and the rf chip 303 and the rf chip 304 are bonded to the second surfaces of the filter chip 301a and the rf chip 302. A second bonding pad is also formed on the second surfaces of the filter chip 301a and the radio frequency chip 302, and the radio frequency chip 303 and the radio frequency chip 304 are bonded on the second surfaces of the filter chip 301a and the radio frequency chip 302, and the bonding is achieved through a photoetching bonding material.

Referring to fig. 12, in this embodiment, the filter chip 301b is a Surface Acoustic Wave (SAW) filter chip, where the surface of the filter chip 301b exposes the resonant film 3013, and the filter chip 301b is bonded above the first cavity 21 and the second cavity 103, and the first cavity 21 and the second cavity 103 which are connected are used as the upper cavities of the filter, so that no cavity needs to be formed inside the chip.

Referring to fig. 13, in this embodiment, the filter chip 301c is an SMR filter chip, and a bragg reflection layer 3014 is disposed at the bottom of the resonant film 3013, and the first cavity 21 and the second cavity 103 that are in communication are used as an upper cavity of the filter chip 301 c.

The relevant structures, materials, effects and the like in the first to ninth embodiments of the present invention may be cited herein, and are not described herein.

Example eleven

Referring to fig. 17, embodiment ten provides a circuit board 10 including: at least one layer 12, each layer 12 at least comprises a substrate and an interconnection structure positioned on the surface of the substrate, and the first bonding pad is positioned on the interconnection structure of the top layer and is electrically connected with the interconnection structure; the front surface of the circuit board is formed with a first organic dielectric layer with photoetching bonding characteristics, and the first welding pad 11 is embedded in the first organic dielectric layer 13. The first organic dielectric layer may be a first inorganic dielectric layer, and specific advantages may be described with reference to the first embodiment.

The circuit board 10 is a printed circuit board, namely a PCB board, and the circuit board 10 can be a single-layer board, a double-layer board, a three-layer board, a four-layer board, etc., and specifically, the number of layers of the circuit board 10 can be determined according to actual requirements. In this embodiment, the circuit board 10 is a three-layer board, each layer board includes: an interconnect structure located on the surface of the substrate, an interconnect plug electrically connected to the interconnect structure; the interconnection plug comprises a through hole and a conductive layer plated on the surface of the through hole, and is filled with insulating resin; the interconnect structure may include interconnect lines and interconnect pads. Or the interconnection plugs can be filled with conductive resin, so that the process of forming the conductive layer is saved. In the invention, whether each layer board contains the interconnection plug and the interconnection structure or not can be determined according to actual requirements, and only the interconnection structure can be provided, and no interconnection plug is provided.

If the second bonding pad 11 is also formed on the back surface of the PCB (refer to fig. 6, 7 and 9), the second bonding pad on the back surface is located on the interconnection structure of the bottom layer of the circuit board and is electrically connected with the corresponding interconnection structure, the second organic dielectric layer 17 with the photolithographic bonding characteristic is formed on the back surface, and the fourth bonding pad is buried in the second organic dielectric layer. The second organic dielectric layer 17 may be replaced with a second inorganic dielectric layer. The advantages may be referred to the description related to embodiment five (fig. 9).

Referring to fig. 14 to 17, the present embodiment also provides a method for forming a circuit board.

Referring to fig. 14, at least one layer 12 is formed, each layer 12 includes at least a substrate, an interconnection structure 14 on the surface of the substrate; in this embodiment, three layers are formed, each layer being formed by a method including providing a substrate, forming interconnect plugs 15 in the substrate, forming interconnect structures 14 on both the upper and lower sides of the substrate, which may include interconnect lines, and interconnect pads on the interconnect plugs. The interconnection plug comprises a through hole and a conductive structure positioned in the through hole, wherein the conductive structure can be a conductive layer positioned on the surface of the through hole, and the through hole can be filled with resin materials; in other embodiments, the interconnect plugs may include vias and conductive resin within the vias that simultaneously conduct and fill the vias, saving processing.

Referring to fig. 15, after the top board is formed, the first pads 11 are formed on the top board 12 and electrically connected to the interconnection structure on the top board; after the bottom plate is formed, forming a first pad 11 on the bottom plate; if the back surface of the circuit board is not required to be electrically connected, the first bonding pad 11 is not required to be formed on the back surface.

Referring to fig. 16, a first organic dielectric layer 13 having a photolithography bonding property is formed on a top plate, and a second organic dielectric layer 17 having a photolithography bonding property is formed on a bottom plate. The organic dielectric layer may be selected from a dry film, and the forming method thereof may be described with reference to the related description in the first embodiment. The advantages of forming the first organic dielectric layer and the second organic dielectric layer may be referred to the relevant description in the above embodiments. The first organic dielectric layer can be replaced by a first inorganic dielectric layer, the second organic dielectric layer needs to be replaced by a second inorganic dielectric layer, and the materials of the first inorganic dielectric layer and the second inorganic dielectric layer can be inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride and the like. The inorganic dielectric layer is formed by deposition.

Referring to fig. 17, openings are formed in the first and second organic dielectric layers 13 and 17 to expose the first pads 11.

It should be noted that, in the present specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. In particular, for structural embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and reference is made to the description of method embodiments for relevant points.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. The method for packaging the radio frequency front end module board level system is characterized by comprising the following steps of:

Providing a circuit board, wherein a plurality of first welding pads are formed on the surface of the circuit board, and the first welding pads are recessed on the surface;

Providing a radio frequency chip, wherein the radio frequency chip comprises at least one filter chip, other radio frequency chips comprise at least one function of signal amplification, signal reception and signal tuning, a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip;

bonding at least one radio frequency chip on the circuit board through a photoetching bonding material, wherein a second welding pad of the at least one radio frequency chip is opposite to a corresponding first welding pad on the circuit board to form a gap;

First conductive bumps defining forming positions by the photoetching bonding material are formed in the gaps through an electroplating process so as to electrically connect the first bonding pads and the second bonding pads.

2. The method of claim 1, wherein the lithographically bondable material is disposed away from the bonding pads.

3. The method of claim 2, wherein the lithographically bondable material covers an area of the periphery of the first conductive bump.

4. The method of claim 2, wherein the thickness of the lithographically bondable material is 5-200 μm, and the lithographically bondable material covers at least 10% of the rf chip area.

5. The method of claim 2, wherein the lithographically bondable material is formed on the rf chip or the circuit board, and then the rf chip is bonded to the circuit board.

6. The method of claim 2, wherein a lithographically bondable material is formed on the region of the circuit board to be bonded; patterning the lithographically bondable material to form openings to expose the bond pads; and bonding the radio frequency chip and the circuit board together through the photoetching bonding material.

7. The method of claim 1, wherein the opposing pads comprise facing portions and staggered portions, the facing portions having an area that is greater than one half the area of the pads.

8. The method of claim 1, wherein the height of the void is 5um-200um.

9. The method of claim 1, wherein the exposed pads have an area of 5-200 square microns; and/or the cross-sectional area of the first conductive bump is greater than 10 square microns.

10. The method of claim 1, wherein the electroplating process comprises electroless plating.

11. The method of claim 10, wherein the electroless plating comprises: electroless palladium plating and gold leaching, wherein the time of electroless nickel is 30-50 minutes, the time of electroless gold is 4-40 minutes, and the time of electroless palladium is 7-32 minutes;

or, electroless nickel gold, wherein the electroless nickel time is 30-50 minutes, and the electroless gold time is 4-40 minutes;

or, electroless nickel, wherein the electroless nickel is for 30-50 minutes.

12. The method of packaging a radio frequency front end module board level system of claim 1, further comprising: patterning the circuit board before bonding the radio frequency chip, and forming a cavity in the circuit board; at least the filter chip is bonded to the cavity, the cavity acting as an upper cavity for the filter chip.

13. The method of claim 1, wherein the rf chip is bonded to the circuit board by a lithographically bondable material; further comprises: patterning the photoetching bonding material to form a cavity; after the filter chip is bonded to the circuit board, the cavity serves as an upper cavity of the filter chip.

14. The method of packaging a radio frequency front end module board level system of claim 13, comprising: after the photoetching bonding material is formed on the bonding surface of the filter chip, patterning the photoetching bonding material to form the cavity, bonding the filter chip on the circuit board through the patterned photoetching bonding material, wherein the cavity is used as an upper cavity of the filter chip.

15. The method of packaging a radio frequency front end module board level system of claim 13, comprising: patterning the lithographically bondable material to form the cavity after the lithographically bondable material is formed on the circuit board; and bonding the filter chip above the cavity through photoetching bonding materials at the edge of the cavity, wherein the cavity is used as an upper cavity of the filter chip.

16. The method of packaging a radio frequency front end module board level system of claim 15, further comprising: and before bonding the radio frequency chip, further patterning the circuit board along the patterned photoetching bonding material to form a cavity communicated with the photoetching bonding material and the circuit board.

17. The method of packaging a radio frequency front end module board level system of claim 1, further comprising: before bonding the radio frequency chip, forming a groove in the circuit board, wherein a third welding pad is formed at the bottom of the groove and is recessed in the bottom surface of the groove; bonding at least part of the radio frequency chip on the bottom surface of the groove, and forming a gap between a second welding pad of the radio frequency chip positioned in the groove and a third welding pad at the bottom of the groove; and forming a first conductive bump in the gap through an electroplating process to electrically connect the second bonding pad and the third bonding pad.

18. The method of packaging a radio frequency front end module board level system of claim 1, comprising: and stacking and bonding at least two radio frequency chips, wherein second welding pads are formed on two opposite side surfaces of the lower radio frequency chip, and a gap is formed between the second welding pads of the upper radio frequency chip and the second welding pads of the lower radio frequency chip.

19. The method of claim 1, wherein the circuit board has opposite front and back sides, and the rf chip is bonded to the front and/or back sides of the circuit board.

20. The method of packaging a radio frequency front end module board level system of claim 1, wherein the radio frequency chip comprises: at least one of a bare chip, a plastic sealing layer, a shielding layer on the top surface, and an interconnection through hole structure penetrating through the chip.

21. The method of claim 1, wherein the circuit board includes opposite front and back sides, each of the front and back sides having the first bond pad formed thereon; forming a second conductive bump on the first bonding pad on the back of the circuit board through an electroplating process; and/or bonding at least one radio frequency chip to the back surface of the circuit board.

22. The utility model provides a radio frequency front end module board level system packaging structure which characterized in that includes:

The circuit board is provided with a plurality of first welding pads on the surface, and the first welding pads are recessed on the surface of the circuit board;

the radio frequency chip comprises at least one filter chip, other radio frequency chips comprise at least one function of signal amplification, signal reception and signal tuning, a second welding pad is formed on the surface of the radio frequency chip, and the second welding pad is recessed on the surface of the radio frequency chip;

At least one radio frequency chip is bonded on the circuit board through a photoetching bonding material, a first electroplated conductive bump is formed between a second bonding pad of the radio frequency chip and a corresponding first bonding pad on the circuit board, and the first conductive bump is defined to form a position by the photoetching bonding material so as to electrically connect the first bonding pad and the second bonding pad.

23. The rf front-end module board-level system package of claim 22, wherein the rf chip is bonded between the circuit boards by a lithographically-bondable material disposed around the bonding pads, the first bonding pads, the second bonding pads, and the lithographically-bondable material define voids, the first conductive bumps are located in the voids, and the morphology is limited by the voids.

24. The system-in-package structure of claim 22, wherein the circuit board has opposite front and back sides, and the rf chips are located on the front side or on the back side, or are bonded on both the front and back sides.

25. The system-in-package structure of claim 22, wherein the circuit board comprises a recess, a third pad is formed at the bottom of the recess, and the third pad is recessed in the bottom of the recess; at least part of the radio frequency chip is bonded on the bottom surface of the groove, a gap is formed between a second welding pad of the radio frequency chip positioned in the groove and a third welding pad at the bottom of the groove, and a first electroplated conductive bump is formed in the gap.

26. The rf front-end module board-level system package of claim 22, wherein the circuit board further has a cavity, at least the filter chip being bonded to the cavity, the cavity being an upper cavity of the filter chip.

27. The rf front-end module board-level system package of claim 22, wherein the rf chip is bonded to the circuit board by a lithographically bondable material; a cavity is formed in the photoetching bonding material; at least the filter chip is bonded over the cavity, the cavity acting as an upper cavity for the filter chip.

28. The rf front end module board level system package of claim 27, wherein the cavity in the lithographically bondable material extends into the circuit board.

29. The package structure of claim 22, wherein at least two rf chips are stacked and bonded, second bonding pads are formed on opposite side surfaces of the lower rf chip, and a gap is formed between the second bonding pad of the upper rf chip and the second bonding pad of the lower rf chip, and a first conductive bump is formed in the gap.

30. The radio frequency front end module board level system package structure of claim 22, wherein the circuit board comprises opposing front and back sides, each of the front and back sides being formed with the first bond pad; forming a second conductive bump on the first bonding pad on the back of the circuit board through an electroplating process; and/or bonding at least one radio frequency chip to the back surface of the circuit board.

31. The radio frequency front end module board level system package structure of any of claims 22 to 30, wherein the bonding is achieved by a lithographically bondable material that is disposed away from the bond pad and covers an area of the periphery of the first conductive bump.

32. The radio frequency front end module board level system package structure of claim 22, wherein the opposing pads comprise facing portions and staggered portions, the facing portions having an area greater than one half the area of the first or second pads.