CN114695576A - Multi-intrinsic-layer amorphous silicon passivation layer structure for HJT battery and preparation method thereof - Google Patents

Abstract

The invention discloses a multi-intrinsic-layer amorphous silicon passivation layer structure for an HJT battery, and belongs to the technical field of photovoltaic batteries. The invention optimizes the structure of the amorphous silicon intrinsic layer for the HJT battery, adopts a multi-layer intrinsic layer structure, strengthens the passivation effect of the intrinsic layer, and can effectively prevent epitaxial silicon from being formed in the process of depositing the hydrogenated amorphous silicon intrinsic layer. Each intrinsic layer serves to improve different electrical performance parameters, which can further optimize the electrical performance of the HJT cell. Meanwhile, the hydrogen treatment is placed at the end of the intrinsic layer, so that the ion bombardment on the surface of the silicon wafer can be effectively reduced, the effect of passivating the intrinsic layer and the silicon wafer can be enhanced, and a solid foundation is provided for realizing a high-efficiency battery.

Description

Multi-intrinsic layer amorphous silicon passivation layer structure for HJT cell and preparation method thereof

technical field

The invention belongs to the technical field of photovoltaic cells, and in particular, relates to a multi-intrinsic layer amorphous silicon passivation layer structure for HJT cells and a preparation method thereof.

Background technique

Photovoltaic cells are an important means of effectively utilizing solar energy. Among many types of photovoltaic cells, monocrystalline silicon solar cell technology has established a significant dominant position in the photovoltaic industry. P-type monocrystalline silicon developed earlier, and mainstream products have experienced the continuous development of BSF cells, PERC cells and double-sided PERC+ cells, and the cell efficiency has gradually approached the bottleneck. In contrast, N-type silicon wafers have a longer minority carrier lifetime and less light-induced attenuation. It is recognized that the development of high-efficiency photovoltaic cells in the future will switch to the direction of N-type cells.

HJT batteries are also called heterojunction (Heterojunction with Intrinsic Thinfilm, HIT) batteries. HIT is a special PN junction, which is formed by amorphous silicon and crystalline silicon materials. It is a kind of N-type battery by depositing an amorphous silicon film on crystalline silicon.

The HJT amorphous silicon passivation layer is a hydrogenated amorphous silicon intrinsic layer, which can reduce a-Si/c-Si dangling bonds and passivate the heterojunction interface. Usually, a chemical vapor deposition (Chemical Vapor Deposition, CVD) method is used to perform hydrogen ion treatment on the front surface of the silicon wafer after texturing and cleaning, and then a hydrogenated amorphous silicon intrinsic layer is deposited. Under the silicon wafer, hydrogen ion treatment is performed first, and then a hydrogenated amorphous silicon intrinsic layer is deposited. The feeding gases are SiH ₄ and H ₂ , H ₂ : SiH ₄ =1～20, the cavity process temperature is generally controlled at about 200°C, and the thickness of the hydrogenated amorphous silicon intrinsic layer on the front and back of the silicon wafer is generally controlled at 5～10nm.

The existing HJT technology, on the one hand, directly performs hydrogen ion treatment on the silicon wafer after texturing and cleaning, although the surface cleanliness of the silicon wafer can be improved, the residual oxide and fluoride can be removed, and the surface defects can be passivated, which can improve the Isc and Voc, However, the surface of the silicon wafer will be selectively etched, which will change the surface roughness of the silicon wafer and cause additional strain and defects in the crystalline silicon, which is not conducive to passivation. On the other hand, for the hydrogenated amorphous silicon intrinsic layer of the single-layer structure, a large amount of H ₂ is introduced into the deposition process to dilute SiH ₄ , and the hydrogen ions will bombard the surface of the silicon wafer to form additional defects, and at the same time, epitaxial silicon may also be formed, among which Epitaxial silicon is composed of columnar agglomerates, cracks and micro-voids, increasing the density of defect states in the film, which will affect the electrical performance of the battery.

SUMMARY OF THE INVENTION

In order to solve at least one of the above-mentioned technical problems, the present invention adopts the following technical solutions:

A first aspect of the present invention provides a multi-intrinsic layer amorphous silicon passivation layer structure for HJT cells, which is characterized by comprising a silicon wafer, a first multi-intrinsic layer group is deposited on the front side of the silicon wafer, and a backside of the silicon wafer is deposited There is a second multi-intrinsic layer group, the first multi-intrinsic layer group includes a first intrinsic layer, a second intrinsic layer, a third intrinsic layer and a fourth intrinsic layer in sequence from the front side of the silicon wafer, and the second multi-intrinsic layer The intrinsic layer group includes five intrinsic layers, a sixth intrinsic layer and a seventh intrinsic layer in sequence from the back of the silicon wafer, wherein:

The first intrinsic layer and the fifth intrinsic layer are obtained by depositing CO ₂ and SiH ₄ ;

The second intrinsic layer and the sixth intrinsic layer are obtained by depositing SiH ₄ ;

The third intrinsic layer is obtained by depositing H ₂ , CH ₄ and SiH ₄ ;

The fourth intrinsic layer is obtained by depositing H ₂ , CO ₂ and SiH ₄ ;

The seventh intrinsic layer is obtained by depositing H ₂ and SiH ₄ .

Further, the silicon wafer is an N-type phosphorus-doped single crystal silicon wafer.

In the present invention, the front surface of the silicon wafer refers to the light incident surface of the silicon wafer, and correspondingly, the back surface of the silicon wafer refers to the other surface opposite to the light incident surface, that is, the backlight surface.

In some embodiments of the present invention, the thickness of the silicon wafer is 50-300 μm, preferably, the thickness of the silicon wafer is 100-2000 μm, more preferably, the thickness of the silicon wafer is 120-180 μm. In a specific embodiment of the present invention, the thickness of the silicon wafer is 150 μm.

In the present invention, the function of the first intrinsic layer is to prevent the epitaxial growth of each intrinsic layer. In some embodiments of the present invention, the thickness of the first intrinsic layer is 0.2-2 nm, preferably, the thickness of the first intrinsic layer is 0.5-1.5 nm, more preferably, the first intrinsic layer has a thickness of 0.5-1.5 nm. The thickness of the sign layer is 0.8-1.2 nm. In a specific embodiment of the present invention, the thickness of the first intrinsic layer is 1 nm.

In the present invention, the function of the second intrinsic layer is to passivate the silicon wafer and the first intrinsic layer. In some embodiments of the present invention, the thickness of the second intrinsic layer is 1-10 nm, preferably, the thickness of the second intrinsic layer is 2-8 nm, more preferably, the thickness of the second intrinsic layer is 2-8 nm The thickness of the layers is 3-5 nm. In a specific embodiment of the present invention, the thickness of the second intrinsic layer is 4 nm.

In the present invention, when the third intrinsic layer is obtained by depositing H ₂ , CH ₄ and SiH ₄ , a-SiC:H can be formed, and a-SiC:H has a negative impact on the silicon wafer and the first intrinsic layer. The layer and the second intrinsic layer have a good passivation effect, and at the same time a-SiC:H has a large optical band gap, which can reduce light absorption and improve the short-circuit current Isc and the open-circuit voltage Voc. In some embodiments of the present invention, the thickness of the third intrinsic layer is 0.2-2 nm, preferably, the thickness of the third intrinsic layer is 0.5-1.5 nm, more preferably, the third intrinsic layer has a thickness of 0.5-1.5 nm. The thickness of the sign layer is 0.8-1.2 nm. In a specific embodiment of the present invention, the thickness of the third intrinsic layer is 1 nm.

In the present invention, when the fourth intrinsic layer is obtained by depositing H ₂ , CO ₂ and SiH ₄ , a-SiOX:H can be formed. layer, the second intrinsic layer and the third intrinsic layer have good passivation, and at the same time a-SiOx:H has a larger forbidden band width, which can reduce light absorption and further improve Isc and Voc. In some embodiments of the present invention, the thickness of the fourth intrinsic layer is 5-20 nm, preferably, the thickness of the fourth intrinsic layer is 7-15 nm, more preferably, the fourth intrinsic layer has a thickness of 7-15 nm The thickness of the layers is 8-12 nm. In a specific embodiment of the present invention, the thickness of the fourth intrinsic layer is 10 nm.

In the present invention, the function of the fifth intrinsic layer is to prevent epitaxial growth of each intrinsic layer. In some embodiments of the present invention, the fifth intrinsic layer has a thickness of 0.2-2 nm, preferably, the fifth intrinsic layer has a thickness of 0.5-1.5 nm, more preferably, the fifth intrinsic layer has a thickness of 0.5-1.5 nm. The thickness of the sign layer is 0.8-1.2 nm. In a specific embodiment of the present invention, the thickness of the fifth intrinsic layer is 1 nm.

In the present invention, the function of the sixth intrinsic layer is to passivate the silicon wafer and the fifth intrinsic layer. In some embodiments of the present invention, the thickness of the sixth intrinsic layer is 1-10 nm, preferably, the thickness of the sixth intrinsic layer is 2-8 nm, more preferably, the sixth intrinsic layer has a thickness of 2-8 nm. The thickness of the sign layer is 3-5 nm. In a specific embodiment of the present invention, the thickness of the sixth intrinsic layer is 4 nm.

In some embodiments of the present invention, the thickness of the seventh intrinsic layer is 1-15 nm, preferably, the thickness of the seventh intrinsic layer is 2-10 nm, more preferably, the seventh intrinsic layer has a thickness of 2-10 nm The thickness of the layers is 3-8 nm. In a specific embodiment of the present invention, the thickness of the seventh intrinsic layer is 5 nm.

A second aspect of the present invention provides a method for preparing the multi-intrinsic layer amorphous silicon passivation layer structure described in the first aspect of the present invention, comprising the following steps:

S1, prepare a first multi-intrinsic layer group on the front side of the silicon wafer, specifically, first deposit four intrinsic layers on the surface of the silicon wafer in sequence, and finally perform hydrogen ion treatment after the fourth intrinsic layer:

S11, prepare the first intrinsic layer: pass in CO ₂ and SiH ₄ for deposition;

S12, prepare the second intrinsic layer: only pass through SiH ₄ for deposition;

S13, prepare the third intrinsic layer: pass in H ₂ , CH ₄ and SiH ₄ for deposition;

S14, prepare the fourth intrinsic layer: pass H ₂ , CO ₂ and SiH ₄ for deposition,

S2, preparing a second multi-intrinsic layer group on the back of the silicon wafer, first depositing three intrinsic layers on the surface of the silicon wafer in sequence, and finally performing hydrogen treatment after the third intrinsic layer:

S21, prepare the fifth intrinsic layer: pass in CO ₂ and SiH ₄ for deposition;

S22, prepare the sixth intrinsic layer: only pass through SiH ₄ for deposition;

S23, prepare the seventh intrinsic layer: pass H ₂ and SiH ₄ for deposition.

Further, in each step, deposition is performed using PECVD.

Hydrogen ion treatment is essential in the process of depositing the hydrogenated amorphous silicon intrinsic layer, but directly performing hydrogen pretreatment on the surface of the silicon wafer after texturing and cleaning will have adverse effects. The hydrogen ion treatment technology will not directly damage the surface of the silicon wafer.

In some embodiments of the present invention, in step S11, the volume ratio of passing CO ₂ and SiH ₄ is: CO ₂ :SiH ₄ =0.1-2:1, preferably, the volume ratio of passing CO ₂ and SiH ₄ It is: CO ₂ :SiH ₄ =0.2-1:1, more preferably, the volume ratio of CO ₂ and SiH ₄ introduced is: CO ₂ :SiH ₄ =0.3-0.7:1. In a specific embodiment of the present invention, the volume ratio of introducing CO ₂ and SiH ₄ is: CO ₂ :SiH ₄ =0.5:1.

In some embodiments of the present invention, in step S13, the volume ratio of passing H ₂ , CH ₄ and SiH ₄ is: H ₂ :CH ₄ :SiH ₄ =1～20:0.1～2:1, preferably, The volume ratio of passing H ₂ , CH ₄ and SiH ₄ is: H ₂ :CH ₄ :SiH ₄ =5～15:0.2～0.8:1, more preferably, the volume of passing H ₂ , CH ₄ and SiH ₄ The ratio is: H ₂ :CH ₄ :SiH ₄ =8 to 12:0.3 to 0.6:1. In a specific embodiment of the present invention, the volume ratio of H ₂ , CH ₄ and SiH ₄ introduced is: H ₂ :CH ₄ :SiH ₄ =10:0.5:1.

In some embodiments of the present invention, in step S14, the volume ratio of passing H ₂ , CO ₂ and SiH ₄ is: H ₂ :CO ₂ :SiH ₄ =1～20:0.1～2:1, preferably, The volume ratio of passing H ₂ , CO ₂ and SiH ₄ is: H ₂ :CO ₂ :SiH ₄ =5～15:0.2～0.8:1, more preferably, the volume of passing H ₂ , CO ₂ and SiH ₄ The ratio is: H ₂ :CO ₂ :SiH ₄ =8-12:0.3-0.6:1. In a specific embodiment of the present invention, the volume ratio of H ₂ , CO ₂ and SiH ₄ introduced is: H ₂ :CO ₂ :SiH ₄ =10:0.5:1.

In some embodiments of the present invention, in step S21, the volume ratio of passing CO ₂ and SiH ₄ is: CO ₂ :SiH ₄ =0.1-2:1, preferably, the volume ratio of passing CO ₂ and SiH ₄ It is: CO ₂ :SiH ₄ =0.2-1:1, more preferably, the volume ratio of CO ₂ and SiH ₄ introduced is: CO ₂ :SiH ₄ =0.3-0.7:1. In a specific embodiment of the present invention, the volume ratio of introducing CO ₂ and SiH ₄ is: CO ₂ :SiH ₄ =0.5:1.

In some embodiments of the present invention, in step S23, the volume ratio of passing H ₂ and SiH ₄ is: H ₂ :SiH ₄ =1～30:1, preferably, the volume ratio of passing H ₂ and SiH ₄ It is: H ₂ :SiH ₄ =5-25:1, more preferably, the volume ratio of H ₂ and SiH ₄ introduced is: H ₂ :SiH ₄ =15-22:1. In a specific embodiment of the present invention, the volume ratio of H ₂ and SiH ₄ introduced is: H ₂ :SiH ₄ =20:1.

A third aspect of the present invention provides an HJT cell having the multi-intrinsic layer amorphous silicon passivation layer structure described in the first aspect of the present invention.

Further, an N-doped layer is deposited on the first multi-intrinsic layer group.

Further, a P-type amorphous silicon layer is deposited on the second multi-intrinsic layer group. In the present invention, a-Si:H can be formed during deposition and preparation of the seventh intrinsic layer by feeding H ₂ and SiH ₄ , and a-Si:H can prevent the diffusion of B doping atoms in the P-type amorphous silicon layer Entering into the fifth intrinsic layer and the sixth intrinsic layer, it has a good passivation effect on the silicon wafer, the fifth intrinsic layer and the sixth intrinsic layer, and improves the Isc and Voc.

Further, a first TCO conductive film is deposited on the N-doped layer, and a second TCO conductive film is deposited on the P-type amorphous silicon layer.

Transparent Conductive Oxide (TCO) is a thin film material with high transmittance and low resistivity in the visible light spectral range (380nm<λ<780nm). In some embodiments of the present invention, the TCO material is selected from the group consisting of, but not limited to, indium tin oxide (ITO, In ₂ O ₃ : Sn), aluminum doped zinc oxide (AZO, ZnO: Al), fluorine doped group of tin oxide (FTO, SnO ₂ :F), antimony-doped tin oxide (ATO, Sn ₂ O:Sb).

Further, a first electrode is provided on the first TCO conductive film, and a second electrode is provided on the second TCO conductive film. Preferably, both the first electrode and the second electrode are Ag electrodes.

HJT cells have high conversion efficiency and do not require high temperature furnace tube preparation, which can reduce production energy consumption and shorten preparation time. It has the advantages of generating electricity after the front and back sides are illuminated, low temperature manufacturing process to protect the carrier life, high open circuit voltage, and good temperature characteristics.

In some embodiments of the present invention, the thickness of the N-doped layer is 5-20 nm, preferably, the thickness of the N-doped layer is 7-15 nm, more preferably, the thickness of the N-doped layer 8-12nm. In a specific embodiment of the present invention, the thickness of the N-doped layer is 10 nm.

In some embodiments of the present invention, the P-type amorphous silicon layer has a thickness of 5-20 nm, preferably, the P-type amorphous silicon layer has a thickness of 7-15 nm, more preferably, the P-type amorphous silicon layer has a thickness of 7-15 nm. The thickness of the amorphous silicon layer is 8-12 nm. In a specific embodiment of the present invention, the thickness of the P-type amorphous silicon layer is 10 nm.

In some embodiments of the present invention, the thickness of the first TCO conductive film and the second TCO conductive film is 50-200 nm, preferably, the thickness of the first TCO conductive film and the second TCO conductive film The thickness is 70-150 nm, and more preferably, the thickness of the first TCO conductive film and the second TCO conductive film is 80-120 nm. In a specific embodiment of the present invention, the thickness of the first TCO conductive film and the second TCO conductive film is 100 nm.

The fourth aspect of the present invention provides the preparation method of the HJT battery described in the third aspect of the present invention, comprising the following steps:

obtaining the multi-intrinsic layer amorphous silicon passivation layer structure described in the first aspect of the present invention, or preparing the multi-intrinsic layer amorphous silicon passivation layer structure by the method described in the second aspect of the present invention;

Further, depositing an N-doped layer on the fourth intrinsic layer, and depositing a P-type amorphous silicon layer on the seventh intrinsic layer, preferably by PECVD;

Further, depositing the first TCO conductive film on the N-doped layer, and depositing the second TCO conductive film on the P-type amorphous silicon layer, preferably, using RPD or PVD for deposition;

Further, the first electrode is provided on the first TCO conductive film, and the second electrode is provided on the second TCO conductive film.

Further, preferably, the above-mentioned method further includes the step of curing, so that the grid lines of the first electrode and the first TCO conductive film, as well as the grid lines of the second electrode and the second TCO are conductive A good ohmic contact is formed between the films.

The beneficial effects of the present invention

Compared with the prior art, the present invention has the following effective effects:

The invention optimizes the structure of the intrinsic layer of amorphous silicon used in HJT cells, adopts a multi-layer intrinsic layer structure, strengthens the passivation of the intrinsic layer, and can effectively prevent the process of depositing the intrinsic layer of hydrogenated amorphous silicon. Formed in epitaxial silicon. Each intrinsic layer plays the role of improving different electrical performance parameters, which can further optimize the electrical performance of HJT cells. Moreover, placing the hydrogen treatment at the end of the intrinsic layer can not only effectively reduce the ion bombardment on the surface of the silicon wafer, but also strengthen the passivation of the intrinsic layer and the silicon wafer, providing a solid foundation for the realization of high-efficiency cells.

Description of drawings

FIG. 1 shows a schematic diagram of the structure of a multi-intrinsic layer amorphous silicon passivation layer used in an HJT cell in Example 1 of the present invention.

FIG. 2 shows a schematic diagram of an HJT cell containing the multi-intrinsic layer amorphous silicon passivation layer structure in Example 1 of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer, the present invention will be further described in detail below with reference to the embodiments.

Example

The following examples are used herein to demonstrate preferred embodiments of the present invention. Those skilled in the art will appreciate that the techniques disclosed in the following examples represent techniques discovered by the inventors that can be used to implement the present invention, and thus can be regarded as preferred solutions for implementing the present invention. However, those skilled in the art should understand from this specification that many modifications can be made to the specific embodiments disclosed herein and still obtain the same or similar results, without departing from the spirit or scope of the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, the public references herein and the materials to which they refer are incorporated by reference .

Those skilled in the art will recognize, or be aware of through routine experimentation, many equivalents to the specific embodiments of the invention described herein. Such equivalents are to be included in the claims.

The experimental methods in the following examples are conventional methods unless otherwise specified. The instruments and equipment used in the following examples are conventional laboratory equipment unless otherwise specified; the test materials used in the following examples are purchased from conventional reagent stores unless otherwise specified.

Example 1 Structure of Intrinsic Amorphous Silicon Passivation Layer of HJT Cell

This embodiment provides an intrinsic amorphous silicon passivation layer structure of an HJT cell, as shown in FIG. 1 . The structure includes a silicon wafer 1 , a first multi-intrinsic layer group 21 is deposited on the front side of the silicon wafer 1 , a second multi-intrinsic layer group 22 is deposited on the backside of the silicon wafer 1 , and the first multi-intrinsic layer group 21 is deposited from the front side of the silicon wafer 1 . Starting from the first intrinsic layer 211, the second intrinsic layer 212, the third intrinsic layer 213 and the fourth intrinsic layer 214, the second multi-intrinsic layer group 22 sequentially includes five intrinsic layers from the back of the silicon wafer 1 221, the sixth intrinsic layer 222 and the seventh intrinsic layer 223, wherein:

The first intrinsic layer 211 and the fifth intrinsic layer 221 are obtained by depositing CO ₂ and SiH ₄ ;

The second intrinsic layer 212 and the sixth intrinsic layer 222 are obtained by depositing SiH ₄ ;

The third intrinsic layer 213 is obtained by depositing H ₂ , CH ₄ and SiH ₄ ;

The fourth intrinsic layer 214 is obtained by depositing H ₂ , CO ₂ and SiH ₄ ;

The seventh intrinsic layer 223 is obtained by depositing H ₂ and SiH ₄ .

Example 2 HJT cell with intrinsic amorphous silicon passivation layer structure in Example 1

This embodiment provides an HJT cell containing the intrinsic amorphous silicon passivation layer structure in Embodiment 1, as shown in FIG. 2 .

In this cell, an N-doped layer 3 is deposited on the first multi-intrinsic layer group 21 , and a P-type amorphous silicon layer 4 is deposited on the second multi-intrinsic layer group 22 .

Further, a first TCO conductive film 51 is deposited on the N-doped layer 3 , and a second TCO conductive film 52 is deposited on the P-type amorphous silicon layer 4 .

Furthermore, a first electrode 61 is provided on the first TCO conductive film 51 , and a second electrode 62 is provided on the second TCO conductive film 52 .

Example 3 Preparation method of HJT battery

This embodiment provides a specific preparation method of the HJT battery in Example 2, which includes the following steps:

(1) Texturing and cleaning the silicon wafer 1, wherein the silicon wafer 1 is an N-type phosphorus-doped single crystal silicon wafer with a size of 158.75mm×158.75mm and a thickness of 150μm;

(2) A first multi-intrinsic layer group 21 is prepared on the light incident surface (front side) of the silicon wafer by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), including 4 intrinsic layers:

The first intrinsic layer 211 is deposited with CO ₂ and SiH ₄ , wherein CO ₂ :SiH ₄ =0.5, and the thickness is about 1 nm;

The second intrinsic layer 212 is deposited only by passing through SiH ₄ , and the thickness is about 4 nm;

The third intrinsic layer 213 is deposited by feeding H ₂ , CH ₄ and SiH ₄ , wherein H ₂ :CH ₄ :SiH ₄ =10:0.5:1, and the thickness is about 1 nm;

The fourth intrinsic layer 214 is deposited by feeding H ₂ , CO ₂ and SiH ₄ , wherein H ₂ :CO ₂ :SiH ₄ =10:0.5:1, and the thickness is about 1 nm;

(3) Prepare the front N-doped layer 3 on the first multi-intrinsic layer 21, that is, the fourth intrinsic layer 214 by PECVD, with a thickness of about 10 nm;

(4) The silicon wafer is turned over, and a second multi-intrinsic layer group 22 is prepared on the backside of the silicon wafer by PECVD, including 3 intrinsic layers:

The fifth intrinsic layer 221 is deposited with CO ₂ and SiH ₄ , wherein CO ₂ :SiH ₄ =0.5, and the thickness is about 1 nm;

The sixth intrinsic layer 222 is deposited only by passing through SiH ₄ , and the thickness is about 4 nm;

The seventh intrinsic layer 223 is deposited by feeding H ₂ and SiH ₄ , wherein H ₂ :SiH ₄ =20:1, and the thickness is about 5nm;

(5) using PECVD to prepare the P-type amorphous silicon layer 4 with a thickness of about 10 nm;

(6) using plasma deposition (Rcactivc Plasma Deposition, RPD) or physical vapor deposition (Physical Vapour Deposition, PVD) to deposit the first TCO conductive film 51 and the second TCO conductive film 52, with a thickness of about 100 nm;

(7) By screen printing, the first electrode 61 is formed on the first TCO conductive film 51, and the second electrode 62 is formed on the second TCO conductive film 52, wherein the first electrode 61 and the second electrode 62 are both Ag electrode;

(8) curing, so that a good ohmic contact is formed between the gate line of the Ag electrode and the first TCO conductive film and the second TCO conductive film.

Example 4 Preparation method and electrical performance test of other HJT batteries

Other specific HJT cells described in Example 2 were prepared by the method of Reference Example 3. The overall steps are the same, the difference is the parameters of the silicon wafer and each intrinsic layer. Further conduct electrical performance tests on each HJT battery.

The parameters and electrical performance data of each HJT battery are as follows:

The list of the electrical properties of the cell set according to each condition in Example 4 is as follows:

The above results show that the HJT batteries prepared by the invention all have good electrical properties and can be popularized and applied on a large scale.

All documents mentioned herein are incorporated by reference in this application as if each document were individually incorporated by reference. In addition, it should be understood that after reading the above teaching content of the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

Claims (10)

1. The utility model provides a many intrinsic layers amorphous silicon passivation layer structure for HJT battery, its characterized in that includes the silicon chip, and the silicon chip openly deposits there is first many intrinsic layers group, and the silicon chip back deposits there is the many intrinsic layers group of second, and first many intrinsic layers group includes first intrinsic layer, second intrinsic layer, third intrinsic layer and fourth in proper order from the silicon chip openly, and the many intrinsic layers group of second includes fifth intrinsic layer, sixth intrinsic layer and seventh intrinsic layer in proper order from the silicon chip back, wherein:

the first intrinsic layer and the fifth intrinsic layer are formed of CO₂And SiH₄Is obtained by deposition;

the second and sixth intrinsic layers are SiH₄Is obtained by deposition;

the third intrinsic layer is H₂、CH₄And SiH₄Is obtained by deposition;

the fourth intrinsic layer is H₂、CO₂And SiH₄Is obtained by deposition;

the seventh intrinsic featureLayer is formed by₂And SiH₄And performing deposition to obtain the product.

2. The multi-intrinsic-layer amorphous silicon passivation layer structure of claim 1, wherein said silicon wafer is an N-type phosphorus-doped single crystal silicon wafer.

3. A method for preparing the extrinsic layer amorphous silicon passivation layer structure of claim 1, comprising the steps of:

s1, preparing a first multi-characteristic layer group on the front side of the silicon wafer:

s11, preparing a first intrinsic layer: introducing CO₂And SiH₄Carrying out deposition;

s12, preparing a second intrinsic layer: introduction of SiH only₄Carrying out deposition;

s13, preparing a third intrinsic layer: introduction of H₂、CH₄And SiH₄Carrying out deposition;

s14, preparing a fourth intrinsic layer: introduction of H₂、CO₂And SiH₄The deposition is carried out, and the deposition,

s2, preparing a second multi-feature layer group on the back of the silicon wafer:

s21, preparing a fifth intrinsic layer: introducing CO₂And SiH₄Carrying out deposition;

s22, preparing a sixth intrinsic layer: introduction of SiH only₄Carrying out deposition;

s23, preparing a seventh intrinsic layer: introduction of H₂And SiH₄And (6) carrying out deposition.

4. The method of claim 3, wherein in each step, the deposition is performed by PECVD.

5. An HJT cell having the extrinsic layer amorphous silicon passivation layer structure of claim 1.

6. The HJT cell of claim 5, wherein an N-doped layer is deposited on the first multiple intrinsic layer group, and a P-type amorphous silicon layer is deposited on the second multiple intrinsic layer group; a first TCO conductive film is deposited on the N doping layer, and a second TCO conductive film is deposited on the P-type amorphous silicon layer; a first electrode is arranged on the first TCO conductive film, and a second electrode is arranged on the second TCO conductive film.

7. The HJT cell of claim 6, wherein the first electrode and the second electrode are both Ag electrodes.

8. The method of claim 6, comprising the steps of:

s81, obtaining the extrinsic layer amorphous silicon passivation layer structure of claim 1, or preparing the extrinsic layer amorphous silicon passivation layer structure by the method of claim 3;

s82, depositing an N-doped layer on the fourth intrinsic layer, and depositing a P-type amorphous silicon layer on the seventh intrinsic layer;

s83, depositing the first TCO conductive film on the N-doped layer, and depositing the second TCO conductive film on the P-type amorphous silicon layer;

s84, disposing the first electrode on the first TCO conductive film, and disposing the second electrode on the second TCO conductive film.

9. The method according to claim 8, further comprising a step of curing so that good ohmic contacts are formed between the grid line of the first electrode and the first TCO conductive film, and between the grid line of the second electrode and the second TCO conductive film.

10. The method of manufacturing according to claim 8 or 9, wherein in S82, the deposition is performed by PECVD; in S83, deposition is performed using RPD or PVD.

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