CN114695115A - Semiconductor device with fin structure and preparation method thereof - Google Patents

Abstract

The application discloses a semiconductor device with a fin structure and a preparation method thereof, which relate to the field of semiconductors and comprise the steps of obtaining a substrate with a patterned polarity adjusting layer; growing a fin type heterojunction by adjusting the input ratio of the group V source and the group III source, wherein the fin type heterojunction comprises a nitrogen polarity heterojunction in a region of the substrate which is not covered by the patterned polarity adjusting layer and a metal polarity heterojunction positioned on the patterned polarity adjusting layer, and the heights of the nitrogen polarity heterojunction and the metal polarity heterojunction are different; and preparing electrodes to obtain the semiconductor device with the fin structure. The graphical polarity adjusting layer can control the distribution of the metal polarity heterojunction and the nitrogen polarity heterojunction, the growth heights of the metal polarity heterojunction and the nitrogen polarity heterojunction are different under the input ratios of different V-group sources and III-group sources, the fin type heterojunction can be directly grown, etching is not needed, damage caused by etching can be avoided, a channel leakage channel caused by etching damage is also avoided, and off-state leakage current is improved.

Description

A kind of semiconductor device with fin structure and preparation method thereof

technical field

The present application relates to the field of semiconductors, and in particular, to a semiconductor device with a fin structure and a preparation method thereof.

Background technique

With the development of semiconductor technology, the device structure has evolved from a planar structure to a fin-type three-dimensional channel structure. The fin-type channel structure increases the contact area between the gate electrode and the channel layer, and further increases the electron depletion area, so that the semiconductor device has The stronger gate control capability can effectively improve the leakage problem caused by the short channel effect.

At present, the fin structures of semiconductor devices are formed by a top-down dry etching process. After the epitaxial planar structure is fabricated, a mask is fabricated by a photolithography process, and then a three-dimensional channel is etched by dry etching. , a fin structure transistor is obtained. Dry etching will introduce a high density of defect states on the etched surface, and the donor-like defect states will cause serious leakage current, increasing the off-state leakage current and power consumption of the device. When the damage of dry etching is too large, it will cause serious leakage of the device, and even the situation that the device is difficult to turn off. At present, although etching damage can be reduced by wet solution etching, dielectric layer passivation and other processes, high-density etching damage is still difficult to fundamentally remove, and the etching cost is also high.

Therefore, how to provide a device fabrication method without etching damage should be urgently solved by those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a semiconductor device with a fin structure and a preparation method thereof to remove damage caused by etching.

In order to solve the above-mentioned technical problems, the present application provides a preparation method of a semiconductor device with a fin structure, including:

obtaining a substrate formed with a patterned polarity adjustment layer;

A fin heterojunction is grown by adjusting the input ratio of the Group V source to the Group III source, the fin heterojunction comprising nitrogen polar heterojunctions in regions of the substrate not covered by the patterned polarity adjusting layer a mass junction, and a metal polar heterojunction on the patterned polarity adjustment layer, the nitrogen polar heterojunction and the metal polar heterojunction have different heights;

Electrodes are prepared to obtain a semiconductor device with a fin structure.

Optionally, when the height of the metal polar heterojunction is higher than the height of the nitrogen polar heterojunction, the input ratio of the group V source to the group III source is below 2500, and the fin-type heterojunction The mass junction includes a buffer layer, a channel layer, and a barrier layer that are sub-stacked away from all Group V sources and Group III sources.

Optionally, when the height of the metal polar heterojunction is lower than the height of the nitrogen polar heterojunction, the input ratio of the Group V source to the Group III source is greater than 2500, and the fin-type heterojunction The junction includes a buffer layer, a back barrier layer, and a channel layer stacked in sequence in a direction away from the substrate.

Optionally, the fin-type heterojunction further includes an insertion layer.

Optionally, the growing fin heterojunction includes:

The fin-type heterojunction is epitaxially grown by a metal organic compound chemical vapor deposition method, a molecular beam epitaxy method or a magnetron sputtering method.

Optionally, the height difference between the nitrogen polar heterojunction and the metal polar heterojunction is within 500 nm.

Optionally, the substrate is any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate.

Optionally, the width of the fins in the fin-type heterojunction is between 5 nm and 3 μm.

Optionally, after the preparation of the electrode, the method further includes:

A passivation layer is deposited on the surface of the semiconductor device having the fin structure.

The present application also provides a semiconductor device with a fin structure, the semiconductor device with a fin structure is prepared by using any one of the above-mentioned preparation methods for a semiconductor device with a fin structure.

A method for preparing a semiconductor device with a fin structure provided by the present application includes: obtaining a substrate formed with a patterned polarity adjustment layer; junction, the fin heterojunction includes a nitrogen-polar heterojunction in a region of the substrate not covered by the patterned polarity-adjusting layer, and a metal electrode on the patterned-polarity-adjusting layer The nitrogen polar heterojunction and the metal polar heterojunction have different heights; electrodes are prepared to obtain a semiconductor device with a fin structure.

It can be seen that the preparation method in the present application obtains a substrate with a patterned polarity adjustment layer when preparing a fin structure in a semiconductor device, and the patterned polarity adjustment layer can control the metal polarity heterogeneity in the fin heterojunction The distribution of junction and nitrogen polar heterojunction, under different input ratios of group V source and group III source, the growth height of metal polar heterojunction and nitrogen polar heterojunction is different. The input ratio of the group III source directly grows the fin-type heterojunction at the patterned polarity adjustment layer and the region of the substrate without the patterned polarity adjustment layer, and a three-dimensional channel structure can be obtained without etching. The damage caused by the etching can be avoided, the etching cost can be reduced, and the channel leakage channel caused by the etching damage can be avoided, the off-state leakage current can be further improved, and the breakdown characteristics of the semiconductor device can be enhanced and the power consumption can be reduced.

In addition, the present application also provides a semiconductor device with a fin structure having the above advantages.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a flowchart of a method for fabricating a semiconductor device with a fin structure provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of adjusting the height difference between the metal polar heterojunction and the nitrogen polar heterojunction by the input ratio of the group V source and the group III source provided by the embodiment of the present application;

3 is a schematic structural diagram of a fin-type AlGaN/GaN heterojunction provided by an embodiment of the present application;

4 is a schematic structural diagram of a fin-type GaN/AlGaN heterojunction provided by an embodiment of the present application;

5 to 11 are process flow diagrams of a semiconductor device with a fin structure provided by embodiments of the present application;

12 to 14 are partial process flow diagrams of another semiconductor device having a fin structure provided by an embodiment of the present application;

In the figure: 1. Substrate, 2. Patterned polarity adjustment layer, 3. Buffer layer, 4. Channel layer, 5. Barrier layer, 6. Two-dimensional electron gas, 7. Gate dielectric layer, 8. Gate Electrode, 9. Insertion layer, 10. Passivation layer, 2'. Polarity adjusting layer, 5'. Back barrier layer, A. Metal polar heterojunction, B. Nitrogen polar heterojunction.

Detailed ways

In order to make those skilled in the art better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.

As mentioned in the background section, the fin structures of current semiconductor devices are all formed by a top-down dry etching process. Dry etching will introduce a high density of defect states on the etched surface, causing donor-like defects. state can cause severe leakage current, increasing the off-state leakage current and power dissipation of the device. Although etching damage can be reduced by processes such as wet solution etching and dielectric layer passivation, high-density etching damage is still difficult to fundamentally remove, and the etching cost is also high.

In view of this, the present application provides a method for fabricating a semiconductor device with a fin structure, please refer to FIG. 1 , including:

Step S101 : obtaining a substrate on which a patterned polarity adjustment layer is formed.

Optionally, this step includes:

Step S1011: prepare a clean substrate;

Step S1012 : depositing a polarity adjustment layer on the upper surface of the substrate, and etching the polarity adjustment layer by wet etching or dry etching to form a patterned polarity adjustment layer.

Wherein, the substrate includes but is not limited to any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate. The patterned polarity adjustment layer may be an AlN layer, a GaN layer, an Al ₂ O ₃ layer, or the like.

Step S102 : growing a fin heterojunction including nitrogen in the regions of the substrate not covered by the patterned polarity adjustment layer by adjusting the input ratio of the group V source to the group III source A polar heterojunction, and a metal polar heterojunction on the patterned polarity adjustment layer, the nitrogen polar heterojunction and the metal polar heterojunction have different heights.

It should be noted that the growth method of the fin-type heterojunction is not limited in this application, and can be selected by oneself. For example, a metal organic compound chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD for short) method, a molecular beam epitaxy (Molecular Beam Epitaxy, MBE for short) method, or a magnetron sputtering method can be used to epitaxially grow the fin-type heterojunction.

Optionally, the height difference between the nitrogen polar heterojunction and the metal polar heterojunction may be within 500 nm. The width of the fins in the fin-shaped heterojunction may be between 5 nm and 3 μm, wherein the direction of the width is a direction perpendicular to the growth direction of the fin-shaped heterojunction.

For the heterojunction of GaN and AlGaN, the source of group V can be ammonia gas, and the source of group III can be metal organic compounds, such as trimethyl aluminum and the like.

Due to the difference in the metal polarity and the surface energy of nitrogen polarity, the two polar regions also have different rates of adsorption of growth molecules and surface nucleation during growth. Therefore, the present application controls the growth rate of the metal polar heterojunction and the nitrogen polar heterojunction by adjusting the input ratio of the group V source to the group III source in the epitaxial growth to obtain a fin structure.

The schematic diagram of the adjustment of the input ratio of the group V source to the group III source for the height difference between the metal polar heterojunction and the nitrogen polar heterojunction is shown in Figure 2, where the abscissa is the input ratio of the group V source and the group III source, The ordinate is the height difference between the nitrogen polar heterojunction and the metal polar heterojunction. When the V source and the III source are lower than 2500, the organometallic molecules of the metal polar heterojunction are adsorbed on the substrate and desorbed. The probability is less, so the nucleation growth rate is higher, resulting in a larger height of the metal polar heterojunction; when the input ratio of the group V source to the group III source is higher than 2500, the nucleation growth of the nitrogen polar heterojunction At a higher rate, the growth pattern at this time shows that the nitrogen-polar heterojunction grows faster, so the nitrogen-polar heterojunction height is higher under this growth condition.

For different heterojunctions, the height relationship between metal polar heterojunction and nitrogen polar heterojunction is different introduce.

The first one, please refer to FIG. 3 , when the fin heterojunction is an AlGaN/GaN heterojunction, the height of the metal polar heterojunction A is higher than the height of the nitrogen polar heterojunction B, and the The input ratio of the group V source to the group III source is below 2500, and the fin-type heterojunction includes a buffer layer 3 , a channel layer 4 , and a barrier layer 5 stacked in sequence in a direction away from the substrate 1 . The material of the barrier layer 5 is AlGaN, the material of the channel layer 4 is GaN, and the material of the buffer layer 3 is AlxGa1 _{- xN} (0≤x≤1).

The area corresponding to the patterned polarity adjustment layer 2 is the metal polar heterojunction A, the area corresponding to the substrate 1 not covered by the patterned polarity adjustment layer 2 is the nitrogen polar heterojunction B, and the metal polar heterojunction A two-dimensional electron gas 6 is induced in the channel layer 4 of A, and this region has a higher height; the nitrogen polar heterojunction B has a lower height, and no two-dimensional electron gas 6 is generated.

In the AlGaN/GaN heterojunction, since the channel layer 4 and the buffer layer 3 occupy most of the thickness, the input ratio of the group V source and the group III source for epitaxial growth of these two parts can be mainly adjusted.

Further, the AlGaN/GaN heterojunction may further include an intervening layer between the barrier layer and the channel layer to adjust the alignment and uniformity of the interface and reduce scattering.

The second type, please refer to FIG. 4 , when the fin heterojunction is a GaN/AlGaN heterojunction, the height of the metal polar heterojunction A is lower than the height of the nitrogen polar heterojunction B, and the The input ratio of the group V source to the group III source is greater than 2500, and the fin-type heterojunction includes a buffer layer 3 , a back barrier layer 5 ′, and a channel layer 4 stacked in sequence in a direction away from the substrate 1 . The material of the back barrier layer 5 ′ is AlGaN, the material of the channel layer 4 is GaN, and the material of the buffer layer 3 is AlxGa1 _{- xN} (0≤x≤1).

The area corresponding to the patterned polarity adjustment layer 2 is the metal polar heterojunction A, and the area corresponding to the substrate 1 not covered by the patterned polarity adjustment layer 2 is the nitrogen polar heterojunction B, and the nitrogen polar heterojunction A two-dimensional electron gas 6 is induced in the channel layer 4 of B, and the height of this region is relatively high; the height of the metal polar heterojunction A is relatively low, and no two-dimensional electron gas 6 is generated.

Further, the GaN/AlGaN heterojunction may further include an intervening layer between the back barrier layer and the channel layer to adjust the alignment and uniformity of the interface and reduce scattering.

Step S103 : preparing electrodes to obtain a semiconductor device with a fin structure.

The electrodes of the semiconductor device with the fin structure may include an ohmic electrode and a gate electrode. In this case, this step may include:

Step S1031 : depositing an ohmic electrode and a gate dielectric layer on the substrate formed with the fin heterojunction, wherein the gate dielectric layer can reduce the leakage current of the device and adjust the threshold voltage;

Step S1032: depositing a gate electrode.

The fin-type heterojunction prepared in this application is suitable for high-voltage power devices, advanced GaN CMOS (Complementary Metal Oxide Semiconductor) logic circuits, and low-power GaN monolithic microwave integrated circuits, etc. . In the present application, the type of semiconductor device having a fin structure is not limited, as long as it has a fin heterostructure, for example, a fin HEMT (High Electron Mobility Transistor, high electron mobility transistor) and the like.

The preparation method in the present application obtains a substrate with a patterned polarity adjustment layer when preparing a fin structure in a semiconductor device, and the patterned polarity adjustment layer can control the polarity of the metal polarity heterojunction in the fin heterojunction and the The distribution of nitrogen polar heterojunctions, under different input ratios of group V sources and group III sources, the growth heights of metal polar heterojunctions and nitrogen polar heterojunctions are different. The input ratio of the source directly grows the fin-type heterojunction at the area of the patterned polarity adjustment layer and the substrate without the patterned polarity adjustment layer, and a three-dimensional channel structure can be obtained without etching, which can avoid etching. The damage caused by the etching can reduce the etching cost, and also avoid the channel leakage channel caused by the etching damage, further improve the off-state leakage current, and enhance the breakdown characteristics of the semiconductor device and reduce the power consumption.

On the basis of the above-mentioned embodiments, in an embodiment of the present application, the method for preparing a semiconductor device with a fin structure further includes after preparing the electrodes:

A passivation layer is deposited on the surface of the semiconductor device with the fin structure to protect the semiconductor device with the fin structure.

The method for fabricating the semiconductor device with the fin structure in the present application will be further described below by taking the fin-type HEMT device as an example.

Example 1. Fin HEMT device with AlGaN/GaN heterojunction

Step 1: Clean the sapphire substrate 1, as shown in FIG. 5 .

Step 2: Use MOCVD to epitaxially grow a 20nm polarity adjustment layer 2' on the sapphire substrate, as shown in Figure 6; use a photolithography process to prepare a patterned polarity adjustment layer (the active area is grown in the region where the polarity adjustment layer exists) , the region growth isolation region of the non-polar adjustment layer), including the patterned polarity adjustment layer with the characteristic size corresponding to the three-dimensional channel structure ranging from microns to sub-microns, and then use dry etching technology to remove the active area. The polarity adjustment layer is obtained to obtain the substrate 1 with the patterned polarity adjustment layer 2 , as shown in FIG. 7 .

Step 3: Based on the substrate 1 with the patterned polarity adjustment layer 2 prepared in Step 2, the lateral polar structure AlGaN/GaN heterojunction is epitaxially grown in MOCVD, and the AlGaN/GaN heterojunction is from top to bottom respectively. It is a 20 nm Al _0.3 Ga _0.7 N barrier layer 5 , a 1 nm AlN insertion layer 9 , a 200 nm GaN channel layer 4 and a 2 μm GaN high resistance buffer layer 3 , as shown in FIG. 8 . Among them, since the channel layer 4 and the buffer layer 3 occupy most of the thickness of the fin-type HEMT device, the input ratio of the group V source and the group III source of the epitaxial growth in these two parts is mainly adjusted, and the group V source and the group III source are adjusted. The input ratio of the source is adjusted to 2200. The GaN channel layer 4 and the buffer layer 3 are grown, the barrier layer 5 and the insertion layer 9 are grown normally, and the metal polar heterojunction A can be obtained as a higher height, that is, the top of the fin structure , the nitrogen polar heterojunction B has a lower height, that is, the bottom of the fin structure. At this time, the two-dimensional electron gas 6 exists in the GaN channel layer 4 of the metal polar heterojunction A.

Step 4: Prepare a Ti/Al/Ni/Au ohmic electrode region by using a photolithography process and an ohmic electrode process, and perform rapid annealing for 30s at 850° C. in a N ₂ atmosphere to obtain an ohmic electrode with low contact resistance.

Step 5: A 10 nm SiN _x gate dielectric layer 7 is prepared by LPCVD (Low Pressure Chemical Vapor Deposition) method, as shown in FIG. 9 .

Step 6: Prepare and deposit Ni/Au gate electrode 8 by photolithography process and electron beam process, as shown in FIG. 10

Step 7: Deposit a 300 nm SiN _x passivation layer 10 based on a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, as shown in FIG. 11 .

Example 2. Fin HEMT device with GaN/AlGaN heterojunction

Step 1: Clean the sapphire substrate 1, as shown in FIG. 5 .

Step 2: Use MOCVD to epitaxially grow a 20nm polarity adjustment layer 2' on the sapphire substrate, as shown in Figure 6; use a photolithography process to prepare a patterned polarity adjustment layer (the active area is grown in the region where the polarity adjustment layer exists) , the region growth isolation region of the non-polar adjustment layer), including the patterned polarity adjustment layer with the characteristic size corresponding to the three-dimensional channel structure ranging from microns to sub-microns, and then use dry etching technology to remove the active area. The AlN crystallized layer is obtained to obtain the substrate 1 with the patterned polarity adjustment layer 2, as shown in FIG. 7 .

Step 3: Based on the substrate 1 with the patterned polarity adjustment layer 2 prepared in Step 2, epitaxially grow a lateral polar structure GaN/AlGaN heterojunction in MOCVD, and the GaN/AlGaN heterojunction is from top to bottom respectively. It is a 100 nm GaN channel layer 4 , a 50 nm Al _0.3 Ga _0.7 N back barrier layer 5 ′, and a 2 μm GaN high-resistance buffer layer 3 , as shown in FIG. 4 . Among them, by adjusting the input ratio of the V group source to the III group source to 2800 to grow the GaN buffer layer 3, and the back barrier layer 5' and the channel layer 4 to grow normally, it can be obtained that the nitrogen polar heterojunction B is higher. The height is the top of the fin structure, and the metal polar heterojunction A is the lower region, that is, the bottom of the fin structure. At this time, the two-dimensional electron gas 6 exists in the GaN channel layer of the nitrogen polar heterojunction B. 4 in.

Step 4: Prepare a Ti/Al/Ni/Au ohmic electrode region by using a photolithography process and an ohmic electrode process, and perform rapid annealing for 30 s at 850° C. in an N2 atmosphere to obtain an ohmic electrode with low contact resistance.

Step 5: 10 nm SiN _x gate dielectric layer 7 is prepared by LPCVD, as shown in FIG. 12 .

Step 6: Using a photolithography process and an electron beam process, the Ni/Au gate electrode 8 is prepared and deposited, as shown in FIG. 13 .

Step 7: deposit a 300 nm SiN _x passivation layer 10 based on PECVD method, as shown in FIG. 14 .

The present application further provides a semiconductor device with a fin structure, the semiconductor device with a fin structure is prepared by using the method for manufacturing a semiconductor device with a fin structure described in any of the above embodiments.

In the present application, the type of semiconductor device having a fin structure is not limited, as long as it has a fin heterostructure, for example, a fin HEMT (High Electron Mobility Transistor, high electron mobility transistor) and the like.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The semiconductor device with the fin structure and the preparation method thereof provided by the present application have been described in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims (10)

1. A method for preparing a semiconductor device with a fin structure, comprising: obtaining a substrate formed with a patterned polarity adjustment layer; A fin heterojunction is grown by adjusting the input ratio of the Group V source to the Group III source, the fin heterojunction comprising nitrogen polar heterojunctions in regions of the substrate not covered by the patterned polarity adjusting layer a mass junction, and a metal polar heterojunction on the patterned polarity adjustment layer, the nitrogen polar heterojunction and the metal polar heterojunction have different heights; Electrodes are prepared to obtain a semiconductor device with a fin structure. 2 . The method for fabricating a semiconductor device with a fin structure according to claim 1 , wherein when the height of the metal polar heterojunction is higher than the height of the nitrogen polar heterojunction, the The input ratio of the Group V source to the Group III source is below 2500, and the fin-type heterojunction includes a buffer layer, a channel layer, and a barrier layer that are stacked in sequence in a direction away from the substrate. 3. The method for fabricating a semiconductor device with a fin structure according to claim 1, wherein when the height of the metal polar heterojunction is lower than the height of the nitrogen polar heterojunction, the The input ratio of the Group V source to the Group III source is greater than 2500, and the fin-type heterojunction includes a buffer layer, a back barrier layer, and a channel layer stacked in sequence in a direction away from the substrate. 4 . The method for fabricating a semiconductor device with a fin structure according to claim 1 , wherein the fin heterojunction further comprises an insertion layer. 5 . 5. The method for fabricating a semiconductor device with a fin structure according to claim 1, wherein the growing fin heterojunction comprises: The fin-type heterojunction is epitaxially grown by a metal organic compound chemical vapor deposition method, a molecular beam epitaxy method or a magnetron sputtering method. 6 . The method for fabricating a semiconductor device with a fin structure according to claim 1 , wherein the height difference between the nitrogen polar heterojunction and the metal polar heterojunction is within 500 nm. 7 . 7. The method for preparing a semiconductor device with a fin structure according to claim 1, wherein the substrate is a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, or a Si substrate any of the. 8 . The method for fabricating a semiconductor device with a fin structure according to claim 1 , wherein the width of the fin in the fin heterojunction is between 5 nm and 3 μm. 9 . 9. The method for manufacturing a semiconductor device with a fin structure according to any one of claims 1 to 8, wherein after the electrode is prepared, the method further comprises: A passivation layer is deposited on the surface of the semiconductor device having the fin structure. 10. A semiconductor device with a fin structure, characterized in that, the semiconductor device with a fin structure is prepared by using the method for preparing a semiconductor device with a fin structure according to any one of claims 1 to 9 .

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