CN114678434B - A heterojunction battery with improved photoelectric conversion efficiency - Google Patents

Abstract

A heterojunction cell for improving photoelectric conversion efficiency belongs to the technical field of solar cells, comprising an n-type silicon substrate, and intrinsic amorphous silicon deposited on the front and back sides of the n-type silicon substrate; the front side of the n-type silicon substrate is provided with a front electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon in order from top to bottom, and the back side of the n-type silicon substrate is provided with a back electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon in order from bottom to top; wherein the mixed layer comprises a first p-type doped amorphous silicon and The first p-type doped amorphous silicon adopts a hollow design, and the The film layer filling is arranged in the hollow part of the first p-type doped amorphous silicon, and the doped amorphous silicon is the first n-type doped amorphous silicon; through this mixed-phase film layer design, the upper limit of the photogenerated current of the HJT cell can be broken while ensuring that other parameters of the HJT cell remain at the same level, thereby enabling it to achieve a higher conversion efficiency.

Description

A heterojunction battery with improved photoelectric conversion efficiency

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application based on application number 2021116201937, application date: December 18, 2021, and the name of the invention is: A heterojunction battery for improving photoelectric conversion efficiency.

Technical Field

The invention belongs to the technical field of solar cell processing, and in particular relates to a heterojunction cell for improving photoelectric conversion efficiency.

Background technique

The front side of the existing HJT cell structure generally uses intrinsic amorphous silicon superimposed on n-type amorphous silicon. Usually, intrinsic amorphous silicon has a good passivation effect, while n-type amorphous silicon usually plays a more electron selective transmission effect, and p-type amorphous silicon usually plays a more hole selective transmission effect. However, due to the large parasitic absorption of both, the photocurrent of the HJT cell cannot be further improved.

Summary of the invention

The object of the present invention is to provide a heterojunction battery with improved photoelectric conversion efficiency to solve the problems raised in the above background technology.

To achieve the above object, the present invention provides the following technical solutions:

A heterojunction cell for improving photoelectric conversion efficiency, comprising an n-type silicon substrate, and intrinsic amorphous silicon deposited on the front and back sides of the n-type silicon substrate; the front side of the n-type silicon substrate is provided with a front electrode, a first TCO layer, a mixed layer and intrinsic amorphous silicon in order from top to bottom, and the back side of the n-type silicon substrate is provided with a back electrode, a second TCO layer, doped amorphous silicon and intrinsic amorphous silicon in order from bottom to top; wherein the mixed layer comprises a first p-type doped amorphous silicon and film layer, the first p-type doped amorphous silicon adopts a hollow design, the The film layer is filled and arranged in the hollowed-out part of the first p-type doped amorphous silicon, and the doped amorphous silicon is the first n-type doped amorphous silicon.

Compared with the prior art, this technical solution has the following effects:

Through this mixed-phase film design, the upper limit of the photogenerated current of the HJT cell can be broken while ensuring that other parameters of the HJT cell remain at the same level, thereby enabling it to achieve a higher conversion efficiency.

Preferably, the mixed layer comprises a second n-type doped amorphous silicon and film layer, the second n-type doped amorphous silicon adopts a hollow design, the The film layer is filled and arranged at the hollowed-out portion of the second n-type doped amorphous silicon.

Preferably, the doped amorphous silicon is second p-type doped amorphous silicon.

Preferably, the front electrode/back electrode is a full metal electrode.

Preferably, the all-metal electrode comprises a silver electrode or a copper electrode.

Preferably, the thickness of the first TCO layer is 80 nm, and the thickness of the second TCO layer is 200 nm.

Preferably, the thickness of the mixed layer is less than 10 nm.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the overall structure of a first embodiment of the present invention;

FIG2 is a schematic diagram of the overall structure of a second embodiment of the present invention;

FIG3 is a first schematic diagram of a detection data table of an embodiment and a comparative example of the present invention;

FIG. 4 is a second schematic diagram of the detection data table of the embodiment and the comparative example in the present invention.

In the figure: 1-n-type silicon substrate; 2-intrinsic amorphous silicon; 3-mixed layer; 30-first p-type doped amorphous silicon; 31- Film layer; 30´- second n-type doped amorphous silicon; 31´-/> Film layer; 4-first TCO layer; 5-front electrode; 6-first n-type doped amorphous silicon; 6´-p-type doped amorphous silicon; 7-second TCO layer; 8-back electrode.

Detailed ways

The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

As shown in Figures 1-2, a heterojunction cell for improving photoelectric conversion efficiency includes an n-type silicon substrate 1, and intrinsic amorphous silicon 2 deposited on the front and back sides of the n-type silicon substrate 1; the front side of the n-type silicon substrate 1 is provided with a front electrode 5, a first TCO layer 4, a mixed layer 3 and an intrinsic amorphous silicon 2 in sequence from top to bottom, and the back side of the n-type silicon substrate 1 is provided with a back electrode 8, a second TCO layer 7, doped amorphous silicon and an intrinsic amorphous silicon 2 in sequence from bottom to top; wherein the front electrode 5/back electrode 8 is a full metal electrode, and the full metal electrode includes a silver electrode or a copper electrode. Through this mixed phase film layer design, the upper limit of the photogenerated current of the HJT cell can be broken while ensuring that other parameters of the HJT cell remain at the same level, thereby enabling it to achieve a higher conversion efficiency.

In order to further illustrate the film design of the mixed phase mentioned in the above effect, in the first embodiment, the mixed layer 3 includes a first p-type doped amorphous silicon 30 and The film layer 31, the first p-type doped amorphous silicon 30 adopts a hollow design, the The film layer 31 is filled in the hollowed-out portion of the first p-type doped amorphous silicon 30. Its function is that the conventional first p-type doped amorphous silicon 30 contained in the film layer has good hole selection and transport properties and has good contact with the first TCO layer 4. The other part of the film layer The film layer 31 has certain hole selective transmission and high transparency, which can greatly improve the level of photogenerated current.

Specifically, when a silicon wafer is deposited on a CVD device, it is usually placed on a carrier and placed in a deposition chamber inside the CVD device for film deposition. Therefore, the specific steps for preparing the mixed layer 3 are as follows:

1. First, place the silicon wafer to be prepared on the carrier, and then fix the pre-designed mask on the upper surface of the silicon wafer. The hollowed-out part of the mask corresponds to the film structure to be deposited, and the rest is blocked;

2. Similarly, after preparing one film in the mixed layer 3, the mask is replaced so that the blocked area corresponds to the previously deposited area, and the previously blocked area becomes a hollow area, and finally the mixed layer 3 structure is deposited again;

The mask designed in advance in step 1 is hollowed out on the complete mask, so that the deposited film layer is attached to the surface of the silicon wafer to be prepared through the hollowed-out portion.

In addition, in order to simplify the description, the preparation process involving the mixed layer 3 in the following preparation process is named "hard mask method".

In addition, in order to ensure a stable structure of the heterojunction cell, the doped amorphous silicon is a first n-type doped amorphous silicon 6 .

In the second embodiment, the mixed layer 3 includes a second n-type doped amorphous silicon 30' and The film layer 31', the second n-type doped amorphous silicon 30' adopts a hollow design, the / > The film layer 31' is filled in the hollowed-out part of the second n-type doped amorphous silicon 30'. Its function is that the second n-type doped amorphous silicon 30' contained in the film layer has good electron selective transmission properties and has good contact with the first TCO layer 4. At the same time, another part of the film layer The film layer 31' has certain electron selective transmission and high transparency, which can greatly improve the level of photogenerated current.

In addition, the doped amorphous silicon is second p-type doped amorphous silicon 6'.

It is worth noting that the thickness of the first TCO layer 4 is 80 nm, the thickness of the second TCO layer 7 is 200 nm, and the thickness of the mixed layer 3 is less than 10 nm.

In order to more clearly express the structural composition of the heterojunction battery in the above scheme, the specific steps of preparing the heterojunction battery in the above scheme are as follows:

Embodiment 1:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a mixed layer 3 is deposited on the front side of the battery using a hard mask method. The thickness of the mixed layer 3 is 9 nm. When the doped amorphous silicon in S3 is the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6', the mixed layer 3 is the second n-type doped amorphous silicon 30' and / > The film layer 31', specifically, the hard mask template method is to deposit the single layers in the mixed layer 3 respectively through the template;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Embodiment 2:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a mixed layer 3 is deposited on the front side of the battery using a hard mask method. The thickness of the mixed layer 3 is 5 nm. When the doped amorphous silicon in S3 is the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6', the mixed layer 3 is the second n-type doped amorphous silicon 30' and / > The film layer 31', specifically, the hard mask template method is to deposit the single layers in the mixed layer 3 respectively through the template;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Embodiment 3:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a mixed layer 3 is deposited on the front side of the battery using a hard mask method. The thickness of the mixed layer 3 is 1 nm. When the doped amorphous silicon in S3 is the first n-type doped amorphous silicon 6, the mixed layer 3 is the first p-type doped amorphous silicon 30 and film layer 31; when the doped amorphous silicon in S3 is selected as the second p-type doped amorphous silicon 6', the mixed layer 3 is the second n-type doped amorphous silicon 30' and / > The film layer 31', specifically, the hard mask template method is to deposit the single layers in the mixed layer 3 respectively through the template;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Comparative Example 1:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a hard mask method is used to deposit a first p-type doped amorphous silicon 30/a second p-type doped amorphous silicon 6' on the front side of the battery, wherein the thickness of the first p-type doped amorphous silicon 30/the second p-type doped amorphous silicon 6' is 9 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Comparative Example 2:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a hard mask method is used to deposit a first p-type doped amorphous silicon 30/a second p-type doped amorphous silicon 6' on the front side of the battery, wherein the thickness of the first p-type doped amorphous silicon 30/the second p-type doped amorphous silicon 6' is 5 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Comparative Example 3:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a first p-type doped amorphous silicon 30/a second p-type doped amorphous silicon 6' is deposited on the front side of the battery by using a hard mask method, and the thickness of the first p-type doped amorphous silicon 30/the second p-type doped amorphous silicon 6' is 1 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Comparative Example 4:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a hard mask method is used to deposit the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' on the front side of the battery, and the thickness of the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' is 9 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5 and the back electrode 8 are prepared by screen printing technology.

Comparative Example 5:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a hard mask method is used to deposit the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' on the front side of the battery, and the thickness of the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' is 5 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

Comparative Example 6:

First, a textured n-type silicon substrate 1 is selected to prepare a textured surface, that is, a pyramid-shaped light trapping structure is constructed on the surface of the n-type silicon substrate 1;

Next, the intrinsic amorphous silicon 2 is deposited on the back side of the n-type silicon substrate 1;

Secondly, doped amorphous silicon is deposited on the intrinsic amorphous silicon 2 at the back side;

Then, intrinsic amorphous silicon 2 is deposited on the front surface of the n-type silicon substrate 1;

Then, a hard mask method is used to deposit the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' on the front side of the battery, and the thickness of the first n-type doped amorphous silicon 6/the second n-type doped amorphous silicon 30' is 1 nm;

Further, TCO thin film deposition is performed on the front and back sides of the n-type silicon substrate 1;

Finally, the front electrode 5/back electrode 8 is prepared by screen printing technology.

It is worth mentioning that, in this embodiment, the comparative example does not need ,/> The reasons are as follows: Currently, the direct application of such single-layer films in heterojunction cells will bring about a lot of performance degradation. Whether from the perspective of commercialization or technical advantages and disadvantages, such single-layer films are still far behind amorphous silicon. Therefore, we mainly compare the relevant data of single-layer films such as n-type doped amorphous silicon and p-type doped amorphous silicon with the mixed-phase films we designed. The comparison data are shown in Figures 3 and 4:

Among them, A in the table represents Mixed phase film, B represents/> Mixed phase film layer, C represents p-type doped amorphous silicon, D represents n-type doped amorphous silicon. By comparing the data, it can be seen that as the thickness of the film layer gradually increases, the voltage value is obviously in an upward change. In addition, when the film layer is in the same specifications, the current density, fill factor and conversion efficiency have all been improved to a certain extent.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "several" means two or more. In addition, the term "including" and any variation thereof are intended to cover non-exclusive inclusions.

The present invention is described according to the embodiments. Without departing from the principle, the present device can also be modified and improved. It should be pointed out that any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims (1)

1. A heterojunction cell for improving photoelectric conversion efficiency comprises an n-type silicon substrate (1) and intrinsic amorphous silicon (2) deposited on the front and back surfaces of the n-type silicon substrate (1); the method is characterized in that: the front surface of the n-type silicon substrate (1) is sequentially provided with a front electrode (5), a first TCO layer (4), a mixed layer (3) and intrinsic amorphous silicon (2) from top to bottom, and the back surface of the n-type silicon substrate (1) is sequentially provided with a back electrode (8), a second TCO layer (7), doped amorphous silicon and intrinsic amorphous silicon (2) from bottom to top; wherein the hybrid layer (3) comprises a first p-type doped amorphous silicon (30) andThe film layer (31) is formed by adopting a hollowed-out design of the first p-type doped amorphous silicon (30), and the/>The film layer (31) is filled at the hollowed-out part of the first p-type doped amorphous silicon (30); the doped amorphous silicon is first n-type doped amorphous silicon (6), the front electrode (5)/the back electrode (8) is an all-metal electrode, the all-metal electrode comprises a silver electrode or a copper electrode, the thickness of the first TCO layer (4) is 80nm, the thickness of the second TCO layer (7) is 200nm, and the thickness of the mixed layer (3) is smaller than 10nm.