CN114678423A - High voltage semiconductor device - Google Patents

Abstract

A high voltage semiconductor device includes a substrate, a first high voltage well, a second high voltage well, a third high voltage well, a drain region, a source region, a gate structure, and a doped region. The substrate has a first conductivity type. The first high voltage well is disposed over the substrate and has a second conductivity type opposite the first conductivity type. The second high voltage well is disposed adjacent to and in contact with the first high voltage well and has the first conductivity type. The third high voltage well is disposed adjacent to and in contact with the first high voltage well and has the second conductivity type. The drain region is disposed within the first high voltage well. The gate structure is disposed between the source region and the drain region. The doped region is disposed within the third high-voltage well and has the second conductivity type.

Description

High Voltage Semiconductor Devices

technical field

The present invention relates to a high voltage semiconductor device, particularly a high voltage semiconductor device having a doped region in an outer high voltage well.

Background technique

Semiconductor integrated circuit (IC) technology has rapidly developed, in which high-voltage semiconductor device technology has been developed for high voltage and high power. High voltage semiconductor devices include vertically diffused metal oxide semiconductor (VDMOS) transistors and laterally diffused metal oxide semiconductor (LDMOS) transistors, and the advantages of high voltage semiconductor devices are that they are cost-effective, and It is easily compatible with other processes and has been widely used in display driver IC devices, power supplies, power management, communications, automotive electronics or industrial control and other fields.

While the prior art for high voltage semiconductor devices is generally adequate for their intended purpose, they are not satisfactory in all respects. With the development of high-voltage semiconductor device technology, it is expected that the high-voltage semiconductor device can have a larger operating voltage, and thus require a larger breakdown voltage. Therefore, there is a need for a high voltage semiconductor device having a larger breakdown voltage.

SUMMARY OF THE INVENTION

The present invention provides a high-voltage semiconductor device. The high-voltage semiconductor device includes a substrate, a first high-voltage well, a second high-voltage well, a third high-voltage well, a drain region, a source region, a gate structure, and a doped region. The substrate has a first conductivity type. The first high voltage well is disposed over the substrate and has a second conductivity type opposite to the first conductivity type. The second high voltage well is disposed adjacent to and in contact with the first high voltage well and has the first conductivity type. The third high voltage well is disposed adjacent to and in contact with the first high voltage well and has the second conductivity type. The drain region is disposed within the first high voltage well. The gate structure is disposed between the source region and the drain region. The doped region is disposed within the third high voltage well and has the second conductivity type.

In some embodiments, the high-voltage semiconductor device further includes a buried layer disposed under the second high-voltage well and the third high-voltage well and having the second conductivity type.

In some embodiments, the boundary of the buried layer is at a predetermined distance from the boundary between the first high voltage well and the aforementioned second high voltage well.

In some embodiments, the high voltage semiconductor device further includes a dielectric layer, a metal contact, and a metal layer. A dielectric layer is disposed over the substrate. Metal contacts are provided in the dielectric layer and contact the doped regions. A metal layer is disposed over the dielectric layer and contacts the metal contacts.

In some embodiments, the ratio of the depth of the doped region to the depth of the third high voltage well is in the range of 0.006 to 0.01.

The present invention provides a high-voltage semiconductor device. The high voltage semiconductor device includes a substrate, a high voltage well, a first annular well, a second annular well, a drain region, an annular gate structure, an annular source region, and an annular doped region. A high voltage well is disposed over the substrate and has dopants of the first conductivity type. The first annular well is disposed around and in contact with the high voltage well and has a second conductivity type dopant opposite to the first conductivity type dopant. The second annular well is disposed around the first annular well and has a first conductivity type dopant. The drain region is disposed in the high voltage well. A ring gate structure is disposed over the high voltage well and surrounds the drain region. A ring-shaped source region is disposed in the first ring-shaped well and surrounds the ring-shaped gate structure. An annular doped region is disposed within the second annular well and has dopants of the first conductivity type.

In some embodiments, the high voltage semiconductor device further includes an annular buried layer disposed under the first annular well and the second annular well and having a dopant of the first conductivity type.

In some embodiments, the inner boundary of the annular buried layer is a predetermined distance from the outer boundary of the high voltage well.

In some embodiments, the high voltage semiconductor device further includes a dielectric layer, a metal contact, and a metal layer. A dielectric layer is disposed over the substrate. A metal contact is provided in the dielectric layer and contacts the annular doped region. A metal layer is disposed over the dielectric layer and contacts the metal contacts.

In some embodiments, the ratio of the depth of the annular doped region to the depth of the second annular well is in the range of 0.006 to 0.01.

With the development of high voltage semiconductor device technology, it is expected that the high voltage semiconductor device can have a larger operating voltage. Therefore, the high voltage well as an isolation region needs to be improved to have a larger breakdown voltage to avoid high voltage semiconductor devices operating at higher operating voltages without affecting adjacent devices.

Description of drawings

In order to enable the description of the present invention to cover the above examples, other advantages and features, the principles briefly described above will be described in more detail by way of specific examples in the drawings. It should be understood that the drawings shown herein are merely exemplary of the present invention and do not limit the scope of the present invention. The principles of the present invention are described and explained with additional character and detail by reference to the accompanying drawings, wherein:

1A is a top view of a high voltage semiconductor device having doped regions in isolated high voltage wells according to an embodiment of the present invention.

1B is a cross-sectional view of a high voltage semiconductor device having doped regions in isolated high voltage wells according to an embodiment of the present invention.

FIG. 2 is a graph comparing the breakdown voltage of a high voltage semiconductor device according to an embodiment of the present invention and a known high voltage semiconductor device.

3 is a cross-sectional view of a high voltage semiconductor device having a doped region in an isolated high voltage well, wherein a via and a metal layer are additionally formed over the doped region, according to an embodiment of the present invention.

reference number

100: High Voltage Semiconductor Devices

102: Substrate

104: Doping region

106: Doping region

108: Epitaxial layer

110: High Voltage Trap

112: High Voltage Trap

114: High Voltage Trap

116: High Voltage Trap

118: Drift Zone

120: Well

122: drain region

124: Ontology area

126: Doping region

128: Doping region

130: source region

132-1: Oxide Structure

132-2: Oxide Structure

132-3: Oxide Structure

132-4: Oxide Structure

134: Gate structure

136: Doping region

138: Doping region

140: Dielectric layer

142: Through hole

144: Dielectric layer

146: Wire

148: Through hole

150: Wire

H1: depth

H2: depth

D1: Distance

202: Curves

204: Curves

152: Through hole

154: Wire

302: Circuit

304: Resistor

Detailed ways

The following summary provides many different embodiments or examples for implementing different features of the present invention. The following summary describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes that a first feature is formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment where the first feature is in direct contact with the second feature. Embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the different examples described below may reuse the same reference symbols and/or labels. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the particular relationship between the various embodiments and/or structures discussed.

For the purpose of this detailed description, unless specifically denied, the singular includes the plural and vice versa. And the word "comprising" means "includes without limitation." In addition, approximation terms such as "about," "almost," "substantially," "approximately," etc., may be used in embodiments of the present invention in the sense of "at, near, or near" or "at," Within 3 to 5%" or "within acceptable manufacturing tolerance" or any logical combination.

Furthermore, it is a spatially related term. Terms such as "below," "below," "lower," "above," "upper," and similar terms are used to facilitate the description of one device or feature in the illustration to another device or feature The relationship between. These spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the schematic diagrams is turned over, devices described as "below" or "beneath" other devices or features would then be oriented "above" the other devices or features. In this way, the model word "below" will cover both upside and downside interpretations. In addition, the device may be turned in different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein are to be interpreted in the same way.

The terminology used herein is for the purpose of describing particular embodiments only, and does not limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, to the extent that the terms "include", "include", "have", "have", "including" or variations thereof are used in the detailed description and/or the claims, these terms are intended to be used in a manner similar to Inclusive by way of "including".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms such as those defined in general dictionaries should be construed to have the same meanings as they have in the context of the relevant field, and should not be construed as idealized or overly formal, unless expressly so stated herein definition.

The present invention generally relates to high voltage semiconductor devices. In a typical high-voltage semiconductor device, a high-voltage well is used as an isolation region at the outer ring of the high-voltage semiconductor device so that the high-voltage semiconductor device does not affect adjacent devices during operation. However, with the development of high voltage semiconductor device technology, it is expected that the high voltage semiconductor device can have a larger operating voltage. Therefore, the high voltage well as an isolation region needs to be improved to have a larger breakdown voltage to avoid high voltage semiconductor devices operating at higher operating voltages without affecting adjacent devices.

1A is a top view of a high-voltage semiconductor device 100 according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view of the high-voltage semiconductor device 100 according to an embodiment of the present invention. According to some embodiments, the high voltage semiconductor device 100 is formed on the substrate 102 . Substrate 102 may consist substantially of silicon. In some embodiments, substrate 102 may include another elemental semiconductor, such as germanium; compound semiconductors, such as silicon carbide, gallium phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or antimony Indium; alloy semiconductors such as silicon germanium (SiGe), silicon carbon phosphide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs) ), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP); or a combination thereof.

Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (germanium-on-insulator) substrate -insulator; GOI) substrate. Semiconductor-on-insulator substrates may be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

In some embodiments, the substrate 102 may have a first conductivity type, such as a P-type conductivity type or an N-type conductivity type. Specifically, the substrate 102 may have dopants of the first conductivity type, such as P-type dopants or N-type dopants. The N-type dopants may include phosphorus (P), arsenic (As), other N-type dopants, or combinations thereof. P-type dopants may include boron (B), indium (In), other P-type dopants, or combinations thereof.

Doped regions 104 and 106 are provided in substrate 102 . In some embodiments, the doped region 104 may have a second conductivity type (eg, N-type conductivity type or P-type conductivity type) that is opposite to the first conductivity type (eg, P-type conductivity type or N-type conductivity type) of the substrate, And the doped region 106 may have the same first conductivity type as the substrate. Specifically, doped region 104 may have a second conductivity type dopant (eg, N-type dopant or P-type dopant), and doped region 106 may have a first conductivity type dopant (eg, P-type dopant) dopant or N-type dopant). The doped regions 104 and 106 may be formed in the substrate 102 by one or more doping processes, such as a diffusion process or an ion implantation process. In some embodiments, the doping concentration of the doped regions 104 may be in the range of 5× ^{10 12} atoms/cm ³ to about 1×10 ¹³ atoms/cm ³ , and the doped regions The doping concentration of 106 may be in the range of 3×10 ¹² atoms/cm ³ to about 8× ^{10 12} atoms/cm ³ . Furthermore, in some embodiments, the thickness of the doped regions 104 and 106 perpendicular to the top surface of the substrate 102 is about 8 microns. In some embodiments, doped regions 104 and 106 may be referred to as buried layers. In addition, as shown in FIG. 1A , the doped regions 104 and 106 are annular in plan view or have an annular layout (indicated by dashed lines), and thus the doped regions 104 and 106 may also be referred to as annular doped regions.

Referring to FIG. 1B , an epitaxial layer 108 is disposed over the substrate 102 . The epitaxial layer 108 may be an epitaxial semiconductor material having a first conductivity type or a second conductivity type (eg, epitaxially grown silicon (Si) or other suitable material). In some embodiments, the epitaxial layer 108 may be formed by metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE) ), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (chloride-vapor phase epitaxy; Cl-VPE), other process methods or combinations thereof.

Still referring to FIG. 1B , high voltage wells 110 , 112 , 114 , 116 are disposed in epitaxial layer 108 . In some embodiments, the high voltage wells 112, 116 may have a first conductivity type (ie, have dopants of the first conductivity type), and the high voltage wells 110, 114 may have a second conductivity type (ie, have dopants of the second conductivity type) thing). Similar to doped regions 104 and 106, high voltage wells 110, 112, 114, 116 may be formed in epitaxial layer 108 by one or more doping processes. Notably, the high voltage wells 110, 112 are adjacent and in contact with each other, while the high voltage wells 112, 114, 116 are spaced apart from each other. In addition, as shown in FIG. 1A , the high-voltage wells 112 , 114 , and 116 are annular or have a ring-shaped layout in plan view, and thus the high-voltage wells 112 , 114 , and 116 may also be called annular wells or annular high-voltage wells, in which the high-voltage well 112 surrounds High voltage well 110 , high voltage well 114 surrounds high voltage well 112 , and high voltage well 116 surrounds high voltage well 114 .

1B again, the drift region 118 is disposed in the high voltage well 110, the well 120 is disposed in the drift region 118, and the drain region 122 is disposed in the well 120, wherein the drift region 118, the well 120, and the drain region 122 all have The second conductivity type (ie, having the second conductivity type dopant). In some embodiments, the doping concentration of drain region 122 is greater than the doping concentration of well 120 , the doping concentration of well 120 is greater than the doping concentration of drift region 118 , and the doping concentration of drift region 118 is greater than that of high voltage well 110 doping concentration. In some embodiments, the doping concentration of the high voltage well 110 may be in the range of 1×10 ¹² atoms/cm ³ to about 5× ^{10 12} atoms/cm ³ and the doping concentration of the drift region 118 may be in the range of 6×10 ¹² atoms/cm ³ to about 6×10 12 atoms/cm 3 In the range of 9×10 ¹³ atoms/cm ³ , the doping concentration of the well 120 may be in the range of 1×10 ¹³ atoms/cm ³ to about 5×10 ¹³ atoms/cm ³ , and the drain region 122 may be in the range of 1×10 ¹⁵ atoms/cm ³ to In the range of about 5x10 ¹⁵ atoms/cm ³ .

A body region 124 is formed in the high voltage well 112 , and a source region 130 is formed in the body region 124 , wherein the source region 130 includes doped regions 126 , 128 . Body regions 124 and doped regions 126 have a first conductivity type (ie, have dopants of the first conductivity type), and doped regions 128 have a second conductivity type (ie, have dopants of the second conductivity type). In some embodiments, the doping concentration of the doped regions 126 , 128 is greater than the doping concentration of the body region 124 , and the doping concentration of the body region 124 is greater than the doping concentration of the high voltage well 112 . In some embodiments, the doping concentration of the doped regions 126 , 128 may be in the range of 1×10 ¹⁵ atoms/cm ³ to about 5× ^{10 15} atoms/cm ³ , and the doping concentration of the body region 124 may be 1×10 ¹³ atoms/cm 3 cm ³ to about 5×10 ¹³ atoms/cm ³ range. As described above, similar to high voltage wells 110, 112, 114, 116, drift region 118, well 120, drain region 122, body region 124, and doped regions 126 and 128 may each be doped by one or more Process formed.

Complex oxide structures 132 - 1 , 132 - 2 , 132 - 3 , 132 - 4 are disposed on and partially embedded in epitaxial layer 108 . In some embodiments, oxide structures 132-1, 132-2, 132-3, 132-4 may be composed of silicon oxide, silicon nitride, or silicon oxynitride, and may be a partial oxidation of silicon formed by thermal oxidation (local oxidation of silicon; LOCOS). In other embodiments, the oxide structures 132-1, 132-2, 132-3, and 132-4 may be shallow trench isolation (STI) structures formed by etching and deposition processes.

The gate structure 134 is disposed on the epitaxial layer 108 and may include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon oxide, silicon oxynitride, silicon aluminum oxide, high-k dielectric materials (eg, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials or a combination thereof, and may be formed by chemical vapor deposition (CVD), spin coating, or other suitable processes. The gate electrode layer may comprise amorphous silicon, polycrystalline silicon, one or more metals, metal nitrides, conductive metal oxides, other suitable materials, or combinations thereof, and may be heated by CVD, sputtering, resistance heating Evaporation, e-beam evaporation, or other suitable deposition process. Notably, as shown in FIG. 1B, a portion of the gate structure 134 is disposed on the oxide structure 132-1. In this embodiment, the oxide structure 132-1 may be referred to as a field oxide to increase the drain-to-gate punchthrough voltage.

In some embodiments, the gate structure 134 may further include one or more work function metal layers to adjust the work function of the gate structure 134 . The material of the work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium disilicide (ZrSi2) , Molybdenum Disilicide (MoSi2), Tantalum Disilicide (TaSi2), Nickel Disilicide (NiSi2), Titanium (Ti), Silver (Ag), Titanium Aluminum (TiAl), Titanium Aluminum Carbide (TiAlC), Titanium Aluminum Nitride ( TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), other suitable work function materials, or combinations thereof, and the work function metal layer may Deposited by atomic layer deposition (ALD), CVD, and/or other suitable processes.

As shown in FIG. 1A , the source region 130 is annular in plan view or has an annular layout, and thus the source region 130 may also be referred to as an annular source region, and surrounds the high voltage well 110 and the drain region 122 . In addition, although not shown in FIG. 1A , in this embodiment, the gate structure 134 may also be annular or have an annular layout, and thus the gate structure 134 may also be referred to as a ring gate structure and surround the drain region 122 . Therefore, the source region 130 also surrounds the gate structure 134 , or the gate structure 134 is disposed between the drain region 122 and the source region 130 .

The doped regions 136, 138 may be individually disposed in the high voltage wells 114 and 116 by one or more doping processes. Doped region 138 has a first conductivity type (ie, has a first conductivity type dopant), and doped region 136 has a second conductivity type (ie, has a second conductivity type dopant). In some embodiments, the doping concentrations of the doped regions 136 , 138 are greater than the doping concentrations of the high voltage wells 114 and 116 , respectively. In some embodiments, the doping concentration of the doped regions 136 , 138 may be in the range of 1×10 ¹⁵ atoms/cm ³ to about 5× ^{10 15} atoms/cm ³ . In addition, as shown in FIG. 1A , the doped regions 136 and 138 are annular in plan view or have an annular layout, so the doped regions 136 and 138 can also be called annular doped regions, wherein the doped regions 136 surround the high voltage well 110 , the drain region 122, the gate structure 134, the high voltage well 112, and the source region 130, and the doped region 138 surrounds the high voltage well 110, the drain region 122, the gate structure 134, the high voltage well 112, the source region 130, High voltage well 114 , and doped region 136 .

Referring again to FIG. 1B , an interconnect structure is disposed over epitaxial layer 108 . The interconnect structure may include a plurality of conductive features configured to interconnect the high voltage semiconductor device 100 with additional devices, components, voltage sources, etc. to ensure proper function of the high voltage semiconductor device 100 . The interconnect structure includes various conductive and dielectric layers. The conductive layers are configured to form vertical interconnect features, such as vertical interconnect structures (eg, vias 142, 148) and/or horizontal interconnect structures (eg, wires 146, 150). Each horizontal interconnect feature disposed in the dielectric layer may be referred to as a "metal layer," and two different metal layers may be electrically coupled by one or more vertical interconnect structures. Various conductive layers are embedded in the dielectric layers, such as dielectric layers 140 and 144 . As shown in FIG. 1B , the source region 130 and the doped region 138 are respectively connected to the via 142 and the wire 146 , and the drain region 122 is connected to the via 142 , the wire 146 , the via 148 , and the wire 150 . Each conductive layer (eg, vias 142, 148 and wires 146, 150) may include copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), other suitable metals, or the like In combination, and in some embodiments may further include a barrier layer comprising titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN). Dielectric layers 140 and 144 may be referred to as interlayer dielectric (ILD) layers. In some embodiments, dielectric layers 140 and 144 may include silicon oxide, tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (borophosphosilicate glass; BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), other suitable dielectric materials or its combination. In some embodiments, dielectric layers 140 and 144 may be formed using CVD, flowable CVD (FCVD), or spin-on-glass.

As described above, in the embodiment of the present invention, the high-voltage well 114 is used as an isolation region on the outer ring of the high-voltage semiconductor device 100 so that the high-voltage semiconductor device does not affect adjacent devices during operation. In order for the high voltage semiconductor device 100 to operate at a larger operating voltage without affecting adjacent devices, the lateral punch voltage of the high voltage semiconductor device 100 needs to be increased. In an embodiment of the present invention, the doped region 136 is disposed in the high voltage well 114 to further increase the lateral breakdown voltage. As described above, the doping concentration of the doped region 136 is greater than the doping concentration of the high voltage well 114 . As such, since the dopant of the doped region 136 can be partially diffused into the high voltage well 114, the doping concentration of the high voltage well 114 is increased, and thus the depletion region is reduced to have a larger lateral breakdown voltage. Notably, the doped region 136 is disposed on the upper portion of the high voltage well 114 . Specifically, the ratio of the depth H1 of the doped region 136 to the depth H2 of the high voltage well 114 is in the range of about 0.006 to about 0.01. If the depth H1 of the doped region 136 is too small, the lateral breakdown voltage cannot be effectively increased. If the depth H1 of the doped region 136 is too deep, it will cause the junction breakdown voltage (JunctionBreakdown) of the device to drop (will cause the breakdown of the high voltage well 114 to the high voltage well 116 ).

FIG. 2 is a graph comparing the breakdown voltage of the high-voltage semiconductor device 100 according to an embodiment of the present invention and a conventional high-voltage semiconductor device. The peripheral high-voltage wells of known high-voltage semiconductor devices do not have doped regions, while the peripheral high-voltage wells of high-voltage semiconductor device 100 (eg, high-voltage well 114 ) have doped regions (eg, doped regions 136 ). As shown in FIG. 2 , in the drain current-drain voltage characteristic diagram (Id-Vd characteristic diagram), curves 202 and 204 respectively represent the Id-Vd characteristic of the known high voltage semiconductor device and the high voltage semiconductor device 100 . When the drain voltage of a known high voltage semiconductor device increases to about 90V, lateral breakdown occurs and the drain current rises sharply. In contrast, since the peripheral high-voltage well of the high-voltage semiconductor device 100 has a doped region, the lateral breakdown occurs only when the drain voltage increases to about 167V, and the drain current increases sharply. Therefore, arranging doped regions in the peripheral high-voltage well of the high-voltage semiconductor device can effectively increase the lateral breakdown voltage.

Referring again to FIGS. 1A and 1B , the doped region 104 is disposed below the high voltage wells 112 and 114 . It should be noted that, in the embodiment of the present invention, the doped region 104 does not extend below the high voltage well 110 . Specifically, the boundary of the doped region 104 (as shown in FIG. 1A , the inner boundary of the doped region 104 ) and the boundary of the high-voltage well 110 (as shown in FIG. 1A , the outer boundary of the high-voltage well 110 ) are separated by a predetermined distance D1 to prevent leakage from the drain region 122 to the doped region 104 . In addition, if the distance D1 is too large, the doped region 104 cannot effectively prevent vertical leakage from the high voltage well 112 to the substrate 102 .

FIG. 3 is a cross-sectional view of a high voltage semiconductor device 100 according to another embodiment, wherein vias 152 and wires 154 are additionally formed over the doped regions 136 . In this case, the doped region 136 , the high voltage well 114 , the doped region 104 , and the drain region 122 may constitute the circuit 302 . As mentioned above, the boundary of the doped region 104 is separated from the boundary of the high voltage well 110 by a distance D1 , which constitutes the resistance 304 in the circuit 302 . In this embodiment, by measuring the resistance value of the resistor 304 in the circuit 302, it can be monitored whether the distance D1 meets the design. Specifically, the sequence of processes used to form the high voltage semiconductor device 100 may affect the profile of the doped region 104 . For example, the process of the high voltage semiconductor device 100 may cause the doped region 104 to extend below the extended high voltage well 110 (ie, the distance D1 decreases), and thus cause the resistance value of the resistor 304 in the circuit 302 to decrease. As a result, the resulting high voltage semiconductor device 100 may experience leakage from the drain region 122 to the doped region 104 during operation. Therefore, by measuring the resistance value of the resistor 304 in the circuit 302, it can be determined whether the high-voltage semiconductor device 100 meets the design requirements or has defects.

Embodiments of the present invention provide a number of advantages over the prior art, and it is understood that other embodiments may provide different advantages, all of which need not be discussed here, and none of which are specific.

The foregoing has outlined the features of the many embodiments so that those skilled in the art may better understand the invention from its various aspects. Those skilled in the art should appreciate and can easily design or modify other processes and structures based on the present invention and thereby achieve the same purposes and/or the same advantages as the embodiments and the like described herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the invention. Various changes, substitutions or modifications can be made in the present invention without departing from the spirit and scope of the invention.

Claims (10)

1. A high voltage semiconductor device, comprising:

a substrate having a first conductivity type;

a first high voltage well disposed above the substrate and having a second conductivity type opposite to the first conductivity type;

a second high voltage well disposed adjacent to and in contact with the first high voltage well and having the first conductivity type;

a third high voltage well disposed adjacent to and in contact with the first high voltage well and having the second conductivity type;

a drain region disposed in the first high-voltage well;

A source region disposed in the second high voltage well;

a gate structure disposed between the source region and the drain region; and

and a doped region disposed in the third high-voltage well and having the second conductivity type.

2. The high voltage semiconductor device of claim 1, further comprising:

and a buried layer disposed under the second high voltage well and the third high voltage well and having the second conductive type.

3. The high voltage semiconductor device of claim 2, wherein a boundary of said buried layer is spaced apart from a boundary between said first high voltage well and said second high voltage well by a predetermined distance.

4. The high voltage semiconductor device of claim 2, further comprising:

a dielectric layer disposed above the substrate;

a metal contact disposed in the dielectric layer and contacting the doped region; and

a metal layer disposed above the dielectric layer and contacting the metal contact.

5. The high voltage semiconductor device of claim 2, wherein a ratio of a depth of the doped region to a depth of the third high voltage well is in a range of 0.006 to 0.01.

6. A high voltage semiconductor device, comprising:

a substrate;

a high voltage well disposed above the substrate and having a first conductive type dopant;

a first ring-shaped well surrounding and contacting the high-voltage well and having a second conductive type dopant opposite to the first conductive type dopant;

a second ring-shaped well which is arranged around the first ring-shaped well and has the first conductive type dopant;

a drain region disposed in the high voltage well;

a ring-shaped gate structure disposed above the high-voltage well and surrounding the drain region;

an annular source region disposed in the first annular well and surrounding the annular gate structure; and

and an annular doped region disposed in the second annular well and having the first conductive type dopant.

7. The high voltage semiconductor device of claim 6, further comprising:

an annular buried layer disposed under the first and second ring wells and having the first conductive type dopant.

8. The high voltage semiconductor device of claim 7, wherein an inner boundary of said annular buried layer is spaced a predetermined distance from an outer boundary of said high voltage well.

9. The high voltage semiconductor device of claim 7, further comprising:

a dielectric layer disposed above the substrate;

a metal contact disposed in the dielectric layer and contacting the annular doped region; and

a metal layer disposed above the dielectric layer and contacting the metal contact.

10. The high voltage semiconductor device of claim 6, wherein a ratio of a depth of the ring-shaped doped region to a depth of the second ring-shaped well is in a range of 0.006 to 0.01.

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