CN114678383A - A TFT array substrate structure with improved metal residue and its manufacturing method - Google Patents

Abstract

The invention discloses a TFT array substrate structure with improved metal residues and a manufacturing method thereof. The TFT array substrate structure with improved metal residues comprises a TFT side glass substrate on which a buffer layer with grooves is arranged, The shape of the groove is a trapezoid with a large upper and a small lower, a GE metal layer is deposited in the groove of the buffer layer, a GI insulating layer is arranged on the GE metal layer, and a GI insulating layer is arranged on the GI insulating layer. PV insulating layer. In the present invention, a buffer layer with groove design is added on the glass substrate, so that the GE metal layer traces are deposited in the buffer layer, and the CMP process is used to flatten the surface of the buffer layer, so that the GE metal layer and the buffer layer are flattened. The layers are coplanar, which eliminates the existence of GE Taper and eliminates the metal residue caused by GE Taper, so as to achieve the purpose of improving product yield.

Description

A TFT array substrate structure with improved metal residue and its manufacturing method

technical field

The invention relates to the field of display technology, in particular to a TFT array substrate structure with improved metal residues and a manufacturing method thereof.

Background technique

IGZO is an amorphous oxide containing indium, gallium and zinc. The carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly improve the charge and discharge rate of TFT to the pixel electrode, improve the response speed of the pixel, and have better performance. Fast panel refresh rate, enabling ultra-high resolution TFT-LCD. At the same time, the existing amorphous silicon production line can be compatible with the IGZO process with only minor modifications, so lower temperature polysilicon (LTPS) is more competitive in terms of cost.

At this stage, as the market demand for narrow borders of LCD displays is obvious, and low-cost, high-resolution IGZO panels have gradually become a hot spot for development, but with the improvement of resolution, the Short chanel (short channel) design of IGZO TFT devices The process requirements are getting higher and higher. The line width and precision of the metal layer, the selection/matching of the film quality of the metal layer and the non-metal layer directly affect the stability of the electrical characteristics of the TFT device.

In terms of manufacturing process, the existing metal layer etching methods of TFT array substrates are mainly wet etching (Mo/Al/Mo as an example) and dry etching (Ti/Al/Ti as an example). Due to various design requirements such as CD size accuracy, TFT device Short chanel design, and the combination of different metal/inorganic film layers, Ti/Al/Ti is often used as the metal of the SD layer, but in the actual mass production process, it will be found that on the side of the GE layer Taper There will be some SD metal residues very easily at the place, which will cause poor coverage of the post-processing film stack and short circuit of the adjacent SD metal lines, which will ultimately affect the yield of the product. In addition to the need to continue to improve the dry etching process in the current process, in fact, the large GE Taper (the angle of the side metal layer after the GE metal is etched) is often the main process reason for the residual SD metal, and slowing down the GE Taper is still the process. The difficulties that need to be overcome have not yet been improved. Therefore, on the basis of the existing process capability, how to avoid metal residues in the SD layer has become a technical key.

SUMMARY OF THE INVENTION

The present invention aims to provide a TFT array substrate structure with improved metal residues and a manufacturing method thereof. With the existing designed photomask and manufacturing process, a buffer layer is added to avoid metal residues caused by GE Taper, so as to achieve improved performance. The purpose of product yield.

To achieve the above object, the present invention adopts the following technical solutions:

A TFT array substrate structure for improving metal residues, comprising a TFT side glass substrate, a buffer layer with grooves is provided on the glass substrate, and the shape of the grooves is a trapezoid shape with a large upper and a smaller lower; A GE metal layer is deposited in the groove of the buffer layer, a GI insulating layer is arranged on the GE metal layer, and a PV insulating layer is arranged on the GI insulating layer.

Further, the upper surface of the buffer layer and the GE metal layer are flush.

The buffer layer is usually made of SiOx, which can not only be applied to planarize the glass surface, but also pattern a corresponding groove shape in a specific area.

The GE metal layer has low resistivity, and can be selected from metals with good electrical conductivity such as aluminum/molybdenum/titanium/nickel/copper, and alloys, such as Mo/Al/Mo or Ti/Al/Ti.

The GI insulating layer is an insulating layer with a larger dielectric constant and is formed of SiOx or SiNx material.

The PV insulating layer is an insulating layer with a larger dielectric constant, and is formed of SiOx or SiNx material.

A method for manufacturing a TFT array substrate structure with improved metal residues, comprising the following steps:

1) A buffer layer is formed on a glass substrate by chemical vapor deposition;

2) Weakly expose the buffer layer by GE illumination, so that the buffer layer forms a groove model with a large upper and a small lower.

3) Deposit a GE metal layer in the groove of the buffer layer,

4) In order to eliminate the GE metal layer higher than the upper surface of the buffer layer, the chemical mechanical planarization (CMP) process is used to grind the GE metal layer with a polishing pad and slurry, and the GE metal layer protruding from the upper surface of the buffer layer will be ground. smooth;

4-1) Use Al ₂ O ₃ slurry to grind and remove most of the GE metal layer, leaving a thin and uniform GE metal layer (the thickness of the GE metal layer before grinding is about 3000A, and the remaining GE metal layer after grinding The thickness is about 500A) the pressure is 0.4~0.8MPa, and the grinding rate is 800~1500A/min;

4-2) Using Al ₂ O ₃ grinding fluid, grind the remaining thin and uniform GE metal layer with low pressure and grinding rate, the pressure is 0.05~0.1MPa, and the grinding rate is 100~300A/min;

4-3) Polish the barrier layer, use Al ₂ O ₃ grinding fluid, and use a polishing pad to polish the GE metal barrier layer protruding from the upper surface of the buffer layer;

5) A GI insulating layer is formed on the GE metal layer by chemical vapor deposition;

6) A PV insulating layer is formed by chemical vapor deposition on the GI insulating layer.

The present invention adopts the above technical scheme, on the basis of the original design and without adding a photomask, a buffer layer with groove design is added on the glass substrate, so that the GE metal layer traces are deposited in the buffer layer, and the new A chemical mechanical polishing (CMP) process is added to planarize the surface of the buffer layer, so that the GE metal layer and the buffer layer are coplanar, which eliminates the existence of GE Taper and eliminates the metal residue caused by GE Taper. The purpose of product yield.

Description of drawings

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments;

1 is a schematic diagram of a structure of a conventional TFT array substrate;

FIG. 2 is a schematic diagram of the manufacturing step 1 of the TFT array substrate structure with improved metal residues according to the present invention;

3 is a schematic diagram of the manufacturing step 2 of the TFT array substrate structure with improved metal residues according to the present invention;

4 is a schematic diagram of the manufacturing step 3 of the TFT array substrate structure with improved metal residues according to the present invention;

5 is a schematic diagram 1 of the manufacturing step 4 of the TFT array substrate structure with improved metal residues according to the present invention;

6 is a schematic diagram 2 of the manufacturing step 4 of the TFT array substrate structure with improved metal residues according to the present invention;

7 is a schematic diagram of the manufacturing step 5 of the TFT array substrate structure with improved metal residues according to the present invention;

FIG. 8 is a schematic diagram of the manufacturing step 6 of the TFT array substrate structure with improved metal residues according to the present invention.

Detailed ways

As shown in FIG. 1 , a TFT array substrate structure with improved metal residues of the present invention includes a TFT side glass substrate 1 , and a buffer layer 2 with grooves is provided on the glass substrate 1 . The shape is a trapezoid with a large upper and a lower lower, and a GE metal layer 3 is deposited in the groove of the buffer layer, and the upper surfaces of the buffer layer 2 and the GE metal layer 3 are flush, and the GE metal layer 3 is provided with There is a GI insulating layer 4 on which a PV insulating layer 5 is provided.

Further, the buffer layer 2 is usually selected from SiOx, which can not only be applied to planarize the glass surface, but also pattern a corresponding groove shape in a specific area.

Further, the GE metal layer 3 has low resistivity, and can be selected from aluminum/molybdenum/titanium/nickel/copper/other metals with good electrical conductivity and alloys, such as Mo/Al/Mo or Ti/Al/Ti.

Further, the GI insulating layer 4 is an insulating layer with a relatively large dielectric constant, and is formed of SiOx or SiNx material.

Further, the PV insulating layer 5 is an insulating layer with a relatively large dielectric constant, and is formed of SiOx or SiNx material.

As shown in one of Figures 2-8, a method for manufacturing a TFT array substrate structure with improved metal residues includes the following steps:

1) A buffer layer is formed on a glass substrate by chemical vapor deposition;

2) Weakly expose the buffer layer by GE illumination, so that the buffer layer forms a groove model with a large upper and a small lower.

3) Deposit a GE metal layer in the groove of the buffer layer,

4) In order to eliminate the GE metal layer higher than the upper surface of the buffer layer, the chemical mechanical planarization (CMP) process is used to grind the GE metal layer with a polishing pad and slurry, and the GE metal layer protruding from the upper surface of the buffer layer will be ground. smooth;

4-1) Use Al ₂ O ₃ slurry to grind and remove most of the GE metal layer, leaving a thin and uniform GE metal layer (the thickness of the GE metal layer before grinding is about 3000A, and the remaining GE metal layer after grinding The thickness is about 500A) the pressure is 0.4~0.8MPa, and the grinding rate is 800~1500A/min;

4-2) Using Al ₂ O ₃ grinding fluid, grind the remaining thin and uniform GE metal layer with low pressure and grinding rate, the pressure is 0.05~0.1MPa, and the grinding rate is 100~300A/min;

4-3) Polish the barrier layer, use Al ₂ O ₃ grinding fluid, and use a polishing pad to polish the GE metal barrier layer protruding from the upper surface of the buffer layer;

4-3) Polish the barrier layer, use Al ₂ O ₃ abrasive slurry, and use a softer abrasive pad to polish the GE metal barrier layer protruding from the upper surface of the buffer layer;

5) A GI insulating layer is formed on the GE metal layer by chemical vapor deposition;

6) A PV insulating layer is formed by chemical vapor deposition on the GI insulating layer.

The invention has the following beneficial effects: on the basis of the original design and without adding a photomask, a buffer layer with groove design is added on the glass substrate, so that the GE metal layer wiring is deposited in the buffer layer, and the use of In the CMP process, the surface of the buffer layer is flattened so that the GE metal layer and the buffer layer are coplanar, which eliminates the existence of GE Taper and eliminates the metal residue caused by GE Taper, so as to achieve the purpose of improving product yield.

The implementation of the present invention is described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are illustrative rather than limiting the present invention. Those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions recorded in the foregoing embodiments, or some or all of the technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention, All of them should be covered within the scope of the claims and description of the present invention.

Claims (8)

1. The utility model provides an improve remaining TFT array substrate structure of metal, includes TFT side glass substrate, its characterized in that:

the glass substrate is provided with a buffer layer with a groove, the groove is in a trapezoid shape with a large upper part and a small lower part, a GE metal layer is deposited in the groove of the buffer layer, a GI (glass electrode) insulating layer is arranged on the GE metal layer, and a PV (photovoltaic) insulating layer is arranged on the GI insulating layer.

2. The TFT array substrate structure of claim 1, wherein: the buffer layer is flush with the upper surface of the GE metal layer.

3. The TFT array substrate structure of claim 1, wherein: the buffer layer is formed of a SiOx material.

4. The TFT array substrate structure of claim 1, wherein: the GE metal layer is formed from aluminum, molybdenum, titanium, nickel, copper, or alloys thereof.

5. The TFT array substrate structure of claim 1, wherein: the GI insulation layer is made of SiOx or SiNx materials.

6. The TFT array substrate structure of claim 1, wherein: the PV insulating layer is made of SiOx or SiNx materials.

7. The method according to any of claims 2 to 6, wherein the method comprises: the method comprises the following steps:

1) forming a buffer layer on a glass substrate by a chemical vapor deposition method;

2) carrying out weak exposure on the buffer layer through GE illumination to enable the buffer layer to form a groove model with a large upper part and a small lower part;

3) depositing a GE metal layer in the groove of the buffer layer;

4) grinding the GE metal layer by using a grinding pad and grinding liquid by adopting a CMP (chemical mechanical polishing) process, and grinding the GE metal layer protruding out of the upper surface of the buffer layer to be flat;

5) forming a GI insulation layer on the GE metal layer by a chemical vapor deposition method;

6) a PV insulation layer is formed on the GI insulation layer by a chemical vapor deposition method.

8. The manufacturing method of the TFT array substrate structure for improving metal residue as claimed in claim 7, wherein: the step 4) is as follows:

4-1) with Al₂O₃Grinding the grinding liquid to remove most of the GE metal layer and leave a thin and uniform GE metal layer, wherein the pressure is 0.4-0.8 MPa, and the grinding speed is 800-1500A/min;

4-2) with Al₂O₃Grinding the residual thin and uniform GE metal layer by using grinding liquid at a low pressure and grinding rate, wherein the pressure is 0.05-0.1 MPa, and the grinding rate is 100-300A/min;

4-3) polishing the barrier layer by using Al₂O₃And the grinding liquid is used for polishing the GE metal barrier layer protruding out of the upper surface of the buffer layer by using a grinding pad.

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