CN114666014B

CN114666014B - Self-adaptive frame structure data link transmission system and method

Info

Publication number: CN114666014B
Application number: CN202210561276.1A
Authority: CN
Inventors: 黄立; 查迎弟; 郑浩; 杨俊�; 程俊
Original assignee: Wuhan Gaode Micro Electromechanical And Sensing Industrial Technology Research Institute Co ltd; Wuhan Guide Infrared Co Ltd
Current assignee: Wuhan Gaode Micro Electromechanical And Sensing Industrial Technology Research Institute Co ltd; Wuhan Guide Infrared Co Ltd
Priority date: 2022-05-23
Filing date: 2022-05-23
Publication date: 2022-09-20
Anticipated expiration: 2042-05-23
Also published as: CN114666014A

Abstract

A self-adaptive frame structure data chain transmission system and method, including UART serial port, development platform, RF transceiver and RF antenna, the development platform includes PS module and PL module, UART, PS, PL, RF transceiver and RF antenna make up the data and receive and dispatch the channel; the PS is used for configuring all parameters required by the whole system and determining the current frame structure of the PL in real time according to the related indexes fed back by the PL, and the PL is used for realizing the function of a physical layer under the current frame structure according to the configuration of the PS; the sending channel is as follows: the PS receives information sent by the UART, splices the information with local information and sends the information to the PL, the information is processed by a physical layer in the PL and then sent to the RF transceiver, and the RF transceiver is processed and then sent to the RF antenna; the receiving channel is as follows: the RF antenna receives signals coupled by the antenna, the signals are processed and then sent to the RF transceiver, the signals are processed and then sent to the PL, the signals are analyzed by a physical layer in the PL and then sent to the PS, and the effective information is decoded by the PS and then displayed on the upper computer through the UART serial port.

Description

Self-adaptive frame structure data link transmission system and method

Technical Field

The invention relates to the field of data link communication, in particular to a self-adaptive frame structure data link transmission system and a self-adaptive frame structure data link transmission method.

Background

The prior patents refer to a frame structure, such as standard communication protocols like LTE, CDMA, etc., the frame structure is fixed; for example, a special communication protocol applied to data link communication, the patent describes a system, and the construction of the frame structure is not explicitly described.

Disclosure of Invention

In view of the technical defects and technical drawbacks in the prior art, embodiments of the present invention provide an adaptive frame structure data link transmission system and method that overcome the above problems or at least partially solve the above problems, and the specific scheme is as follows:

as a first aspect of the present invention, there is provided an adaptive frame structure data chain transmission system, the system comprising: the UART device comprises a UART serial port, an embedded development platform, an RF transceiver and an RF antenna, wherein the embedded development platform comprises a PS module and a PL module, and the UART serial port, the PS module, the PL module, the RF transceiver and the RF antenna form a data transceiving channel;

the PS module is used for configuring all parameters required by the whole system and determining the current frame structure of the PL module in real time according to related indexes fed back by the PL module, and the PL module is used for realizing the function of a physical layer under the current frame structure according to the configuration of the PS;

wherein, the sending channel is: the PS module receives information sent by a UART serial port, splices the information with local information, sends the spliced content to the PL module, sends the information to the RF transceiver after being processed by a physical layer in the PL module, sends the information to the RF antenna after being processed by the RF transceiver, and finally radiates the information to a space through the RF antenna; the receiving channel is as follows: the RF antenna receives signals coupled by the antenna, the signals are processed and then sent to the RF transceiver, the signals are processed and then sent to the PL module, the signals are analyzed by a physical layer in the PL module and then sent to the PS module, and effective information is decoded by the PS module and then displayed on the upper computer through a UART serial port.

Further, the system also comprises a DDR module, wherein the DDR module is used for storing data interacted between the development platform and the RF transceiver and data of each node of a physical layer, transmitting the data to the upper computer for storage, and allowing developers to perform MATLAB analysis and FPGA simulation so as to assist in positioning problems in the debugging process.

Further, the RF transceiver is configured to process interactive data between the PL module and the RF antenna, specifically:

receiving data sent by a PL module, performing up-conversion on the data, then performing DA conversion, and finally sending the data after DA conversion to an RF antenna after radio frequency back-end processing;

and receiving data sent by the RF antenna, performing AD conversion on the data processed by the radio frequency front end, performing down-conversion on the data, and sending the data to the PL module.

Further, the RF is specifically configured to:

receiving a signal sent by an RF transceiver, amplifying the signal, and radiating the amplified signal to a space through an antenna;

the antenna-coupled signal is amplified by a low noise amplifier and the amplified signal is transmitted to an RF transceiver.

Further, the PS module determines the current frame structure of the PL module in real time according to the relevant index fed back by the PL module, specifically: and the PS module receives the interrupt sent by the PL module, and decides the working mode of the next time slot of the PL at the interrupt time point according to the interrupt content after receiving the corresponding interrupt according to the pre-agreed interrupt list.

Further, the PL module comprises a Register module, a Test module, a BRAM _0 module and a BRAM _1 module; the PS module interacts with a Register module of the PL module through an AXI _ LITE bus, the PS module interacts with a Test module of the PL module through an AXI _ FULL bus, and the PS module interacts with a BRAM _0 module and a BRAM _1 module of the PL module through a BRAM controller;

the sending channel specifically comprises: the PS module firstly performs framing, namely receives data sent by a UART serial port, performs data splicing with local data according to a preset communication protocol, writes the spliced data into the Bram _0 module through the BRAM controller, starts to read the data of the BRMA _0 module at a preset time point by the PL module, analyzes the data read from the BRAM _0 module according to the time sequence requirement required by the baseband sending end inlet data and sends the data to a baseband, performs subsequent physical layer processing, sends the baseband data processed by the physical layer to the RF transceiver, and the RF transceiver sends the data meeting the interface time sequence requirement of the RF transceiver chip to the RF transceiver chip for subsequent processing;

the receiving channel specifically comprises: the method comprises the steps that an RF transceiver receives data sent by an RF antenna, the data are converted into data needed by a baseband and then sent to a PL module, the PL module receives the data sent by the RF transceiver and analyzes the data through a baseband physical layer, analyzed complete frame data are completely written into a BRAM _1 module, after the data are written, a PS module is informed in an interrupted mode to read the content of the BRAM _1 and perform a frame decoding operation, and the PS module sends the related content after frame decoding to an upper computer through a UART serial port according to requirements to be displayed and stored.

As a second aspect of the present invention, there is provided an adaptive frame structure data chain transmission method, the method comprising:

step 1, the system is powered on, and the PS module waits for the initialization of related devices on the board to be completed, wherein the related devices comprise a PL module and an RF transceiver

Step 2, the PS module configures all parameters of the system, including parameters required by all sub-modules of the physical layer of the PL module and all handshaking signals required by the cooperative work of the PS module and the PL module;

step 3, the PS module starts a switch, and the related modules of the PL module start to work;

step 4, the link layer of the PL module enters a blind search mode, and the physical layer of the PL module selects a corresponding sub-module to enter a working mode according to the configuration of the PS module to carry out physical layer synchronization;

step 5, after the physical layer of the PL module is successfully synchronized, the link layer is switched to a locking mode;

step 6, in the locking mode: the PL physical layer sends an interrupt signal to the PS module after receiving and analyzing the data, the PS module detects the interrupt signal sent by the PL module, the BRAM controller reads the data of the PL module to perform the unframing operation, simultaneously reads the analysis result fed back by the PL module in a parameter mode through an AXI _ LITE bus, and determines a sub-module of the next time slot PL module physical layer according to the analysis result;

step 7, in the locking mode, the PL module link layer enters an idle time slot;

step 8, in the locking mode, after the idle time slot is finished, selecting a corresponding sub-module to enter a working mode by the PL physical layer according to the configuration of the PS module;

step 9, if the idle time slot is the data transmission end or the graph transmission end after the idle time slot is ended, repeating the content of the step 6;

step 10, if the idle time slot is a data transmission or graph transmission end after the idle time slot is finished, sending an interrupt signal to the PS module after the physical layer of the PL module finishes sending data;

and 11, repeating the steps 7 to 10 in the locking mode.

Further, in step 11, if the timing sequence is abnormal in the locked mode, the PS module forcibly switches the locked mode of the PL module to the blind search mode, and starts to go back to step 4.

The invention has the following beneficial effects:

based on the idea of defining software radio, the invention changes the fixed communication bottom frame structure into a self-adaptive frame structure capable of being programmed by software, modularizes and parameterizes the physical layer and the mac layer, namely, the same hardware environment configures software according to the upper layer to generate different frame structures and communication systems, so that the upgrading and updating of the communication systems are simpler, the hardware and software resources can be fully and reasonably utilized, and the enterprise cost is greatly reduced.

Drawings

Fig. 1 is a block diagram of an adaptive frame structure data chain transmission system according to an embodiment of the present invention;

FIG. 2 is a block diagram of a PS module and a PL module according to an embodiment of the present invention;

fig. 3 is a flowchart of an adaptive frame structure data chain transmission method according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

The invention aims to provide a data chain system of a self-adaptive frame structure, which is convenient and flexible, is easy to transplant, can meet the real-time communication requirements in different scenes, and specifically describes the implementation mode of the self-adaptive frame structure by taking a ZYNQ development platform as an example, but the working mode of the self-adaptive frame structure is not limited to the ZYNQ development platform;

in order to realize the above functions, the structure of the proposed technical solution is shown in fig. 1;

as shown in fig. 1, the structure diagram of the embodiment of the present patent includes five parts: the System comprises a UART serial port, a DDR, a ZYNQ development platform, an RF transceiver and an RF antenna, wherein the RF transceiver comprises an AD9361 chip and a rear-end radio frequency device, the ZYNQ development platform also comprises a PS (Processing System) module and a PL (programmable Logic) module, for a sending channel, the PS receives information sent by the serial port, the information is spliced with local information, the spliced content is sent to the PL and sent to the AD9361 after being processed by a physical layer in the PL, the AD9361 carries out radio frequency rear-end Processing after being processed, and the processed signal is radiated to a space through the RF antenna; for a receiving channel, the RF antenna receives signals coupled by the antenna, the signals are processed by the radio frequency front end and then sent to the AD9361, the signals are processed by the AD9361 and then sent to the PL, the signals are analyzed by the physical layer in the PL and then sent to the PS, and the PS solves effective information and then displays the effective information on the upper computer through a serial port.

The UART serial port has the function of ensuring the communication between the PS and the upper computer, and the PS receives or sends effective information.

The DDR module is mainly used for storing data interacted between the ZYNQ development platform and the AD9361 chip and data of each node of a physical layer, and is used for MATLAB analysis, FPGA simulation and auxiliary positioning and debugging of problems.

The ZYNQ development platform comprises two parts: the system comprises a PS module and a PL module, wherein the PS module comprises two cortex xA9 ARM, the PL is an FPGA, the PS configures all parameters required by the whole system, and determines the current frame structure design of the PL in real time according to the related indexes fed back by the PL; the PL implements the physical layer functions under the current frame structure according to the configuration of the PS.

The AD9361 function distinguishes sending and receiving channels, the sending channel is used for receiving data sent by a ZYNQ development platform, performing DA conversion after up-conversion, and sending the data to a radio frequency rear end for processing; the receiving means that data processed by the radio frequency front end is received, AD conversion is carried out firstly, then down-conversion is carried out, and then the data are sent to the ZYNQ development platform.

The function of the RF antenna is to distinguish the sending channel and the receiving channel, the sending channel is mainly used for receiving the signal sent by the radio frequency rear end, amplifying the signal and radiating the signal to the space through the antenna; the receiving channel mainly amplifies the signals coupled by the antenna through a low noise amplifier and sends the amplified signals to the AD 9361.

Corresponding to the structure diagram of the embodiment of the technical solution in fig. 1, the structure of the embodiment of the technical solution of the ZYNQ development platform is shown in fig. 2.

As shown in fig. 2, the ZYNQ scheme contains two major parts: the PS module is mainly responsible for scheduling the whole system and determining the current frame structure; the parameter configuration of the whole system is responsible; framing and unframing in charge of the system; and (4) taking charge of excitation test of the whole system. The PL module mainly implements the physical layer functions under the current frame structure according to the configuration of the PS module.

The PS module and the PL module Register module are interacted through an AXI _ LITE bus to realize parameter configuration; each parameter corresponds to an address, a register list agreed by both parties is formed, and the parameter interaction between the PS module and the PL module in the later period is carried out according to the register list; the PL module Register module updates the parameters in real time according to the configuration of the PS and sends the parameters to the corresponding module, and similarly, the PL module Register module also receives the result fed back by the corresponding module and feeds back the result to the PS module in real time.

The PS module and the PL module Test module are interacted through an AXI _ FULL bus and are mainly used for problem location during debugging; effective data interacted between the baseband and the AD9361 can be stored in a DDR connected with the PS module, and after the PS module detects that handshaking signals of the PS module and the PL module about reading the DDR are successful, the data in the DDR can be read, and the data are displayed on an upper computer through a serial port or a network port and are saved for MATLAB data analysis and FPGA code simulation.

And the PS module receives the interrupt sent by the PL module, and executes a corresponding task after receiving the corresponding interrupt according to the appointed interrupt list. For example, when the PS module receives the end flag of the map-based transmission start sent by the PL module, it decides whether the next timeslot is to perform data transmission or data transmission; for example, when the PS module receives the end flag of the data transfer baseband deframing sent by the PL module, the PS module reads the content of the relevant register to obtain the relevant information of the current data transfer end, and further determines whether the next time slot is to perform the transmission or reception of the graph. The PS module decides the working mode of the next time slot of the PL module at the interruption time point after receiving the relevant interruption, and the PL module executes the relevant operation according to the configuration of the PS module, which is called as an adaptive frame structure, namely, the frame structure is not fixed, the working mode of each time slot is temporarily decided by the PS module according to the relevant index of the previous time slot, and the PL module executes the working mode.

The PS module interacts with the PL modules BRAM _0 and BRAM _1 through a BRAM controller, and mainly performs writing operation on the BRAM _0 and reading operation on the BRAM _1 through the BRAM controller. After the PS module writes the framed content into BRAM _0, the PS module informs the PL module of a read start address, a read length and read enable required when reading BRAM _0 in a parameter configuration mode, and reads the content of BRAM _0 when a transmitting end starts and outputs the content to a baseband for physical layer processing according to the time sequence requirement required by the baseband. The PL module can configure a write start address, a write length and a write enable of the write BRAM _1 according to the PS module, and after the PL module analyzes data received by the baseband, the PL module can write the analyzed complete frame data into the BRAM _1 according to parameters configured by the PS module, and after the write is finished, the PS module is informed to read the data. And the PS reads the data of the BRAM _1 and performs the unframing operation to obtain the finally required effective information.

For the sending channel, the PS module firstly performs framing, that is, receives data sent by the UART serial port, and performs data splicing with the local data according to the agreed communication protocol. And the spliced data PS module is written into the Bram _0 through the BRAM controller, starts to read the data of the BRMA _0 at a certain appointed time point PL, analyzes the data read in the BRAM _0 according to the time sequence requirement required by the entry data of the baseband originating end, and sends the data to the baseband for subsequent physical layer processing. The baseband data processed by the physical layer is sent to the PL module AD9361 module, and the AD9361 module finally sends the data meeting the interface time sequence requirement of the AD9361 chip to the AD9361 chip for subsequent processing.

For a receiving channel, the PL module firstly receives data sent by the AD9361 chip, the data are converted into data required by a baseband after passing through the AD9361 chip of the PL module, then the data are analyzed by a baseband physical layer, the PL module completely writes analyzed complete frame data into BRAM _1, and after the data are completely written, the PL module informs the PS module in an interrupted mode to read the content of the BRAM _1 and perform a deframing operation, and the related content after deframing can be sent to an upper computer through a UART serial port according to requirements to be displayed and stored.

Corresponding to the implementation structure diagram of the technical solution in fig. 1, taking an antenna as an example, a flow chart of the implementation of the adaptive frame structure is shown in fig. 3.

As shown in the flowchart of fig. 3, after the system is powered on, the PS module waits for the initialization of the relevant devices on the board; after the initialization is completed, the PS module starts to configure all parameters needed by the system; after parameter configuration is completed, the PS module starts a switch, and the related modules of the PL module start to work normally; the PL module link layer enters a blind search mode, and the PL module physical layer selects a corresponding sub-module to enter a working mode according to the configuration of the PS module; after the physical layer is successfully synchronized, indicating that blind searching is successful, and switching the link layer of the PL module to a locking mode; in the locking mode, after the physical layer sub-module of the PL module receives data, the PL module sends a data receiving completion interrupt signal to the PS module, and meanwhile, a link layer of the PL module enters an idle time slot; the physical layer of the PL module continues to analyze the received data, and after the data analysis is finished, the PL module sends a data analysis finished interrupt signal to the PS module; after the link layer waits for the idle time slot to end, indicating a physical layer of a PL (packet data) module to select a corresponding sub-module to enter a working mode according to the latest configuration of the PS module; if the data transmission or graph transmission end is arranged after the idle time slot is finished, the physical layer of the PL module sends a data receiving finishing interrupt signal to the PS module after the data is completely received, and meanwhile, the link layer of the PL module enters the idle time slot; the physical layer of the PL module continues to analyze the received data, and after the data analysis is finished, the PL module sends a data analysis finished interrupt signal to the PS module; if the data transmission or graph transmission end is the transmission end after the idle time slot is finished, the physical layer of the PL module sends a data transmission finishing interrupt signal to the PS module after the transmission end data is finished, and then the link layer enters the idle time slot; if the time slot is idle, the PS module forces the link layer to be switched from the locking mode to the blind searching mode, and the link layer starts to go through the previous synchronous flow again, and so on.

Fig. 3 is a flow chart of an adaptive frame structure at an antenna end, and details of the steps are as follows:

1) and powering on the system.

2) And the PS module waits for the initialization of the related devices on the board to be completed, wherein the related devices refer to PL and AD9361 chips, and after the initialization of the devices is completed, the devices can inform the PS module in a mode of reading and writing a register, and the PS module is always in a polling state, and once the state of the register is inquired to be changed, the initialization of the related devices on the board is completed, and the next process can be entered.

3) The PS module configures all parameters of the system, where the parameters include parameters required by all sub-modules of the physical layer of the PL module, and all handshake signals required by cooperative work of the PS and the PL, such as an initial address and a length when the BRAM is read and written in fig. 2; PL writes the initial address, length, etc. of the DDR.

4) The PS module turns on the switch and the PL module related module starts to work. After the initialization of the PL module is completed, the PL module is in an idle state, and after the PS module is configured with all parameters, the PL module is informed of the normal work in a register reading and writing mode.

5) And the PL module link layer enters a blind search mode, and the PL module physical layer selects a corresponding sub-module to enter a working mode according to the configuration of the PS module. The PL module enters a blind search mode from initialization completion to work, and the link layer firstly aims to perform physical layer synchronization with equipment at the other end. The PS module determines whether the PL module link layer enters a blind search mode according to whether the other end sends data transmission or image transmission, and then the physical layer selects the data transmission end or the image transmission end to start working.

6) And the physical layer is successfully synchronized, and the link layer is switched to a locking mode. The link layer is switched from the blind searching mode to the locking mode, and is related to whether the physical layer is successfully synchronized or not, and is further related to the success of continuous several frames of synchronization of the physical layer. Wherein, the successful synchronization of several continuous frames of the physical layer is a parameter configuration controlled by the PS. The PS can be configured as 1 according to the actual situation, that is, as long as 1 frame synchronization is successful in the physical layer, the link layer is switched from the blind search mode to the lock mode; the PS can also be configured to be 4 according to practical situations, that is, the physical layer needs to succeed in continuous 4-frame synchronization, and the link layer can switch from the blind search mode to the lock mode.

7) In the locking mode, the physical layer sends an interrupt signal to the PS module after receiving the data. The time length of data received by the physical layer of the PL module is configured by taking the PS module as a parameter, once the PL module link layer detects that the time length of data received by the physical layer is equal to a parameter value configured by the PS module, the PL module sends an interruption signal of data receiving completion to the PS module, and the PS module detects the interruption signal sent by the PL module, and writes framed data into the PL module BRAM through the BRAM controller.

In the locking mode, the physical layer sends an interrupt signal to the PS module after the data is analyzed. And the PL module physical layer finishes analyzing the data at the time point after receiving the data. Once the physical layer of the PL module analyzes data, an interruption signal of data analysis completion is sent to the PS module, the PS module detects the interruption signal sent by the PL module, the data of the PL module BRAM is read through the BRAM controller to perform frame decoding operation, meanwhile, the PS module reads an analysis result fed back by the PL module in a parameter mode through an AXI _ LITE bus, and determines which sub-module of the physical layer of the next time slot works according to the analysis result.

8) In the locked mode, the link layer enters an idle slot. After the physical layer of the PL module receives the data, the PL module enters an idle time slot, and the time length of the idle time slot is configured by the PS module as a parameter.

9) In the locking mode, after the idle time slot is finished, the physical layer selects the corresponding sub-module to enter the working mode according to the configuration of the PS module. The PS module can determine which sub-module works in the next time slot of the physical layer before the idle time slot is finished, and distinguish the transmitting end from the receiving end.

10) And if the data transmission end or the graph transmission end is after the idle time slot is finished, repeating the content of the step 7).

11) If the data transmission or graph transmission end is after the idle time slot is over, an interrupt signal is sent to the PS module after the physical layer of the PL module finishes sending data. The time length of the transmitting end is configured by the PS module, and the physical layer enters the idle time slot after transmitting data.

12) In the lock mode, repeating step 8) to step 11). If the time sequence is abnormal in the locking mode, the PS module will force the locking mode of the PL module to be switched to the blind search mode, and the content of the step 5) is started to be re-executed.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. An adaptive frame structure data chain transmission system, the system comprising: the UART device comprises a UART serial port, an embedded development platform, an RF transceiver and an RF antenna, wherein the embedded development platform comprises a PS module and a PL module, and the UART serial port, the PS module, the PL module, the RF transceiver and the RF antenna form a data transceiving channel;

wherein, the sending channel is: the PS module receives information sent by a UART serial port, splices the information with local information, sends the spliced content to the PL module, sends the information to the RF transceiver after being processed by a physical layer in the PL module, sends the information to the RF antenna after being processed by the RF transceiver, and finally radiates the information to a space through the RF antenna; the receiving channel is as follows: the RF antenna receives signals coupled by the antenna, the signals are processed and then sent to the RF transceiver, the signals are processed and then sent to the PL module, the signals are analyzed by a physical layer in the PL module and then sent to the PS module, and the effective information is decoded by the PS module and then displayed on the upper computer through a UART serial port.

2. The adaptive frame structured data link transmission system according to claim 1, further comprising a DDR module, wherein the DDR module is configured to store data exchanged between the development platform and the RF transceiver and data of each node in a physical layer, and to transmit and store the data to the upper computer, so that developers can perform MATLAB analysis and FPGA simulation to assist in locating problems occurring during debugging.

3. The adaptive frame structure data chain transmission system according to claim 1, wherein the RF transceiver is configured to process interactive data between the PL module and the RF antenna, specifically:

4. The adaptive frame structure data chain transmission system according to claim 1, wherein the RF antenna is specifically configured to:

5. The adaptive frame structure data chain transmission system according to claim 1, wherein the PS module determines the current frame structure of the PL module in real time according to the relevant index fed back by the PL module, specifically: and the PS module receives the interrupt sent by the PL module, and after receiving the corresponding interrupt according to the pre-agreed interrupt list, the PS module decides the working mode of the next time slot of the PL at the interrupt time point according to the interrupt content.

6. The adaptive frame structure data chain transmission system of claim 1, wherein the PL module comprises a Register module, a Test module, a BRAM _0 module, and a BRAM _1 module; the PS module interacts with a Register module of the PL module through an AXI _ LITE bus, the PS module interacts with a Test module of the PL module through an AXI _ FULL bus, and the PS module interacts with a BRAM _0 module and a BRAM _1 module of the PL module through a BRAM controller;

7. A method for adaptive frame structure data link transmission, the method comprising:

step 1, a system is powered on, and a PS module waits for the initialization of related devices on a board to be completed, wherein the related devices comprise a PL module and an RF transceiver;

step 7, in the locking mode, the PL module link layer enters an idle time slot;

and 11, repeating the steps 7 to 10 in the locking mode.

8. The adaptive frame structure data chain transmission method according to claim 7, wherein in step 11, if the timing sequence is abnormal in the locked mode, the PS module forcibly switches the locked mode of the PL module to the blind search mode, and starts to go back to step 4.