CN114664834B - Groove type ferroelectric memory cell structure and preparation method thereof - Google Patents

Abstract

The present invention relates to the field of information storage technology, and proposes a trench-type ferroelectric memory cell structure and a preparation method. The present invention includes using fin field effect transistors FinFET to replace traditional planar transistors in the preparation process. Compared with traditional planar transistors, FinFET transistors have absolute advantages in suppressing short channel effects and reducing leakage. The present invention also includes folding and integrating ferroelectric capacitors on the surface and sidewalls of the trench opened in the drain region. Compared with the traditional structure, the ferroelectric memory cell structure proposed in the present invention can further reduce the size of the memory cell. Under the same process node, only changes need to be made in the structure of the memory device to achieve a significant increase in data information capacity. The structure is simple and can be widely used in high-density ferroelectric memory chips.

Description

A trench type ferroelectric memory cell structure and preparation method

Technical Field

The present invention relates to the field of information storage, and in particular to a ferroelectric storage unit structure and a preparation method thereof.

Background technique

Ferroelectric memory is a new type of non-volatile memory. Compared with traditional memory, ferroelectric memory has the following advantages: fast access time, low operating voltage, low reading and writing power consumption, and long service life. And as a RAM-type memory, the data of ferroelectric memory still exists after power failure and will not be lost. In addition, the strong radiation resistance of ferroelectric memory gives it a unique advantage in aerospace applications.

In some dielectric crystals, the special structure of the unit cell causes the centers of positive and negative charges to not coincide, resulting in an electric dipole moment and an electric polarization intensity that is not equal to zero. This gives the crystal spontaneous polarization, and the direction of the electric dipole moment can be changed by the action of an external electric field, exhibiting characteristics similar to those of ferromagnets. Since the relationship curve between the degree of polarization and the intensity of the electric field is similar in shape to the hysteresis loop of a ferromagnet, people call this property "ferroelectricity", the relationship curve between the degree of polarization and the intensity of the electric field is called "hysteresis loop", and materials with ferroelectricity are called "ferroelectric materials".

Figure 1 shows the measured hysteresis loop of ferroelectric material. Taking the positive half axis of Figure 1 as an example, Vmax is the maximum value of the applied voltage. Pmax is the maximum polarization intensity of the ferroelectric material when the applied voltage is Vmax. Pr is the forward spontaneous polarization intensity of the ferroelectric material when the applied voltage is 0, also known as the residual polarization intensity. Vc is the applied forward voltage value required to increase the spontaneous polarization intensity of the ferroelectric material from -Pr to 0, also known as the coercive voltage. Ferroelectric memory utilizes the nonlinear response between the polarization intensity and the applied voltage and the residual polarization characteristics of the ferroelectric material to realize the storage of "1" and "0" digital information.

Figure 2 shows a schematic diagram of the basic memory cell circuit of a ferroelectric memory. Its structure is a "2T2C" type, that is, each memory cell includes two transistors and two ferroelectric capacitors. In Figure 2, the word line WL is connected to the transistor gate G, the two complementary bit lines BL and BLN are connected to the transistor source S, the upper plate of the ferroelectric capacitor is connected to the transistor drain D, and the plate line PL is connected to the lower plate of the ferroelectric capacitor. Under working conditions, the polarization directions of the two ferroelectric capacitors are always opposite. When performing a read operation, it is precisely because the polarization directions of the two capacitors are different that the charge amount on the bit line capacitors at the BL and BLN ends changes differently, and the judgment of the data "0" and "1" is realized through the sensitive amplifier. Therefore, in order to ensure the accuracy of the data, the maximum charge amount that the ferroelectric capacitor can store cannot be too low, which makes a requirement for the minimum area of the planar ferroelectric capacitor, which greatly limits the further improvement of the integration of the ferroelectric memory.

Figure 3 shows a schematic diagram of a tiled structure in the manufacture of a "2T2C" memory cell. In this structure, the transistor and the ferroelectric capacitor are located in the same metal layer, and the transistor drain and the ferroelectric capacitor plate are electrically connected through a metal wire. In order to ensure the charge storage capacity of the ferroelectric capacitor, the area consumed by a single memory cell is relatively large, so this structure is not suitable for the preparation of large-capacity ferroelectric memory.

FIG4 is a schematic diagram of a stacked structure in the manufacture of a "2T2C" memory cell. In this structure, the transistor and the ferroelectric capacitor are located in different metal layers, and the transistor drain and the ferroelectric capacitor are electrically connected through interlayer vias and metal wires. Compared with the structure shown in FIG3, this structure reduces the area of a single memory cell to a certain extent, but is still limited by the minimum area requirement of the planar capacitor.

Summary of the invention

The present invention specifically relates to a trench type ferroelectric memory cell structure and a preparation method thereof. By using the ferroelectric memory cell structure and a preparation method disclosed by the present invention, the size of the ferroelectric memory cell can be reduced, the storage density of the ferroelectric memory can be further improved, and the production cost can be reduced.

Technical solutions

A trench-type ferroelectric memory cell structure comprises: a substrate; a transistor source, a drain region and a source-drain fin structure connecting the source and drain formed by etching on the substrate; a drain trench structure formed by etching in the transistor drain region; a substrate insulating layer deposited on the substrate surface; a gate metal oxide layer deposited in the middle of the source-drain fin structure; a gate electrode surrounding the gate metal oxide layer deposited; and a ferroelectric capacitor structure formed by sequentially depositing a bottom electrode layer, a ferroelectric film layer and a top electrode layer on the surface, sidewall and bottom of the drain trench structure.

Furthermore, the substrate is a semiconductor substrate, generally one of materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

Furthermore, the source, drain, and fin-shaped structure between the source and drain are formed by etching the semiconductor substrate and are in a barbell-shaped structure. The cross-sectional shape of the fin-shaped structure between the source and drain is a rectangular, trapezoidal, or inverted triangle structure.

Furthermore, the drain trench structure is formed by etching in the drain region of the transistor, and the number of trenches can be freely selected according to actual needs, and the trench width must be greater than or equal to twice the thickness of the ferroelectric capacitor to ensure the generation of the ferroelectric capacitor. Further, when etching to generate the drain trench structure, the remaining area on the drain except the trench portion should maintain physical connection. Further, the cross-sectional shape of each trench structure can be rectangular, trapezoidal, "U"-shaped or "V"-shaped.

Furthermore, the substrate insulating layer is an insulating thin film layer structure deposited on the surface of the semiconductor substrate.

Furthermore, the gate oxide layer is a uniform oxide film formed on three outer surfaces of the middle of the fin structure between the source and drain by thermal oxidation or deposition. The gate oxide layer is generally made of oxides with high dielectric constants such as silicon dioxide ( _SiO2 ), hafnium dioxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), etc.

Furthermore, the gate electrode is an electrode surrounding the gate oxide layer generated by deposition. The gate electrode is orthogonal to the fin structure between the source and drain. The gate electrode width should be slightly less than or equal to the gate oxide layer width. The gate electrode is generally made of a metal gate electrode or n-type doped polysilicon (Si).

Further, the ferroelectric capacitor is a multilayer structure formed by sequentially depositing a bottom electrode layer, a ferroelectric thin film layer, and a top electrode layer on the drain trench structure. Further, the bottom electrode layer and the top electrode layer are made of TiN, TaN or HfN _X (0<X≤1.1). Further, the ferroelectric thin film layer is generally made of hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), zirconium oxide (ZrO ₂ ) doped with other elements, or hafnium oxide (HfO ₂ ) doped with other elements; the other doping elements include one or more of silicon (Si), aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), and nitrogen (N).

Furthermore, the ferroelectric capacitor needs to be rapidly thermally annealed after formation to obtain a better ferroelectric film interface state, the annealing temperature is between 400°C and 600°C, and the annealing time is between 40s and 400s; preferably, the annealing temperature is 500°C and the annealing time is 60s.

The above technical solution of the present invention has the following beneficial technical effects:

The present invention uses FinFET to replace the planar transistor in the traditional process, which can effectively solve the leakage loss problem caused by the short channel effect when the feature size of the planar transistor is reduced, thereby adapting to it.

At the same time, the present invention provides a method for preparing a three-dimensional groove type ferroelectric capacitor, which converts the ferroelectric capacitor from a flat plate structure to a three-dimensional structure to increase the capacitance area, and further reduce the size of the storage unit without reducing the charge storage capacity of the ferroelectric capacitor. This groove structure makes the integration density of the ferroelectric random access memory higher and the manufacturing cost lower, solves the difficulties encountered by the flat plate structure ferroelectric memory, and provides important research significance and wide application value for further developing a ferroelectric random access memory with low manufacturing cost, high storage density, and high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a hysteresis loop of a ferroelectric material;

FIG2 is a circuit diagram of a “2T2C” type ferroelectric memory cell;

FIG3 is a schematic diagram of a tiled structure in the manufacture of a “2T2C” type ferroelectric memory cell;

FIG4 is a schematic diagram of a stacked structure in the manufacture of a “2T2C” type ferroelectric memory cell;

5 to 7 are schematic diagrams of etching a transistor source, a drain, a fin structure between the source and the drain, and a drain trench structure on a substrate, respectively, according to Embodiment 1, Embodiment 2, and Embodiment 3 of the present invention;

8 is a schematic diagram of depositing a substrate insulating layer on a substrate provided in Embodiment 1 of the present invention;

9 is a schematic diagram of depositing a gate oxide layer in the middle of a fin-shaped structure between a source and a drain according to Embodiment 1 of the present invention;

FIG10 is a schematic diagram of a transistor gate formed by deposition according to Embodiment 1 of the present invention;

11-13 are schematic diagrams of sequentially depositing a bottom electrode layer, a ferroelectric thin film layer, and a top electrode layer of a ferroelectric capacitor according to Embodiment 1, Embodiment 2, and Embodiment 3 of the present invention, respectively;

FIG14 is a cross-sectional schematic diagram of a ferroelectric memory cell provided in Embodiment 1 of the present invention.

Figure numerals: 1-semiconductor substrate; 2-substrate insulating layer; 3-transistor source; 4-transistor drain; 5-fin structure between source and drain; 6-gate oxide layer; 7-transistor gate; 8-drain fin structure; 9-capacitor bottom electrode layer; 10-ferroelectric thin film layer; 11-capacitor top electrode layer.

Detailed ways

In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, the description of common structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention.

The method for preparing a trench ferroelectric memory cell provided by the present invention comprises the following steps:

As shown in Figure 5, the source region, drain region, and fin structure between the source and drain of the transistor are completed by etching on the semiconductor substrate, and the preparation of the drain trench structure is completed at the same time. Specifically, the remaining parts of the drain except the groove should maintain a physical connection. Optionally, the cross-section of the groove is rectangular, trapezoidal "U" shape or "V" shape. Furthermore, the source and drain need to be formed separately in the corresponding areas by ion implantation.

FIG6 is a schematic diagram of a drain trench structure formed in Example 2, which is different from Example 1 in that the drain trench structure is completely wrapped by the drain region.

FIG7 is a schematic diagram of a drain trench structure formed in Example 3, which is different from Example 1 in that the bottom of the drain trench structure is higher than the substrate surface, and the trench length runs through the entire drain region.

FIG. 8 is a schematic diagram showing the deposition of a substrate insulating layer in the non-source, drain and drain trench regions on the substrate according to Example 1.

As shown in Figure 9, a uniform gate oxide layer is deposited in the middle of the fin structure between the source and drain to cover three outer surfaces in Example 1. Optionally, the gate oxide layer is an oxide with a high K value such as silicon dioxide ( _SiO2 ), hafnium dioxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), etc.

FIG. 10 is a schematic diagram of depositing a transistor gate in Example 1.

As shown in Figure 11, in Example 1, a bottom electrode layer, a ferroelectric thin film layer, and a top electrode layer are deposited above the surface, on the sidewalls, and at the bottom of the drain trench region to form a ferroelectric capacitor structure. Preferably, the thickness of the ferroelectric thin film layer should be in the range of 10-30nm. Optionally, after all the thin film layers are deposited, in order to optimize the interface state of the ferroelectric thin film, rapid thermal annealing (RTA) can be performed, and the annealing temperature ranges from 400°C to 600°C, and the annealing time is 40s-100s. Preferably, the annealing temperature is 550°C, and the annealing time is 60s.

FIG. 12 is a schematic diagram of the overall structure of Embodiment 2 of the present invention.

FIG. 13 is a schematic diagram of the overall structure of Example 3 of the present invention.

The accompanying drawings show schematic diagrams of layer structures according to embodiments of the present invention. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clarity. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions/layers with different shapes, sizes, and relative positions according to actual needs.

Some steps in the above process involve some process flows such as etching and deposition steps which are not clearly described, but these technologies are mature technologies in this field. Professionals and technicians in this field may know how to implement the above steps through existing microelectronics manufacturing technology.

It should be noted that the above specific embodiments of the present invention are only used to illustrate or explain the principles of the present invention, and do not constitute a limitation of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made within the scope of the inventive concept of the present invention should be included in the protection scope of the claims attached to the present invention.

Claims (2)

1. A trench ferroelectric memory cell structure and a method of fabricating the same are characterized in that the ferroelectric memory cell structure comprises a semiconductor substrate; a transistor source electrode, a drain electrode region and a fin-shaped structure between source and drain electrodes, which are formed on the semiconductor substrate by etching; a drain trench structure etched in the transistor drain region; depositing a generated substrate insulating layer on the surface of the substrate; a grid oxide layer formed in the middle of the fin-shaped structure between the source and the drain; depositing a generated gate electrode surrounding the gate oxide layer; a ferroelectric capacitor structure formed by sequentially depositing a bottom electrode layer, a ferroelectric film layer and a top electrode layer on the surface, the side wall and the bottom of the drain electrode groove structure, wherein the bottom electrode layer completely covers the drain electrode of the transistor; the drain trench, the trench bottom may be flush with the substrate or above the substrate surface; in order to be compatible with the mature transistor manufacturing flow, forming a drain groove structure while forming a source electrode, a drain electrode and a fin-shaped structure between the source electrode and the drain electrode, so that the bottom of the groove is flush with the surface of the substrate, and the groove spacing is at least equal to or greater than twice the thickness of the ferroelectric capacitor; in order to obtain a better ferroelectric film interface state, a bottom electrode layer, a ferroelectric film layer and a top electrode layer are deposited in sequence to form a ferroelectric capacitor structure, and then rapid thermal annealing is carried out, wherein the annealing temperature is 400-600 ℃, and the annealing time is 40-400 s;

the ferroelectric memory cell is of a 2T2C structure, and each memory cell comprises two transistors and two ferroelectric capacitors;

The material of the grid electrode oxide layer is oxide with high dielectric constant, and the oxide is silicon dioxide, hafnium dioxide or zirconium dioxide;

the gate electrode is an electrode which is formed by deposition and surrounds the gate oxide layer, and the gate electrode and the fin-shaped structure between the source electrode and the drain electrode are in an orthogonal relationship;

The bottom electrode layer and the top electrode layer are made of TiN, taN, or HfN _X;

The ferroelectric film layer is made of hafnium oxide, zirconium oxide doped with other elements or hafnium oxide doped with other elements; the other elements comprise one or more of silicon, aluminum (Al), zirconium (Zr), lanthanum (La), cerium (Ce), strontium (Sr), lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge) and nitrogen (N);

Wherein the drain trench is a plurality of continuous trenches;

wherein the transistor is a FinFET.

2. The trench ferroelectric memory cell structure of claim 1 wherein the transistor drain is grooved and the ferroelectric capacitor is integrated into the trench to convert from a conventional planar structure to a folded structure to achieve a larger surface area capacitance over a smaller area;

The drain trench is characterized in that the cross section of the trench can be rectangular, trapezoidal, U-shaped or V-shaped.