CN114661127A - Reset circuit, reset method and chip - Google Patents
Reset circuit, reset method and chip Download PDFInfo
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- CN114661127A CN114661127A CN202210566846.6A CN202210566846A CN114661127A CN 114661127 A CN114661127 A CN 114661127A CN 202210566846 A CN202210566846 A CN 202210566846A CN 114661127 A CN114661127 A CN 114661127A
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Abstract
The invention discloses a reset circuit, a reset method and a chip.A first receiving end of a first reset control module is configured to receive a reset request signal of a main equipment module in the chip through the first reset control module integrated in the chip, an output end of the first reset control module is configured to output a reset control signal of the main equipment module or a slave equipment module in the chip, when the main equipment module or the slave equipment module needs to be reset, the internal reset command decoding is carried out after the reset request signal is received, the reset request initiated by each main equipment can be analyzed, the reset control signal is correspondingly output to the main equipment module or the slave equipment module needing to be reset, and the reliability of the normal reset operation of each module equipment in the chip is improved.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a reset circuit, a reset method, and a chip.
Background
In a complex integrated circuit, a plurality of sub-modules with different functions are often designed on an on-chip bus to be used as a master device of the whole system. For example, in a GPU (Graphics Processing Unit) system, a PCIe (Peripheral Component Interconnect Express) Controller for main data transmission, an MCU (Micro Controller Unit) for internal control and monitoring, a debug interface (e.g., UART Controller) for online debugging, and the like are generally integrated. The master equipment module and the slave equipment module are communicated with each other in the system through an on-chip bus. The reset control is an indispensable subunit of various equipment modules, and the reset control signal generally comprises the following two types, 1, reset activation, the reset control signal of the module is in an effective state, and the module does not work or enters a low power consumption state according to the following convention in the industry; 2. and resetting is released, the reset control signal of the module is in an invalid state, and the module works normally.
At present, the reset control of the chip is realized by controlling a special reset control module, and the reset control module is usually hung on an on-chip bus in the chip, so that the on-chip reset control has limitation.
Therefore, how to improve the reliability of the normal reset operation of each module device in the chip is a technical problem to be solved urgently at present.
Disclosure of Invention
The reset circuit, the reset method and the chip improve the reliability of the normal reset operation of each module device in the chip.
The embodiment of the invention provides the following scheme:
in a first aspect, an embodiment of the present invention provides a reset circuit, including a first reset control module integrated inside a chip;
a first receiving end of the first reset control module is configured to receive reset request signals of one or more master device modules inside the chip;
the output end of the first reset control module is configured to output a reset control signal of a master device module or a slave device module inside the chip;
and the first reset control module outputs the reset control signal after receiving the reset request signal, and controls the reset operation of the master equipment module or the slave equipment module after being powered on.
In an optional embodiment, the second receiving end of the first reset control module is configured to receive a power-on reset initial value signal external to the chip;
the first reset control module outputs the reset control signal after receiving the power-on reset initial value signal, and controls the reset initial value when the main equipment module is started.
In an alternative embodiment, the first reset control module comprises at least one hardware state machine;
and the hardware state machine outputs the reset control signal after receiving the reset request signal and the power-on reset initial value signal, and correspondingly configures the reset triggering condition of the master equipment module or the slave equipment module.
In an optional embodiment, the system further comprises a second reset control module;
a receiving end of the second reset control module configured to input the reset request signal;
the output end of the second reset control module is configured to output the reset control signal to an on-chip bus inside the chip;
and the second reset control module outputs the reset control signal after receiving the reset request signal and controls the reset operation of the slave equipment module through the on-chip bus.
In a second aspect, an embodiment of the present invention further provides a reset method, applied to the reset circuit in the first aspect, including:
receiving a reset request signal of a current master equipment module;
and outputting a reset control signal according to the current module number of the current main equipment module and the reset module number of the reset request signal so as to reset the main equipment module or the slave equipment module in the chip.
In an optional embodiment, the outputting a reset control signal according to the current module number of the current master device module and the reset module number of the reset request signal includes:
if the current module number is the same as the reset module number, outputting the reset control signal which is a monostable reset signal to reset the current main equipment module;
if the current module number is different from the reset module number, the reset control signal which is a bistable reset signal is output to reset other main equipment modules.
In an optional embodiment, after receiving the reset request signal of the current master device module, the method further includes:
and when the reset module number of the reset request signal is a preset set module number, outputting the reset control signal which is a monostable reset signal to reset the slave equipment module.
In an optional embodiment, further comprising:
receiving a power-on reset initial value signal outside a chip;
determining corresponding initial reset operation according to the reset control signal and the reset initial value of the power-on reset initial value signal;
and configuring a trigger condition of reset release according to the initial reset operation and the input reset mode.
In an optional embodiment, the configuring the trigger condition of the reset release according to the initial reset operation and the input reset mode includes:
if the initial reset operation is reset release or reset activation and the reset mode is bistable release reset, outputting the reset control signal to carry out reset activation, and configuring the trigger condition of the release reset as the bistable release reset;
and if the initial reset operation is reset release or reset activation and the reset mode is monostable release reset, outputting the reset control signal to carry out reset activation, and configuring the trigger condition of the release reset as reaching preset duration.
In a third aspect, an embodiment of the present invention further provides a chip, where the chip includes the reset circuit described in any one of the first aspects.
Compared with the prior art, the reset circuit, the reset method and the chip provided by the invention have the following advantages:
according to the invention, through the first reset control module integrated in the chip, the first receiving end of the first reset control module is configured to receive the reset request signal of the main equipment module in the chip, the output end of the first reset control module is configured to output the reset control signal of the main equipment module or the slave equipment module in the chip, when the main equipment module or the slave equipment module needs to be reset, after the reset request signal is received, the internal reset command decoding is carried out, the reset request initiated by each main equipment can be analyzed, the reset control signal is correspondingly output to the main equipment module or the slave equipment module needing to be reset, the bus in the chip is not depended on in the reset process, and the reliability of the normal reset operation of each module equipment in the chip is further improved; meanwhile, the reset implementation mode is more flexible, the main equipment module can complete self reset according to the application requirement, reset other main equipment modules and reset the functions of the slave equipment modules, the limitation of reset control in the prior art is eliminated, and various application requirements of complex multi-main equipment modules on a system on a chip for reset can be met.
Drawings
In order to more clearly illustrate the embodiments of the present specification or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a reset circuit in the prior art according to an embodiment of the present invention;
FIG. 2 is a flow chart of bistable reset provided by an embodiment of the present invention;
FIG. 3 is a flow chart of a monostable reset provided by an embodiment of the invention;
fig. 4 is a schematic structural diagram of a reset circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a first reset control module according to an embodiment of the present invention;
fig. 6 is a flowchart of a reset method according to an embodiment of the present invention;
fig. 7 is a decoding flowchart of a first reset control module according to an embodiment of the present invention;
FIG. 8 is a flow chart of a process for a hardware state machine according to an embodiment of the present invention;
fig. 9 is a transition diagram of a hardware state machine according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention belong to the scope of protection of the embodiments of the present invention.
The reset circuit and the reset method of the present invention can be applied to any chip that needs to reset the master device module and the slave device module, this embodiment will be further described by taking GPU as an example, the reset control of such chips is generally implemented by a special reset control module, please refer to fig. 1, and the specific reset modes mainly include the following:
(1) the software directly controls, activates or releases the reset signal: one master device writes a reset control module through a bus, and other master devices or slave devices carry out reset activation and release operations in a 0 setting or 1 setting mode. Typically, a 1 write activates a reset to a specified register bit and a 0 rewrite releases the reset. Referring to fig. 2, until the next software reset operation, the reset state is stable, and the reset circuit is in the form of a bistable circuit.
(2) Software control activates reset, hardware automatic release resets: the method is realized by a master device through a bus write reset control module and a monostable reset circuit, the 1-write reset is usually activated to the designated register bit, and the hardware automatically releases the reset after a certain time interval. Referring to fig. 3, the reset circuit is in the form of a monostable circuit.
In the system on chip with multiple main device modules like fig. 1, the scenario that a device needs to be reset is mainly as follows: a. the application needs to activate reset and release again; b. when abnormal conditions occur, the reset is required to be activated and released again; c. it is necessary to turn off or turn on a functional module to make the reset activation or reset state in a software controllable state.
Sometimes, when the master device needs to reset its own module or reset a module affecting global functions such as an on-chip bus, it needs hardware to automatically release reset (using a monostable reset circuit), and when other master devices or slave devices are reset, it needs more flexible software control reset (using a bistable reset circuit).
For the reset scheme described above, the transition of the reset state of the module is completely software dependent, and a reset request to the other module is initiated by the master module. The limitation is that the master device initiating the reset operation cannot reset itself. The main device MCU in the GPU system is usually independent of most other functional modules to implement the monitoring function of the system, and the reset request to the MCU generally comes from the inside of the MCU program and not from other functional modules such as PCIe. When the MCU controls the reset register to place the reset signal of the MCU in a reset activation state, the reset release operation can not be executed any more, so that the normal reset can not be carried out.
In addition, for the reset scheme, the monostable circuit is adopted to enable hardware to carry out reset release operation, and the problem that the hardware cannot reset in the prior art (1) can be solved. However, the limitation of (2) is that the reset activation signal generated by the reset control logic is monostable (temporary state) in the reset operation initiated by the master device, and the normal reset operation of the module cannot be realized, and the requirements of power consumption control and other special functions are not met.
In addition, in the prior art, the reset control module is usually hung on an on-chip bus within a chip and is a slave device of a system on chip, which causes a common limitation of the prior art (1) (2): both of these reset designs pass through the bus, and if the bus is hung up for some reason, the reset of each device module and the bus cannot be completed.
The reset circuit provided by the invention combines the advantages of the two resets and simultaneously meets the different reset application requirements, and the specific explanation is provided below.
Referring to fig. 4, an embodiment of the invention provides a reset circuit, which includes a first reset control module integrated in a chip; a first receiving end of the first reset control module, configured to receive reset request signals of one or more master device modules inside the chip; the output end of the first reset control module is configured to output a reset control signal of a master device module or a slave device module in the chip; and the first reset control module outputs a reset control signal after receiving the reset request signal and controls the reset operation of the master equipment module or the slave equipment module after being electrified.
Specifically, the main device module is a module which is controlled by an on-chip bus to other device modules in a chip, such as an MCU device module and a UART device module; the slave device module is a module controlled by the master device module, such as an on-chip bus module and other functional modules. Generally, each module device in a chip can be automatically reset when being powered on, the reset mode comprises low level reset or high level reset, when a master device module or a slave device module needs to be reset after being powered on, the master device module sends a reset request signal, and after being received by a first receiving end, a first reset control module correspondingly outputs the reset request signal to the master device module or the slave device module to be reset. It should be noted that the master device module may be a master device module that sends a reset request signal, so as to perform a reset operation on the master device module itself; of course, other master device modules may also be used to control the other master device modules to perform the reset operation. The slave device module may also be reset through an on-chip bus, and it can be understood that the first reset control module transmits a reset request signal and a reset control signal through a metal line inside the chip.
In specific implementation, the reset operation of each equipment module is controlled by the main equipment module and is performed autonomously in the chip, so that the flexibility of control is limited.
In a specific embodiment, the second receiving end of the first reset control module is configured to input a power-on reset initial value signal outside the chip; and the first reset control module outputs a reset control signal after receiving the power-on reset initial value signal and controls the reset initial value when the main equipment module is started.
Specifically, the power-on reset initial value signal can be operated by an off-chip device, so that a plurality of signals related to the power-on starting state can be conveniently introduced from off-chip pins, and the power-on reset initial value signal is used for controlling the reset initial value of each main device module during starting so as to control or modify the reset operation of the main device module. The reset initial value is erased and written in a binary mode through a power-on reset initial value signal in a register in the chip, and the reset initial value in the register can be modified.
In a particular embodiment, the first reset control module includes at least one hardware state machine;
and the hardware state machine outputs a reset control signal after receiving the reset request signal and the power-on reset initial value signal, and correspondingly configures the reset triggering condition of the master equipment module or the slave equipment module.
Specifically, a hardware state machine (or reset state machine) is configured by a state register and a combinational logic circuit, and can perform state transition in accordance with an input signal by a preset state. The reset request signal sent by the main device module has corresponding identification characteristics, such as a preset number of the main device module, which main device module sends out the reset request signal can be identified through decoding operation, the reset request signal and the power-on reset initial value signal are output to a hardware state machine corresponding to the device module to be reset, and the reset request signal and the power-on reset initial value signal are converted into a reset control signal. Each equipment module to be reset is provided with a corresponding hardware state machine so as to realize the conversion processes of the initial state, the direct software reset, the monostable reset and other states of the reset of each main equipment module. Referring to fig. 5, for example, if the master device module 1 sends a reset request signal and the decoding result indicates that the on-chip bus needs to be reset, the bus monostable reset enable is sent to a corresponding hardware state machine, that is, the bus reset state machine in the figure, and the bus reset state machine performs conversion according to the bus reset initial value of the power-on reset initial value signal, and outputs a reset control signal (that is, a bus reset valid signal) to the on-chip bus to reset the on-chip bus.
In specific implementation, because the logic implementation inside the chip is completed by the transistors integrated in the chip, if the first reset control module (or called the first reset controller) directly resets all the slave device modules, the number of the integrated transistors is increased rapidly, and the design difficulty is increased.
In order to solve the above problem, in a specific embodiment, the reset circuit further includes a second reset control module; a receiving end of the second reset control module configured to input a reset request signal; the output end of the second reset control module is configured to output a reset control signal to an on-chip bus inside the chip; and the second reset control module outputs a reset control signal after receiving the reset request signal and controls the reset operation of the slave equipment module through the on-chip bus.
Specifically, the master device module operates the second reset control module to reset each slave device module in the chip through the bus in the chip, instead of directly using the first reset control module to reset the slave device module, so that the design complexity of the first reset control module can be reduced.
Based on the same inventive concept as the reset circuit, an embodiment of the present invention further provides a reset method applied to the reset circuit, and referring to fig. 6, the method includes:
s11, receiving a reset request signal of the current master equipment module;
specifically, after the master device module sends a reset request signal, the first reset control module may receive the reset request signal of the current master device module, and the master device module sends a reset request to the first reset control module, which may be implemented in a manner specially defined by control software or firmware thereof, without conflicting with normal bus operation. For example, in the GPU system, the MCU master device module uses a specific GPIO (general-purpose input/output), the PCIe master device module uses an FLR (function level reset), and the UART master device module uses a custom special field, which can both bypass the bus and directly send a request to the first reset control module. The process proceeds to step S12 after acquiring the reset request signal.
And S12, outputting a reset control signal according to the current module number of the current master device module and the reset module number of the reset request signal, so as to reset the master device module or the slave device module in the chip.
Specifically, the reset request signal is decoded to determine the number of the reset module, and the reset request signal is output to the corresponding master device module or slave device module to perform the reset operation. The decoding can be completed by a decoding module (or decoder) inside the chip.
In a specific embodiment, outputting the reset control signal according to the current module number of the current master device module and the reset module number of the reset request signal includes:
if the current module number is the same as the number of the reset module, outputting a reset control signal which is a monostable reset signal to reset the current main equipment module; if the current module number is different from the number of the reset module, a reset control signal which is a bistable reset signal is output to reset other main equipment modules.
Specifically, referring to fig. 7, a master device (e.g., reference numeral i) inputs a reset request signal of the first reset control module, and includes a reference numeral (e.g., j) of the master module to be reset. And the first reset control module is input into the decoding module and judges whether the number i of the equipment initiating the reset is equal to the number j of the equipment being reset or not. If i, j are equal, this means that the master device is to reset itself, and then monostable reset is used; if i, j are not equal, this indicates that the master is to reset the other masters, and a bistable reset is used.
In a specific embodiment, after receiving the reset request signal of the current master device module, the method further includes:
and when the reset module number of the reset request signal is a preset set module number, outputting a reset control signal which is a monostable reset signal to reset the slave equipment module.
Specifically, if j is a special module flag after decoding, such as a module that must be reset by a monostable circuit, for example, an on-chip bus itself, a monostable reset signal is sent to the reset module. It can be understood that the monostable reset represents a transient reset mode, and the reset control signal generates a jump edge, that is, triggers the reset operation of the device module to be reset; the bistable state reset representation is a normal reset mode, when the reset control signal continuously keeps the level signal, the reset operation of the equipment module to be reset is triggered, and when the level signal is not kept, the reset operation of the equipment module to be reset is stopped. Through the identification of the reset module number, reset control signals of different reset modes can be output in a targeted manner, so that the applicability of the reset operation of each equipment module in the chip is better.
In a specific embodiment, the reset method further includes: receiving a power-on reset initial value signal outside a chip; determining corresponding initial reset operation according to reset initial values of the reset control signal and the power-on reset initial value signal; and configuring a trigger condition of reset release according to the initial reset operation and the input reset mode.
Specifically, referring to fig. 8, the initial reset operation includes reset release and reset activation, where the reset activation is that the reset control signal of the device module is in an active state, and the device module does not work or enters a low power consumption state; when the reset is released, the reset control signal of the equipment module is in an invalid state, and the equipment module works normally. The reset initial value can be configured through a power-on reset initial value signal input outside the chip so as to determine to execute reset release or reset activation, and after the initial reset operation is completed, a trigger condition of the reset release is configured.
In a specific embodiment, the configuration of the trigger condition of the reset release according to the initial reset operation and the input reset mode comprises the following steps: if the initial reset operation is reset release or reset activation and the reset mode is bistable release reset, outputting a reset control signal to carry out reset activation, and configuring a trigger condition for releasing reset as bistable release reset; if the initial reset operation is reset release or reset activation and the reset mode is monostable release reset, a reset control signal is output to carry out reset activation, and the trigger condition of the release reset is configured to reach the preset duration.
In particular, referring to FIGS. 8-9, the same is meant to characterize the transition process of the hardware state machine. This is explained in the following steps.
(1) The power-on reset is triggered when the chip is powered on, the power-on state is S0, the chip enters S1 (initial release) and S2 (initial activation) according to the external reset initial value, and the chip is reset to output the activation state.
(2) In the state S1, S2, if a bistable active reset input is received, the state S3 is entered; if a monostable active reset input is received, state S4 is entered.
(3) In the state S3, the output is reset active; if a bistable release reset input is received, the state returns to state S1, where the monostable reset input is inactive.
(4) At state S4, a reset activation state is output, and after the hardware is delayed for a configurable period of time, the state returns to state S1.
As shown in the flow chart, it can be concluded that the bistable reset input has a higher priority than the monostable reset input. The state machine for resetting the on-chip bus has the same structure as that of other main equipment reset state machines, and is characterized in that the reset initial value input of the bus reset state machine is fixed in a reset release state, and the bistable reset input is fixed in the reset release state. Preferably, the state S4 is a monostable state (transient state), the holding time, i.e. the time period of the reset activation, can be designed to be configurable by software, the setting of the preset time period is completed by a timer or a delay function, and the specific setting value can be freely set according to the requirement.
Based on the same inventive concept as the reset circuit, the embodiment of the invention also provides a chip, and the chip comprises any one of the reset circuits.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
1. the method comprises the steps that through a first reset control module integrated in a chip, a first receiving end of the first reset control module is configured to receive a reset request signal of a main equipment module in the chip, an output end of the first reset control module is configured to output a reset control signal of the main equipment module or a slave equipment module in the chip, when the main equipment module or the slave equipment module needs to be reset, internal reset command decoding is carried out after the reset request signal is received, reset requests initiated by each main equipment can be analyzed, the reset control signal is correspondingly output to the main equipment module or the slave equipment module needing to be reset, an on-chip bus is not needed in the reset process, and the reliability of normal reset operation of each module equipment in the chip is improved; meanwhile, the reset implementation mode is more flexible, the main equipment module can complete self reset according to the application requirement, reset other main equipment modules and reset the functions of the slave equipment modules, the limitation of reset control in the prior art is eliminated, and various application requirements of complex multi-main equipment modules on a system on a chip for reset can be met.
2. The first reset control module can analyze reset requests initiated by each main equipment module by decoding reset request signals sent by the internal main equipment module, which require software to control stable activation or release states, which require software to initiate reset activation, and hardware is automatically released.
3. The main idea of the application is more innovative, reset control is more flexible, application scenes are more extensive, not only the whole system is automatically reset when being limited to specific functional faults, the reset system is realized on the basis of reset input request decoding and a state machine circuit, the reset system not only has the reset function, but also can be accurately reset by each submodule in a control system which is more convenient for software/firmware, comparison is carried out from specific embodiments, the application is realized in a mode of a state machine in a system on a chip, compared with the circuit realization of an off-chip reset chip, a logic chip and the like in the prior art, and the application has stronger practicability.
Since the electronic device described in this embodiment is an electronic device used for implementing the method for processing information in this embodiment, a person skilled in the art can understand the specific implementation manner of the electronic device of this embodiment and various variations thereof based on the method for processing information described in this embodiment, and therefore, how to implement the method in this embodiment by the electronic device is not described in detail here. Electronic devices used by those skilled in the art to implement the method for processing information in the embodiments of the present application are all within the scope of the present application.
Claims (10)
1. A reset circuit is characterized by comprising a first reset control module integrated in a chip;
a first receiving end of the first reset control module is configured to receive a reset request signal of one or more master device modules inside the chip;
the output end of the first reset control module is configured to output a reset control signal of a master device module or a slave device module inside the chip;
and the first reset control module outputs the reset control signal after receiving the reset request signal, and controls the reset operation of the master equipment module or the slave equipment module after being powered on.
2. The reset circuit of claim 1,
the second receiving end of the first reset control module is configured to receive a power-on reset initial value signal outside the chip;
the first reset control module outputs the reset control signal after receiving the power-on reset initial value signal, and controls the reset initial value when the main equipment module is started.
3. The reset circuit of claim 2,
the first reset control module comprises at least one hardware state machine;
and the hardware state machine outputs the reset control signal after receiving the reset request signal and the power-on reset initial value signal, and correspondingly configures the reset triggering condition of the master equipment module or the slave equipment module.
4. The reset circuit of claim 1, further comprising a second reset control module;
a receiving end of the second reset control module configured to input the reset request signal;
the output end of the second reset control module is configured to output the reset control signal to an on-chip bus inside the chip;
and the second reset control module outputs the reset control signal after receiving the reset request signal and controls the reset operation of the slave equipment module through the on-chip bus.
5. A reset method applied to the reset circuit according to any one of claims 1 to 4, comprising:
receiving a reset request signal of a current master equipment module;
and outputting a reset control signal according to the current module number of the current main equipment module and the reset module number of the reset request signal so as to reset the main equipment module or the slave equipment module in the chip.
6. The reset method of claim 5, wherein outputting a reset control signal according to a current module number of the current master module and a reset module number of the reset request signal comprises:
if the current module number is the same as the reset module number, outputting the reset control signal which is a monostable reset signal to reset the current main equipment module;
if the current module number is different from the reset module number, the reset control signal which is a bistable reset signal is output to reset other main equipment modules.
7. The reset method according to claim 5, wherein after receiving the reset request signal of the current master device module, the method further comprises:
and when the reset module number of the reset request signal is a preset set module number, outputting the reset control signal which is a monostable reset signal to reset the slave equipment module.
8. The reset method according to claim 5, further comprising:
receiving a power-on reset initial value signal outside a chip;
determining corresponding initial reset operation according to the reset control signal and the reset initial value of the power-on reset initial value signal;
and configuring a trigger condition of reset release according to the initial reset operation and the input reset mode.
9. The reset method according to claim 8, wherein the configuring the trigger condition of the reset release according to the initial reset operation and the input reset mode comprises:
if the initial reset operation is reset release or reset activation and the reset mode is bistable release reset, outputting the reset control signal to carry out reset activation, and configuring the trigger condition of the release reset as the bistable release reset;
and if the initial reset operation is reset release or reset activation and the reset mode is monostable release reset, outputting the reset control signal to carry out reset activation, and configuring the trigger condition of the release reset as reaching preset duration.
10. A chip comprising a reset circuit according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210566846.6A CN114661127B (en) | 2022-05-24 | 2022-05-24 | Reset circuit, reset method and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210566846.6A CN114661127B (en) | 2022-05-24 | 2022-05-24 | Reset circuit, reset method and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114661127A true CN114661127A (en) | 2022-06-24 |
| CN114661127B CN114661127B (en) | 2022-09-06 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843436A (en) * | 2017-01-20 | 2017-06-13 | 苏州国芯科技有限公司 | A kind of reset control module and repositioning method |
| CN108011623A (en) * | 2017-12-25 | 2018-05-08 | 杭州魔点科技有限公司 | One-key recovery default setting circuit |
| CN111625075A (en) * | 2020-05-20 | 2020-09-04 | 天津芯海创科技有限公司 | Software configurable reset device and method |
| GB202101560D0 (en) * | 2021-02-04 | 2021-03-24 | Nordic Semiconductor Asa | Reset domain control |
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- 2022-05-24 CN CN202210566846.6A patent/CN114661127B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843436A (en) * | 2017-01-20 | 2017-06-13 | 苏州国芯科技有限公司 | A kind of reset control module and repositioning method |
| CN108011623A (en) * | 2017-12-25 | 2018-05-08 | 杭州魔点科技有限公司 | One-key recovery default setting circuit |
| CN111625075A (en) * | 2020-05-20 | 2020-09-04 | 天津芯海创科技有限公司 | Software configurable reset device and method |
| GB202101560D0 (en) * | 2021-02-04 | 2021-03-24 | Nordic Semiconductor Asa | Reset domain control |
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| CN114661127B (en) | 2022-09-06 |
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