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CN114649295B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN114649295B
CN114649295B CN202011521372.0A CN202011521372A CN114649295B CN 114649295 B CN114649295 B CN 114649295B CN 202011521372 A CN202011521372 A CN 202011521372A CN 114649295 B CN114649295 B CN 114649295B
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Prior art keywords
metal layer
plugs
substrate
plug
layer
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CN202011521372.0A
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Chinese (zh)
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CN114649295A (en
Inventor
熊鹏
李斌
徐一凡
施维
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011521372.0A priority Critical patent/CN114649295B/en
Publication of CN114649295A publication Critical patent/CN114649295A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The structure comprises a substrate, a first metal layer, a plurality of rows of first plugs and a plurality of adjacent rows of first plugs, wherein the first metal layer is arranged on the substrate and comprises a plurality of first areas, the plurality of first areas are uniformly distributed around the central point of the first metal layer, the plurality of rows of first plugs are arranged on the first areas along the direction from the central point to the edge of the first metal layer, the central lines of the two adjacent rows of first plugs are not overlapped, and the central lines pass through the central point. The impact resistance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
With the continuous improvement of the performance of very large scale integrated circuits, the gradual reduction of the device size and the continuous increase of the density, copper and low dielectric constant materials are selected as the back-end metal interconnect and the Inter-metal dielectric (IMD, inter-METAL DIELECTRIC) in the back-end metal process of the semiconductor process to reduce the resistance-capacitance Delay (RC Delay) of the interconnect.
However, the performance of the existing back-end-of-line processes and the semiconductor structures formed thereby remains to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a method for forming the semiconductor structure to improve the performance of the semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a first metal layer arranged on the substrate, a plurality of rows of first plugs arranged on the first region, wherein the first metal layer comprises a plurality of first areas, the plurality of first areas are uniformly distributed around the central point of the first metal layer, the plurality of rows of first plugs are arranged along the direction from the central point to the edge of the first metal layer, the central lines of two adjacent rows of first plugs are not overlapped, and the central line passes through the central point.
Optionally, the first metal layer further includes a plurality of second regions, and the second regions are located between adjacent first regions.
Optionally, the semiconductor device further comprises a plurality of second plugs positioned on the second region, wherein the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer.
Optionally, the shape of the first metal layer projected on the surface of the substrate is rectangular or circular.
Optionally, when the shape of the first metal layer projected on the surface of the substrate is rectangular, the symmetry axis of the second area is a diagonal line of the first metal layer.
Optionally, the pattern of the second plug projected on the surface of the substrate is rectangular.
Optionally, when the pattern of the second plug projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the arrangement direction of the second plug.
Optionally, the pattern of the first plug projected on the surface of the substrate is rectangular.
Optionally, when the pattern of the first plug projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first area.
Optionally, the semiconductor device further comprises a second metal layer positioned on the first plug and the second plug, wherein the second metal layer is electrically connected with the first metal layer through the first plug and the second plug, and a dielectric structure positioned on the substrate, and the first metal layer, the second metal layer, the first plug and the second plug are positioned in the dielectric structure.
Optionally, the semiconductor device further comprises an insulating layer positioned on the second metal layer, an opening positioned in the insulating layer, wherein part of the surface of the second metal layer is exposed by the opening, an electric contact layer positioned in the opening, and an electric connection wire electrically connected with the electric contact layer.
Optionally, the substrate comprises a base, a device layer located on the base, wherein the device layer comprises an isolation structure and a device structure located in the isolation structure, the device structure comprises one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure, and the first metal layer is electrically connected with the device structure.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a first metal layer on the substrate, wherein the first metal layer comprises a plurality of first areas, the plurality of first areas are uniformly distributed around the central point of the first metal layer, a plurality of rows of first plugs are formed on the first areas, the plurality of rows of first plugs are distributed along the direction from the central point to the edge of the first metal layer, the central lines of two adjacent rows of first plugs are not overlapped, and the central line passes through the central point.
Optionally, the first metal layer further includes a plurality of second regions, and the second regions are located between adjacent first regions.
Optionally, forming a plurality of second plugs on the second region, wherein the plurality of second plugs are arranged in parallel from the center point to the edge of the first metal layer.
Optionally, the shape of the first metal layer projected on the surface of the substrate is rectangular or circular.
Optionally, when the shape of the first metal layer projected on the surface of the substrate is rectangular, the symmetry axis of the second area is a diagonal line of the first metal layer.
Optionally, the pattern of the second plug projected on the surface of the substrate is rectangular.
Optionally, when the pattern of the second plug projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the arrangement direction of the second plug.
Optionally, the pattern of the first plug projected on the surface of the substrate is rectangular.
Optionally, when the pattern of the first plug projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first area.
Optionally, a second metal layer is formed on the first plug and the second plug, the second metal layer is electrically connected with the first metal layer through the first plug and the second plug, a dielectric structure is formed on the substrate, and the first metal layer, the second metal layer, the first plug and the second plug are located in the dielectric structure.
Optionally, the method further comprises forming an insulating layer on the second metal layer, forming an opening in the insulating layer, wherein the opening exposes part of the surface of the second metal layer, forming an electric contact layer in the opening, and forming an electric connection wire electrically connected with the electric contact layer.
Optionally, the substrate comprises a base, a device layer located on the base, wherein the device layer comprises an isolation structure and a device structure located in the isolation structure, the device structure comprises one or more of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure, and the first metal layer is electrically connected with the device structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
According to the semiconductor structure disclosed by the technical scheme of the invention, the first metal layer comprises a plurality of first areas, the plurality of first areas are uniformly distributed around the central point of the first metal layer, the first areas are provided with a plurality of rows of first plugs, the first plugs are distributed along the direction from the central point to the edge of the first metal layer, the central lines of two adjacent rows of first plugs are not coincident, and the central lines pass through the central point. Therefore, a plurality of first plugs can be staggered from inside to outside around the central point of the first metal layer, and subsequently when the shear force in the direction parallel to the surface of the substrate is received, the shear force in any direction can be effectively blocked, so that the impact resistance of the first plugs can be enhanced, and the reliability of the semiconductor structure is improved.
Further, the first plug is projected on the surface of the substrate in a rectangular shape, the second plug is projected on the surface of the substrate in a rectangular shape, and the rectangle has a larger surface area, so that the first plug and the second plug can have a larger stress area in the direction parallel to the surface of the substrate, the impact resistance of the first plug and the second plug can be enhanced, and the reliability of the semiconductor structure is improved.
Further, the second plugs are arranged in parallel from the center point to the edge of the first metal layer. Therefore, the second plug and the first plug can have larger stress areas in all directions parallel to the surface of the substrate, so that the impact resistance of the second plug and the first plug can be enhanced, and the reliability of the semiconductor structure is improved.
Drawings
FIGS. 1 and 2 are schematic cross-sectional and top views of a semiconductor structure in one embodiment;
FIGS. 3-8 are schematic cross-sectional and top views illustrating a semiconductor structure formation process in accordance with one embodiment of the present invention;
Figure 9 is a top view of a semiconductor structure in another embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing back-end-of-line process and the semiconductor structure formed thereby is still to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 and 2 are schematic cross-sectional and top views of a semiconductor structure in one embodiment.
Referring to fig. 1 and 2, fig. 1 is a schematic cross-sectional structure of a semiconductor structure, fig. 2 is a top view of the semiconductor structure, fig. 1 omitting a connection structure, an insulating layer 106, an electrical contact layer 107, a second metal layer 105 and a dielectric structure 104, including a substrate 100, a device layer 101 on the substrate 100, the device layer 101 including an isolation structure (not shown) and a device structure (not shown) within the isolation structure, the device structure including one or more of a transistor, a diode, a transistor, a capacitor, an inductor and a conductive structure, a first metal layer 102 on the device layer 101, a plurality of plugs 103 on the first metal layer 102, a second metal layer 105 on the plurality of plugs 103, a dielectric structure 104 on the device layer 101, the first metal layer 102, the plugs 103 and the second metal layer 105 being located within the dielectric structure 104, an insulating layer 106 on the dielectric structure 104 and a device layer 108 within the isolation structure, the electrical contact layer 107 being electrically connected to the second metal layer 105, the electrical contact layer 107 being electrically connected to the connection structure 107 and the connection structure including the connection layer 109.
In the semiconductor structure, the pattern of the plugs 103 projected onto the substrate 100 is generally circular, and a plurality of the plugs 103 are generally arranged in an array on the first metal layer 102. The dielectric structure 104 is typically a low K dielectric material to reduce parasitic capacitance of the semiconductor structure. In forming the connection structure electrically connected to the electrical contact layer 107, the material of the connection layer 108 is typically solder for connecting the connection wire 109 to the electrical contact layer 107.
However, during the spot welding, the solder strip cannot be brought into contact with the electrical contact layer 107 in a direction perpendicular to the surface of the substrate 100, and thus the force of the spot welding is not at right angles to the surface of the electrical contact layer 107, and thus the force of the spot welding is decomposed into two shearing forces in a direction perpendicular to the surface of the substrate 100 and a direction parallel to the surface of the substrate 100. When a shearing force in a direction parallel to the surface of the substrate 100 acts on the semiconductor structure, on one hand, the low-K dielectric material of the dielectric structure 104 is more porous, so that the material of the dielectric structure 104 is more brittle, the dielectric structure 104 is easy to break and delaminate under the action of the shearing force in the direction parallel to the surface of the substrate 100, and on the other hand, since the pattern of the plugs 103 projected on the substrate 100 is circular, and a plurality of the plugs 103 are generally arranged in an array on the first metal layer 102, the stress area of the plugs 103 is smaller, so that the pressure born by the plugs 103 is larger, and in both cases, the plugs 103 and the dielectric structure 104 are easy to delaminate, thereby affecting the performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure, where the first metal layer includes a plurality of first regions, the plurality of first regions are uniformly distributed around a central point of the first metal layer, the first regions are provided with a plurality of rows of first plugs, the plurality of rows of first plugs are arranged along a direction from the central point to an edge of the first metal layer, central lines of two adjacent rows of first plugs are not coincident, and the central lines pass through the central point. Therefore, a plurality of first plugs can be staggered from inside to outside around the central point of the first metal layer, and subsequently when the shear force in the direction parallel to the surface of the substrate is received, the shear force in any direction can be effectively blocked, so that the impact resistance of the first plugs can be enhanced, and the reliability of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3-8 are schematic cross-sectional views and top views of a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 3, a substrate is provided.
The substrate includes a base 200, a device layer 201 on the base 200, the device layer 201 including an isolation structure (not shown) and a device structure (not shown) within the isolation structure, the device structure including a combination of one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Referring to fig. 4 and 5, fig. 5 is a top view of the first metal layer 202 in fig. 4, the first metal layer 202 is formed on a substrate, and the first metal layer 202 includes a plurality of first regions I, and the plurality of first regions I are uniformly distributed around a center point O of the first metal layer 202.
The first metal layer 202 is electrically connected to the device structure.
In this embodiment, the first metal layer 202 further includes a plurality of second regions II, where the second regions II are located between adjacent first regions I.
The first metal layer 202 is projected on the surface of the substrate and has a rectangular or circular shape.
In this embodiment, when the shape of the first metal layer 202 projected on the substrate surface is rectangular, the symmetry axis of the second region II is the diagonal line of the first metal layer 202.
The first regions I are uniformly distributed around the center point O of the first metal layer 202, and the number of the first regions I is at least 2.
In this embodiment, the first metal layer 202 is projected on the surface of the substrate in a rectangular shape, and the number of the first areas I is 4.
In other embodiments, the shape of the first metal layer projected on the surface of the substrate is a circle, and the number of the first areas I is a plurality.
The material of the first metal layer 202 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.
The method for forming the first metal layer 202 includes forming a first dielectric layer (not shown) on a substrate, forming a first groove (not shown) in the first dielectric layer, wherein the first groove exposes the surface of the device structure, forming a first metal material layer (not shown) in the first groove and on the first dielectric layer, and planarizing the first metal material layer until the surface of the substrate is exposed, thereby forming the first metal layer 202.
The material of the first dielectric layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride.
In this embodiment, the dielectric constant of the material of the first dielectric layer is less than 2.8. The dielectric constant of the material of the first dielectric layer is smaller, so that parasitic capacitance of the semiconductor structure can be reduced, and performance of the semiconductor structure is improved.
Referring to fig. 6 and 7, fig. 7 is a top view showing the distribution of the first plugs 203 and the second plugs on the first metal layer 202 in fig. 6, wherein the second dielectric layer 204 is omitted, a plurality of rows of first plugs 203 are formed on the first region I, the plurality of rows of first plugs 203 are arranged along the direction from the center point O to the edge of the first metal layer 202, the center lines of two adjacent rows of first plugs 203 are not coincident, the center lines pass through the center point O, a plurality of second plugs 205 are formed on the second region II, and the plurality of second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202.
The first plugs 203 in the arrangement mode can surround the center point O of the first metal layer 202 from inside to outside in a staggered manner, and then when the shear force in the direction parallel to the surface of the substrate is received, the shear force in any direction can be effectively blocked, so that the impact resistance of the first plugs 203 can be enhanced, the reliability of the semiconductor structure is improved, and the second plugs 205 and the first plugs 203 in the arrangement mode can have larger stress areas in all directions parallel to the surface of the substrate, so that the impact resistance of the second plugs 205 and the first plugs 203 can be enhanced, and the reliability of the semiconductor structure is improved.
In this embodiment, the pattern of the first plug 203 projected on the surface of the substrate is rectangular. The rectangle has a larger surface area, so that the first plug 203 can have a larger stress area in a direction parallel to the substrate surface, so that the impact resistance of the first plug 203 can be enhanced, thereby improving the reliability of the semiconductor structure.
In this embodiment, the pattern of the second plug 205 projected on the surface of the substrate is rectangular. The rectangle has a larger surface area, so that the second plug 205 can have a larger stress area in a direction parallel to the substrate surface, so that the impact resistance of the second plug 205 can be enhanced, thereby improving the reliability of the semiconductor structure.
When the pattern of the first plug 203 projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first area I.
When the pattern of the second plug 205 projected on the surface of the substrate is rectangular, the long side of the rectangle is perpendicular to the arrangement direction of the second plug 205.
In this embodiment, the first plug 203 and the second plug 205 are formed simultaneously. In other embodiments, the first plug and the second plug can be formed at different times.
The method for forming the first plug 203 and the second plug 205 includes forming a second dielectric layer 204 on the first dielectric layer and on the first metal layer 202, forming a second groove (not shown) in the second dielectric layer 204, wherein the second groove exposes the surface of the first metal layer 202, forming a plug material layer (not shown) in the second groove and on the second dielectric layer 204, and planarizing the plug material layer until the surface of the second dielectric layer 204 is exposed, thereby forming the first plug 203 and the second plug 205.
The material of the first plug 203 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum. The material of the second plug 205 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum. The second plug 205 is located within the second dielectric layer 204.
The material of the second dielectric layer 204 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride.
In this embodiment, the dielectric constant of the material of the second dielectric layer 204 is less than 2.8. The dielectric constant of the material of the second dielectric layer 204 is smaller, so that parasitic capacitance of the semiconductor structure can be reduced, and performance of the semiconductor structure can be improved.
Referring to fig. 8, a second metal layer 206 is formed on the first plug 203 and the second plug 205, and the second metal layer 206 is electrically connected to the first metal layer 202 through the first plug 203 and the second plug 205.
The second metal layer 206 is formed by forming a third dielectric layer (not shown) on the second dielectric layer 204, on the first plug 203 and on the second plug 205, forming a third groove (not shown) in the third dielectric layer, wherein the third groove exposes the surfaces of the first plug 203 and the second plug 205, forming a second metal material layer (not shown) in the third groove and on the third dielectric layer, and planarizing the second metal material layer until the surface of the third dielectric layer is exposed, thereby forming the second metal layer 206.
The material of the second metal layer 206 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.
The material of the third dielectric layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride.
In this embodiment, a dielectric constant of a material of the third dielectric layer is less than 2.8. The dielectric constant of the material of the third dielectric layer is smaller, so that parasitic capacitance of the semiconductor structure can be reduced, and performance of the semiconductor structure is improved.
The first dielectric layer, the second dielectric layer 204, and the third dielectric layer form a dielectric structure.
With continued reference to fig. 8, an insulating layer 207 is formed over the second metal layer 206, an opening (not shown) is formed in the insulating layer 207 exposing a portion of the surface of the second metal layer 206, an electrical contact layer 208 is formed in the opening, and an electrically conductive connection line 210 is formed in electrical contact with the electrical contact layer 208.
The material of the electrical contact layer 208 comprises a metal comprising copper.
The electrically conductive connection lines 210 are used for electrical connection between electrically conductive devices in a semiconductor package.
In this embodiment, the conductive connection line 210 is electrically connected to the electrical contact layer 208 through a solder ball 209. The material of the solder balls 209 includes tin.
Since the plurality of first plugs 203 can be staggered from inside to outside around the center point O of the first metal layer 202, and the plurality of second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202, when the solder balls 209 are formed on the electrical contact layer 208, the semiconductor structure is subjected to a shearing force in a direction parallel to the surface of the substrate, and the first plugs 203 and the second plugs 205 can effectively block the shearing force in any direction, so that the impact resistance of the first plugs 203 and the second plugs 205 can be enhanced, and the reliability of the semiconductor structure is improved.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 8, including:
A substrate;
a first metal layer 202 located on the substrate, wherein the first metal layer 202 includes a plurality of first regions I, and the plurality of first regions I are uniformly distributed around a center point O of the first metal layer 202;
And a plurality of rows of first plugs 203 positioned on the first region I, wherein the rows of first plugs 203 are arranged along the direction from the center point O to the edge of the first metal layer 202, the central lines of two adjacent rows of first plugs 203 are not coincident, and the central line passes through the center point O.
In this embodiment, the first metal layer 202 further includes a plurality of second regions II, where the second regions II are located between adjacent first regions I.
In this embodiment, the second plugs 205 are located on the second region II, and the second plugs 205 are arranged in parallel from the center point O to the edge of the first metal layer 202.
In this embodiment, the shape of the first metal layer 202 projected on the surface of the substrate is rectangular or circular.
In this embodiment, when the shape of the first metal layer 202 projected on the substrate surface is rectangular, the symmetry axis of the second region II is the diagonal line of the first metal layer 202.
In this embodiment, the pattern of the second plug 205 projected on the surface of the substrate is rectangular.
In this embodiment, when the pattern of the second plug 205 projected onto the substrate surface is rectangular, the long side of the rectangle is perpendicular to the arrangement direction of the second plug 205.
In this embodiment, the pattern of the first plug 203 projected on the surface of the substrate is rectangular.
In this embodiment, when the pattern of the first plug 203 projected on the substrate surface is rectangular, the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first region I.
In this embodiment, the semiconductor device further comprises a second metal layer 206 located on the first plug 203 and the second plug 205, wherein the second metal layer 206 is electrically connected with the first metal layer 202 through the first plug 203 and the second plug 205, and a dielectric structure located on the substrate, wherein the first metal layer 202, the second metal layer 206, the first plug 203 and the second plug 205 are located in the dielectric structure.
In this embodiment, the semiconductor device further comprises an insulating layer 207 positioned on the second metal layer 206, an opening positioned in the insulating layer 207, the opening exposing a part of the surface of the second metal layer 206, an electrical contact layer 208 positioned in the opening, and an electrically conductive connection line 210 electrically connected with the electrical contact layer 208.
In this embodiment, the substrate comprises a base 200, a device layer 201 located on the base, wherein the device layer 201 comprises an isolation structure and a device structure located in the isolation structure, the device structure comprises one or a combination of a transistor, a diode, a triode, a capacitor, an inductor and a conductive structure, and the first metal layer is electrically connected with the device structure.
The semiconductor structure includes a plurality of first regions I, wherein the plurality of first regions I are uniformly distributed around a center point O of the first metal layer 202, the first regions I have a plurality of rows of first plugs 203, the plurality of rows of first plugs 203 are arranged along a direction from the center point O to an edge of the first metal layer 202, center lines of two adjacent rows of first plugs 203 are not coincident, and the center line passes through the center point O. Therefore, the plurality of first plugs 203 can be staggered from inside to outside around the center point O of the first metal layer 202, and then when receiving a shearing force in a direction parallel to the surface of the substrate, the shearing force in any direction can be effectively blocked, so that the impact resistance of the first plugs 203 can be enhanced, and the reliability of the semiconductor structure is improved.
Further, the pattern of the first plug 203 projected on the surface of the substrate is rectangular, the pattern of the second plug 205 projected on the surface of the substrate is rectangular, and the rectangle has a larger surface area, so that the first plug 203 and the second plug 205 can have a larger stress area in the direction parallel to the surface of the substrate, thereby enhancing the impact resistance of the first plug 203 and the second plug 205, and improving the reliability of the semiconductor structure.
Further, a plurality of the second plugs 205 are arranged in parallel from the center point O toward the edge of the first metal layer 202. Therefore, the second plug 205 and the first plug 203 can have larger stress areas in all directions parallel to the surface of the substrate, so that the impact resistance of the second plug 205 and the first plug 203 can be enhanced, and the reliability of the semiconductor structure is improved.
Figure 9 is a top view of a semiconductor structure in another embodiment of the present invention.
Referring to fig. 9, a first metal layer 302 is formed on a substrate, where the first metal layer 302 includes a plurality of first regions I uniformly distributed around a center point O of the first metal layer 302, and the first metal layer 302 further includes a plurality of second regions II located between adjacent first regions I.
In this embodiment, the shape of the first metal layer 302 projected on the surface of the substrate is circular. At this time, the symmetry axis of the second region II is the radius of the first metal layer 302. The first areas I are evenly distributed around the central point O of the first metal layer 302, the number of first areas I being several, 4 being schematically shown.
The method for forming the first metal layer 302 is shown in fig. 4 and fig. 5, and will not be described herein.
In other embodiments, the shape of the first metal layer projected on the surface of the substrate may be any desired pattern, such as oval, etc.
With continued reference to fig. 9, a plurality of rows of first plugs 303 are formed in the first region I, the rows of first plugs 303 are arranged along the direction from the center point O to the edge of the first metal layer 302, the center lines of two adjacent rows of first plugs 303 are not coincident, the center lines pass through the center point O, a plurality of second plugs 305 are formed in the second region II, and the plurality of second plugs 305 are arranged in parallel from the center point O to the edge of the first metal layer 302.
The formation process of the first plug 303 and the second plug 305 is shown in fig. 6 and 7, and will not be described herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A semiconductor structure, comprising:
A substrate;
The first metal layer is positioned on the substrate and comprises a plurality of first areas and a plurality of second areas, the first areas are uniformly distributed around the central point of the first metal layer, and the second areas are positioned between the adjacent first areas;
The first plugs are arranged along the direction from the central point to the edge of the first metal layer, the central lines of two adjacent rows of first plugs are not overlapped, the central lines pass through the central point, the pattern of the first plugs projected on the surface of the substrate is rectangular, and the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first region;
The second plugs are arranged in parallel from the center point to the edge of the first metal layer, the patterns of the second plugs projected on the surface of the substrate are rectangular, the long sides of the rectangular are perpendicular to the arrangement direction of the second plugs, and the arrangement modes of the second plugs and the first plugs are different.
2. The semiconductor structure of claim 1, wherein the first metal layer is rectangular or circular in shape projected onto the substrate surface.
3. The semiconductor structure of claim 2, wherein when the first metal layer is projected onto the substrate surface in a rectangular shape, the symmetry axis of the second region is a diagonal of the first metal layer.
4. The semiconductor structure of claim 1, further comprising a second metal layer on the first plug and the second plug, the second metal layer electrically connected to the first metal layer through the first plug and the second plug, and a dielectric structure on the substrate, the first metal layer, the second metal layer, the first plug, and the second plug being located within the dielectric structure.
5. The semiconductor structure of claim 4, further comprising an insulating layer over the second metal layer, an opening in the insulating layer exposing a portion of a surface of the second metal layer, an electrical contact layer in the opening, and an electrically conductive connection line electrically connected to the electrical contact layer.
6. The semiconductor structure of claim 1, wherein the substrate comprises a base, a device layer on the base, the device layer comprising an isolation structure and a device structure within the isolation structure, the device structure comprising a combination of one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure, the first metal layer being electrically connected to the device structure.
7. A method of forming a semiconductor structure, comprising:
Providing a substrate;
forming a first metal layer on a substrate, wherein the first metal layer comprises a plurality of first areas and a plurality of second areas, the first areas are uniformly distributed around the central point of the first metal layer, and the second areas are positioned between adjacent first areas;
Forming a plurality of rows of first plugs on a first area, wherein the first plugs are distributed along the direction from the central point to the edge of the first metal layer, the central lines of two adjacent rows of first plugs are not overlapped, the central lines pass through the central point, the pattern of the first plugs projected on the surface of the substrate is rectangular, and the long side of the rectangle is perpendicular to the direction of the symmetry axis of the first area;
and forming a plurality of second plugs on the second area, wherein the second plugs are arranged in parallel from the central point to the edge of the first metal layer, the pattern of the second plugs projected on the surface of the substrate is rectangular, the long sides of the rectangle are perpendicular to the arrangement direction of the second plugs, and the arrangement modes of the second plugs and the first plugs are different.
8. The method of claim 7, wherein the first metal layer is projected onto the substrate surface in a rectangular or circular shape.
9. The method of claim 8, wherein when the first metal layer is projected onto the substrate surface in a rectangular shape, the symmetry axis of the second region is a diagonal line of the first metal layer.
10. The method of forming a semiconductor structure of claim 7, further comprising forming a second metal layer over the first plug and the second plug, the second metal layer being electrically connected to the first metal layer through the first plug and the second plug, forming a dielectric structure over the substrate, the first metal layer, the second metal layer, the first plug, and the second plug being within the dielectric structure.
11. The method of forming a semiconductor structure as claimed in claim 10, further comprising forming an insulating layer over the second metal layer, forming an opening in the insulating layer, the opening exposing a portion of a surface of the second metal layer, forming an electrical contact layer in the opening, and forming a conductive connection line electrically connected to the electrical contact layer.
12. The method of forming a semiconductor structure of claim 7, wherein the substrate comprises a base, a device layer on the base, the device layer comprising an isolation structure and a device structure within the isolation structure, the device structure comprising a combination of one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure, the first metal layer being electrically connected to the device structure.
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Citations (1)

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Publication number Priority date Publication date Assignee Title
US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process

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US6552438B2 (en) * 1998-06-24 2003-04-22 Samsung Electronics Co. Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same
JP2007149931A (en) * 2005-11-28 2007-06-14 Renesas Technology Corp Semiconductor device, and method of manufacturing same
KR101184375B1 (en) * 2010-05-10 2012-09-20 매그나칩 반도체 유한회사 Semiconductor device preventing crack occurrence in pad region and method for fabricating the same
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US5700735A (en) * 1996-08-22 1997-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bond pad structure for the via plug process

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